Patent
Atlas literature
Patent
US 11,728,415 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a vertical-fin-based field effect transistor (FET) device according to an embodi- ment of the present disclosure.
FIG. 2 is a simplified cross-sectional view of a vertical- fin-based FET device illustrating current flow from a lateral direction along a two-dimensional …
FIG. 3 is a simplified flowchart of a method of fabricating a vertical-fin-based FET device according to an embodiment of the present disclosure.
FIG. 4U are cross-sectional views show- ing intermediate stages of a method of fabricating a vertical- fin-based FET device that can be applied to the first and …
FIG. 5 is a simulation structure of a vertical-fin-based FET device having a 0.2 µm fin thickness.
FIG. 6 is a graph illustrating a threshold voltage (in V) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 7 is a graph illustrating an electric field E (in MV/cm) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 8 is a graph illustrating channel leakage (in A) of a vertical-fin-based FET device as a function of an etch offset 5 (in µm).
FIG. 9B is a graph illustrating a current density for a 0.1 µm overetch. 10
FIG. 10B is a graph illustrating an electric field at the gate corner for a 0.1 µm underetch.
FIG. 11 is a graph illustrating the on-resistance Ron as a 20 function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 12 is a graph illustrating a threshold voltage Vt (V) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer. 25
FIG. 13 is a graph illustrating a maximum electric field (MV/cm) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 14 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation 30 (µm) for the 0.2 µm graded epitaxial …
FIG. 15 is a graph illustrating the on-resistance Ron (mΩ) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 16 is a graph illustrating a threshold voltage Vt (V) 35 as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 17 is a graph illustrating an electric field (MV/cm) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer. 40
FIG. 18 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation (µm) for the 0.3 µm graded epitaxial …
FIG. 19B is a graph illustrating an effect of the polariza- tion charge predicted to result at the c-plane In0.15Ga0.85N/GaN interface according to some …
FIG. 20B is a graph illustrating an effect of an electric field predicted to result at the c-plane In0.15Ga0.85N/GaN 55 interface according to some embodiments …
FIG. 21C is a graph of current density through the channel 65 of the baseline FET compared with that of the non-polar FET. B₂
FIG. 22J are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 23G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 24G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 60 18, the high-voltage drain leakage current Idss was well controlled over the simulated etch range. In summary, the inventors have determined that using …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming an alignment contact, the method comprising: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a plurality of III-nitride fins on the first III-nitride layer, wherein each the plurality of III-nitride fins is separated by one of a plurality of first recess regions and characterized by a fin surface, wherein the plurality of III-nitride fins are characterized by the first conduc-tivity type; forming a III-nitride gate layer disposed between adjacent III-nitride fins of the plurality of III-nitride fins, wherein a surface of the III-nitride gate layer is substantially coplanar with the fin surface; epitaxially regrowing a III-nitride source contact portion on each of the plurality of III-nitride fins; and forming a source contact structure on the III-nitride source contact portions.
The method of claim 1 wherein the III-nitride substrate comprises an n-GaN substrate.
The method of claim 1 wherein the first III-nitride layer and the plurality of III-nitride fins comprise an n-GaN epitaxial layer.
The method of claim 1, further comprising, prior to forming the plurality of III-nitride fins, forming a hardmask on the fin surface of each of the plurality of III-nitride fins.
The method of claim 1 wherein sidewalls of each of the plurality of III-nitride fins are aligned with an m-plane and the fin surface is aligned with a c-plane.
The method of claim 1 wherein epitaxially regrowing the III-nitride source contact portion comprises performing a self-limiting growth process on top of each of the plurality of III-nitride fins and the epitaxially regrown III-nitride B₂ source contact portion is characterized by an isosceles triangle shape having a base angle in a range between 58 degrees and 65 degrees in a cross-section view.
A method for forming an alignment contact, the method comprising: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a first hardmask layer on the first III-nitride layer; forming a plurality of III-nitride fins on the first III-nitride layer using the first hardmask layer as a mask, wherein each of the plurality of III-nitride fins are separated by one of a plurality of first recess regions and character-ized by a fin surface, wherein the plurality of III-nitride fins are characterized by the first conductivity type; epitaxially growing a III-nitride gate layer having a sec-ond conductivity type opposite to the first conductivity type in the plurality of first recess regions, wherein a surface of the III-nitride gate layer is substantially coplanar with the fin surface; forming a first dielectric layer on the first hardmask layer and the III-nitride gate layer, wherein the first dielectric layer comprises a contact region aligned with each of the plurality of III-nitride fins and a gate region aligned with the III-nitride gate layer; forming a photoresist layer on the gate region of the first dielectric layer; etching the contact region of the first dielectric layer using the photoresist layer as a mask to form a second recess region, wherein an upper surface of each of the plural-ity of the III-nitride fins and a portion of upper surface of the III-nitride gate layer surrounding each of the plurality of III-nitride fins are exposed from a bottom surface of the second recess region; removing the photoresist layer; epitaxially regrowing a III-nitride source contact portion in the second recess region; and removing the first dielectric layer.
The method of claim 7 wherein a width of the contact region is at least three times of that of a width of each of the plurality of III-nitride fins.
The method of claim 7, further comprising: forming a source metal mask layer having an opening aligned with the III-nitride source contact portion on each of the plurality of III-nitride fins; forming a first source metal layer coupled to the III-nitride source contact portion; forming a second source metal layer coupled to the first source metal layer; forming a third source metal layer coupled to the second source metal layer; and removing the source metal mask layer.
The method of claim 7 wherein epitaxially regrowing the III-nitride source contact portion comprises performing a self-limiting growth process on top of each of the plurality of III-nitride fins.
The method of claim 7 wherein the III-nitride source contact portion is characterized by an isosceles triangle shape having a base angle in a range between 58 degrees and 65 degrees in a cross-section view.
The method of claim 7 wherein the III-nitride gate layer is disposed in the plurality of first recess regions between adjacent III-nitride fins of the plurality of III-nitride fins. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical fin-based field effect transistor (FET)
Materials described outside the worked examples.
III-nitride substrate
III-nitride gate layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view of a vertical-fin-based field effect transistor (FET) device according to an embodi- ment of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.7–0.8 µm | — |
Temperature |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,728,415 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a vertical-fin-based field effect transistor (FET) device according to an embodi- ment of the present disclosure.
FIG. 2 is a simplified cross-sectional view of a vertical- fin-based FET device illustrating current flow from a lateral direction along a two-dimensional …
FIG. 3 is a simplified flowchart of a method of fabricating a vertical-fin-based FET device according to an embodiment of the present disclosure.
FIG. 4U are cross-sectional views show- ing intermediate stages of a method of fabricating a vertical- fin-based FET device that can be applied to the first and …
FIG. 5 is a simulation structure of a vertical-fin-based FET device having a 0.2 µm fin thickness.
FIG. 6 is a graph illustrating a threshold voltage (in V) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 7 is a graph illustrating an electric field E (in MV/cm) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 8 is a graph illustrating channel leakage (in A) of a vertical-fin-based FET device as a function of an etch offset 5 (in µm).
FIG. 9B is a graph illustrating a current density for a 0.1 µm overetch. 10
FIG. 10B is a graph illustrating an electric field at the gate corner for a 0.1 µm underetch.
FIG. 11 is a graph illustrating the on-resistance Ron as a 20 function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 12 is a graph illustrating a threshold voltage Vt (V) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer. 25
FIG. 13 is a graph illustrating a maximum electric field (MV/cm) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 14 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation 30 (µm) for the 0.2 µm graded epitaxial …
FIG. 15 is a graph illustrating the on-resistance Ron (mΩ) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 16 is a graph illustrating a threshold voltage Vt (V) 35 as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 17 is a graph illustrating an electric field (MV/cm) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer. 40
FIG. 18 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation (µm) for the 0.3 µm graded epitaxial …
FIG. 19B is a graph illustrating an effect of the polariza- tion charge predicted to result at the c-plane In0.15Ga0.85N/GaN interface according to some …
FIG. 20B is a graph illustrating an effect of an electric field predicted to result at the c-plane In0.15Ga0.85N/GaN 55 interface according to some embodiments …
FIG. 21C is a graph of current density through the channel 65 of the baseline FET compared with that of the non-polar FET. B₂
FIG. 22J are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 23G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 24G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 60 18, the high-voltage drain leakage current Idss was well controlled over the simulated etch range. In summary, the inventors have determined that using …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming an alignment contact, the method comprising: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a plurality of III-nitride fins on the first III-nitride layer, wherein each the plurality of III-nitride fins is separated by one of a plurality of first recess regions and characterized by a fin surface, wherein the plurality of III-nitride fins are characterized by the first conduc-tivity type; forming a III-nitride gate layer disposed between adjacent III-nitride fins of the plurality of III-nitride fins, wherein a surface of the III-nitride gate layer is substantially coplanar with the fin surface; epitaxially regrowing a III-nitride source contact portion on each of the plurality of III-nitride fins; and forming a source contact structure on the III-nitride source contact portions.
The method of claim 1 wherein the III-nitride substrate comprises an n-GaN substrate.
The method of claim 1 wherein the first III-nitride layer and the plurality of III-nitride fins comprise an n-GaN epitaxial layer.
The method of claim 1, further comprising, prior to forming the plurality of III-nitride fins, forming a hardmask on the fin surface of each of the plurality of III-nitride fins.
The method of claim 1 wherein sidewalls of each of the plurality of III-nitride fins are aligned with an m-plane and the fin surface is aligned with a c-plane.
The method of claim 1 wherein epitaxially regrowing the III-nitride source contact portion comprises performing a self-limiting growth process on top of each of the plurality of III-nitride fins and the epitaxially regrown III-nitride B₂ source contact portion is characterized by an isosceles triangle shape having a base angle in a range between 58 degrees and 65 degrees in a cross-section view.
A method for forming an alignment contact, the method comprising: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a first hardmask layer on the first III-nitride layer; forming a plurality of III-nitride fins on the first III-nitride layer using the first hardmask layer as a mask, wherein each of the plurality of III-nitride fins are separated by one of a plurality of first recess regions and character-ized by a fin surface, wherein the plurality of III-nitride fins are characterized by the first conductivity type; epitaxially growing a III-nitride gate layer having a sec-ond conductivity type opposite to the first conductivity type in the plurality of first recess regions, wherein a surface of the III-nitride gate layer is substantially coplanar with the fin surface; forming a first dielectric layer on the first hardmask layer and the III-nitride gate layer, wherein the first dielectric layer comprises a contact region aligned with each of the plurality of III-nitride fins and a gate region aligned with the III-nitride gate layer; forming a photoresist layer on the gate region of the first dielectric layer; etching the contact region of the first dielectric layer using the photoresist layer as a mask to form a second recess region, wherein an upper surface of each of the plural-ity of the III-nitride fins and a portion of upper surface of the III-nitride gate layer surrounding each of the plurality of III-nitride fins are exposed from a bottom surface of the second recess region; removing the photoresist layer; epitaxially regrowing a III-nitride source contact portion in the second recess region; and removing the first dielectric layer.
The method of claim 7 wherein a width of the contact region is at least three times of that of a width of each of the plurality of III-nitride fins.
The method of claim 7, further comprising: forming a source metal mask layer having an opening aligned with the III-nitride source contact portion on each of the plurality of III-nitride fins; forming a first source metal layer coupled to the III-nitride source contact portion; forming a second source metal layer coupled to the first source metal layer; forming a third source metal layer coupled to the second source metal layer; and removing the source metal mask layer.
The method of claim 7 wherein epitaxially regrowing the III-nitride source contact portion comprises performing a self-limiting growth process on top of each of the plurality of III-nitride fins.
The method of claim 7 wherein the III-nitride source contact portion is characterized by an isosceles triangle shape having a base angle in a range between 58 degrees and 65 degrees in a cross-section view.
The method of claim 7 wherein the III-nitride gate layer is disposed in the plurality of first recess regions between adjacent III-nitride fins of the plurality of III-nitride fins. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical fin-based field effect transistor (FET)
Materials described outside the worked examples.
III-nitride substrate
III-nitride gate layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view of a vertical-fin-based field effect transistor (FET) device according to an embodi- ment of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.7–0.8 µm | — |
Temperature |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,728,415 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a vertical-fin-based field effect transistor (FET) device according to an embodi- ment of the present disclosure.
FIG. 2 is a simplified cross-sectional view of a vertical- fin-based FET device illustrating current flow from a lateral direction along a two-dimensional …
FIG. 3 is a simplified flowchart of a method of fabricating a vertical-fin-based FET device according to an embodiment of the present disclosure.
FIG. 4U are cross-sectional views show- ing intermediate stages of a method of fabricating a vertical- fin-based FET device that can be applied to the first and …
FIG. 5 is a simulation structure of a vertical-fin-based FET device having a 0.2 µm fin thickness.
FIG. 6 is a graph illustrating a threshold voltage (in V) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 7 is a graph illustrating an electric field E (in MV/cm) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 8 is a graph illustrating channel leakage (in A) of a vertical-fin-based FET device as a function of an etch offset 5 (in µm).
FIG. 9B is a graph illustrating a current density for a 0.1 µm overetch. 10
FIG. 10B is a graph illustrating an electric field at the gate corner for a 0.1 µm underetch.
FIG. 11 is a graph illustrating the on-resistance Ron as a 20 function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 12 is a graph illustrating a threshold voltage Vt (V) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer. 25
FIG. 13 is a graph illustrating a maximum electric field (MV/cm) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 14 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation 30 (µm) for the 0.2 µm graded epitaxial …
FIG. 15 is a graph illustrating the on-resistance Ron (mΩ) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 16 is a graph illustrating a threshold voltage Vt (V) 35 as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 17 is a graph illustrating an electric field (MV/cm) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer. 40
FIG. 18 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation (µm) for the 0.3 µm graded epitaxial …
FIG. 19B is a graph illustrating an effect of the polariza- tion charge predicted to result at the c-plane In0.15Ga0.85N/GaN interface according to some …
FIG. 20B is a graph illustrating an effect of an electric field predicted to result at the c-plane In0.15Ga0.85N/GaN 55 interface according to some embodiments …
FIG. 21C is a graph of current density through the channel 65 of the baseline FET compared with that of the non-polar FET. B₂
FIG. 22J are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 23G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 24G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 60 18, the high-voltage drain leakage current Idss was well controlled over the simulated etch range. In summary, the inventors have determined that using …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming an alignment contact, the method comprising: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a plurality of III-nitride fins on the first III-nitride layer, wherein each the plurality of III-nitride fins is separated by one of a plurality of first recess regions and characterized by a fin surface, wherein the plurality of III-nitride fins are characterized by the first conduc-tivity type; forming a III-nitride gate layer disposed between adjacent III-nitride fins of the plurality of III-nitride fins, wherein a surface of the III-nitride gate layer is substantially coplanar with the fin surface; epitaxially regrowing a III-nitride source contact portion on each of the plurality of III-nitride fins; and forming a source contact structure on the III-nitride source contact portions.
The method of claim 1 wherein the III-nitride substrate comprises an n-GaN substrate.
The method of claim 1 wherein the first III-nitride layer and the plurality of III-nitride fins comprise an n-GaN epitaxial layer.
The method of claim 1, further comprising, prior to forming the plurality of III-nitride fins, forming a hardmask on the fin surface of each of the plurality of III-nitride fins.
The method of claim 1 wherein sidewalls of each of the plurality of III-nitride fins are aligned with an m-plane and the fin surface is aligned with a c-plane.
The method of claim 1 wherein epitaxially regrowing the III-nitride source contact portion comprises performing a self-limiting growth process on top of each of the plurality of III-nitride fins and the epitaxially regrown III-nitride B₂ source contact portion is characterized by an isosceles triangle shape having a base angle in a range between 58 degrees and 65 degrees in a cross-section view.
A method for forming an alignment contact, the method comprising: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a first hardmask layer on the first III-nitride layer; forming a plurality of III-nitride fins on the first III-nitride layer using the first hardmask layer as a mask, wherein each of the plurality of III-nitride fins are separated by one of a plurality of first recess regions and character-ized by a fin surface, wherein the plurality of III-nitride fins are characterized by the first conductivity type; epitaxially growing a III-nitride gate layer having a sec-ond conductivity type opposite to the first conductivity type in the plurality of first recess regions, wherein a surface of the III-nitride gate layer is substantially coplanar with the fin surface; forming a first dielectric layer on the first hardmask layer and the III-nitride gate layer, wherein the first dielectric layer comprises a contact region aligned with each of the plurality of III-nitride fins and a gate region aligned with the III-nitride gate layer; forming a photoresist layer on the gate region of the first dielectric layer; etching the contact region of the first dielectric layer using the photoresist layer as a mask to form a second recess region, wherein an upper surface of each of the plural-ity of the III-nitride fins and a portion of upper surface of the III-nitride gate layer surrounding each of the plurality of III-nitride fins are exposed from a bottom surface of the second recess region; removing the photoresist layer; epitaxially regrowing a III-nitride source contact portion in the second recess region; and removing the first dielectric layer.
The method of claim 7 wherein a width of the contact region is at least three times of that of a width of each of the plurality of III-nitride fins.
The method of claim 7, further comprising: forming a source metal mask layer having an opening aligned with the III-nitride source contact portion on each of the plurality of III-nitride fins; forming a first source metal layer coupled to the III-nitride source contact portion; forming a second source metal layer coupled to the first source metal layer; forming a third source metal layer coupled to the second source metal layer; and removing the source metal mask layer.
The method of claim 7 wherein epitaxially regrowing the III-nitride source contact portion comprises performing a self-limiting growth process on top of each of the plurality of III-nitride fins.
The method of claim 7 wherein the III-nitride source contact portion is characterized by an isosceles triangle shape having a base angle in a range between 58 degrees and 65 degrees in a cross-section view.
The method of claim 7 wherein the III-nitride gate layer is disposed in the plurality of first recess regions between adjacent III-nitride fins of the plurality of III-nitride fins. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical fin-based field effect transistor (FET)
Materials described outside the worked examples.
III-nitride substrate
III-nitride gate layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view of a vertical-fin-based field effect transistor (FET) device according to an embodi- ment of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.7–0.8 µm | — |
Temperature |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,728,415 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a vertical-fin-based field effect transistor (FET) device according to an embodi- ment of the present disclosure.
FIG. 2 is a simplified cross-sectional view of a vertical- fin-based FET device illustrating current flow from a lateral direction along a two-dimensional …
FIG. 3 is a simplified flowchart of a method of fabricating a vertical-fin-based FET device according to an embodiment of the present disclosure.
FIG. 4U are cross-sectional views show- ing intermediate stages of a method of fabricating a vertical- fin-based FET device that can be applied to the first and …
FIG. 5 is a simulation structure of a vertical-fin-based FET device having a 0.2 µm fin thickness.
FIG. 6 is a graph illustrating a threshold voltage (in V) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 7 is a graph illustrating an electric field E (in MV/cm) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 8 is a graph illustrating channel leakage (in A) of a vertical-fin-based FET device as a function of an etch offset 5 (in µm).
FIG. 9B is a graph illustrating a current density for a 0.1 µm overetch. 10
FIG. 10B is a graph illustrating an electric field at the gate corner for a 0.1 µm underetch.
FIG. 11 is a graph illustrating the on-resistance Ron as a 20 function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 12 is a graph illustrating a threshold voltage Vt (V) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer. 25
FIG. 13 is a graph illustrating a maximum electric field (MV/cm) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 14 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation 30 (µm) for the 0.2 µm graded epitaxial …
FIG. 15 is a graph illustrating the on-resistance Ron (mΩ) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 16 is a graph illustrating a threshold voltage Vt (V) 35 as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 17 is a graph illustrating an electric field (MV/cm) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer. 40
FIG. 18 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation (µm) for the 0.3 µm graded epitaxial …
FIG. 19B is a graph illustrating an effect of the polariza- tion charge predicted to result at the c-plane In0.15Ga0.85N/GaN interface according to some …
FIG. 20B is a graph illustrating an effect of an electric field predicted to result at the c-plane In0.15Ga0.85N/GaN 55 interface according to some embodiments …
FIG. 21C is a graph of current density through the channel 65 of the baseline FET compared with that of the non-polar FET. B₂
FIG. 22J are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 23G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 24G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 60 18, the high-voltage drain leakage current Idss was well controlled over the simulated etch range. In summary, the inventors have determined that using …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming an alignment contact, the method comprising: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a plurality of III-nitride fins on the first III-nitride layer, wherein each the plurality of III-nitride fins is separated by one of a plurality of first recess regions and characterized by a fin surface, wherein the plurality of III-nitride fins are characterized by the first conduc-tivity type; forming a III-nitride gate layer disposed between adjacent III-nitride fins of the plurality of III-nitride fins, wherein a surface of the III-nitride gate layer is substantially coplanar with the fin surface; epitaxially regrowing a III-nitride source contact portion on each of the plurality of III-nitride fins; and forming a source contact structure on the III-nitride source contact portions.
The method of claim 1 wherein the III-nitride substrate comprises an n-GaN substrate.
The method of claim 1 wherein the first III-nitride layer and the plurality of III-nitride fins comprise an n-GaN epitaxial layer.
The method of claim 1, further comprising, prior to forming the plurality of III-nitride fins, forming a hardmask on the fin surface of each of the plurality of III-nitride fins.
The method of claim 1 wherein sidewalls of each of the plurality of III-nitride fins are aligned with an m-plane and the fin surface is aligned with a c-plane.
The method of claim 1 wherein epitaxially regrowing the III-nitride source contact portion comprises performing a self-limiting growth process on top of each of the plurality of III-nitride fins and the epitaxially regrown III-nitride B₂ source contact portion is characterized by an isosceles triangle shape having a base angle in a range between 58 degrees and 65 degrees in a cross-section view.
A method for forming an alignment contact, the method comprising: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a first hardmask layer on the first III-nitride layer; forming a plurality of III-nitride fins on the first III-nitride layer using the first hardmask layer as a mask, wherein each of the plurality of III-nitride fins are separated by one of a plurality of first recess regions and character-ized by a fin surface, wherein the plurality of III-nitride fins are characterized by the first conductivity type; epitaxially growing a III-nitride gate layer having a sec-ond conductivity type opposite to the first conductivity type in the plurality of first recess regions, wherein a surface of the III-nitride gate layer is substantially coplanar with the fin surface; forming a first dielectric layer on the first hardmask layer and the III-nitride gate layer, wherein the first dielectric layer comprises a contact region aligned with each of the plurality of III-nitride fins and a gate region aligned with the III-nitride gate layer; forming a photoresist layer on the gate region of the first dielectric layer; etching the contact region of the first dielectric layer using the photoresist layer as a mask to form a second recess region, wherein an upper surface of each of the plural-ity of the III-nitride fins and a portion of upper surface of the III-nitride gate layer surrounding each of the plurality of III-nitride fins are exposed from a bottom surface of the second recess region; removing the photoresist layer; epitaxially regrowing a III-nitride source contact portion in the second recess region; and removing the first dielectric layer.
The method of claim 7 wherein a width of the contact region is at least three times of that of a width of each of the plurality of III-nitride fins.
The method of claim 7, further comprising: forming a source metal mask layer having an opening aligned with the III-nitride source contact portion on each of the plurality of III-nitride fins; forming a first source metal layer coupled to the III-nitride source contact portion; forming a second source metal layer coupled to the first source metal layer; forming a third source metal layer coupled to the second source metal layer; and removing the source metal mask layer.
The method of claim 7 wherein epitaxially regrowing the III-nitride source contact portion comprises performing a self-limiting growth process on top of each of the plurality of III-nitride fins.
The method of claim 7 wherein the III-nitride source contact portion is characterized by an isosceles triangle shape having a base angle in a range between 58 degrees and 65 degrees in a cross-section view.
The method of claim 7 wherein the III-nitride gate layer is disposed in the plurality of first recess regions between adjacent III-nitride fins of the plurality of III-nitride fins. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical fin-based field effect transistor (FET)
Materials described outside the worked examples.
III-nitride substrate
III-nitride gate layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view of a vertical-fin-based field effect transistor (FET) device according to an embodi- ment of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.7–0.8 µm | — |
Temperature |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
n-GaN substrate
GaN
III-nitride fins
FIG. 2 is a simplified cross-sectional view of a vertical- fin-based FET device illustrating current flow from a lateral direction along a two-dimensional …
FIG. 3 is a simplified flowchart of a method of fabricating a vertical-fin-based FET device according to an embodiment of the present disclosure.
FIG. 4U are cross-sectional views show- ing intermediate stages of a method of fabricating a vertical- fin-based FET device that can be applied to the first and …
FIG. 5 is a simulation structure of a vertical-fin-based FET device having a 0.2 µm fin thickness.
FIG. 5 is a simulation structure of a vertical-fin-based FET device having a 0.2 µm fin thickness.
FIG. 6 is a graph illustrating a threshold voltage (in V) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 6 is a graph illustrating a threshold voltage (in V) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 7 is a graph illustrating an electric field E (in MV/cm) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 7 is a graph illustrating an electric field E (in MV/cm) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 8 is a graph illustrating channel leakage (in A) of a vertical-fin-based FET device as a function of an etch offset 5 (in µm).
FIG. 8 is a graph illustrating channel leakage (in A) of a vertical-fin-based FET device as a function of an etch offset 5 (in µm).
FIG. 9B is a graph illustrating a current density for a 0.1 µm overetch. 10
FIG. 10B is a graph illustrating an electric field at the gate corner for a 0.1 µm underetch.
FIG. 11 is a graph illustrating the on-resistance Ron as a 20 function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 12 is a graph illustrating a threshold voltage Vt (V) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer. 25
FIG. 13 is a graph illustrating a maximum electric field (MV/cm) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 14 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation 30 (µm) for the 0.2 µm graded epitaxial …
FIG. 15 is a graph illustrating the on-resistance Ron (mΩ) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 16 is a graph illustrating a threshold voltage Vt (V) 35 as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 17 is a graph illustrating an electric field (MV/cm) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer. 40
FIG. 18 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation (µm) for the 0.3 µm graded epitaxial …
FIG. 19B is a graph illustrating an effect of the polariza- tion charge predicted to result at the c-plane In0.15Ga0.85N/GaN interface according to some …
FIG. 20B is a graph illustrating an effect of an electric field predicted to result at the c-plane In0.15Ga0.85N/GaN 55 interface according to some embodiments …
FIG. 21C is a graph of current density through the channel 65 of the baseline FET compared with that of the non-polar FET. B₂
FIG. 21C is a graph of current density through the channel 65 of the baseline FET compared with that of the non-polar FET. B₂
FIG. 22J are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 23G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 24G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
| 950–1100 °C |
| — |
Temperature | 950–1200 °C | — |
Temperature | 1000–1150 °C | — |
Temperature | 800–1150 °C | — |
Temperature | 850–1100 °C | — |
Temperature | 900–1050 °C | — |
Temperature | 930–970 °C | — |
n-GaN substrate
GaN
III-nitride fins
FIG. 2 is a simplified cross-sectional view of a vertical- fin-based FET device illustrating current flow from a lateral direction along a two-dimensional …
FIG. 3 is a simplified flowchart of a method of fabricating a vertical-fin-based FET device according to an embodiment of the present disclosure.
FIG. 4U are cross-sectional views show- ing intermediate stages of a method of fabricating a vertical- fin-based FET device that can be applied to the first and …
FIG. 5 is a simulation structure of a vertical-fin-based FET device having a 0.2 µm fin thickness.
FIG. 5 is a simulation structure of a vertical-fin-based FET device having a 0.2 µm fin thickness.
FIG. 6 is a graph illustrating a threshold voltage (in V) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 6 is a graph illustrating a threshold voltage (in V) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 7 is a graph illustrating an electric field E (in MV/cm) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 7 is a graph illustrating an electric field E (in MV/cm) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 8 is a graph illustrating channel leakage (in A) of a vertical-fin-based FET device as a function of an etch offset 5 (in µm).
FIG. 8 is a graph illustrating channel leakage (in A) of a vertical-fin-based FET device as a function of an etch offset 5 (in µm).
FIG. 9B is a graph illustrating a current density for a 0.1 µm overetch. 10
FIG. 10B is a graph illustrating an electric field at the gate corner for a 0.1 µm underetch.
FIG. 11 is a graph illustrating the on-resistance Ron as a 20 function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 12 is a graph illustrating a threshold voltage Vt (V) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer. 25
FIG. 13 is a graph illustrating a maximum electric field (MV/cm) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 14 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation 30 (µm) for the 0.2 µm graded epitaxial …
FIG. 15 is a graph illustrating the on-resistance Ron (mΩ) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 16 is a graph illustrating a threshold voltage Vt (V) 35 as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 17 is a graph illustrating an electric field (MV/cm) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer. 40
FIG. 18 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation (µm) for the 0.3 µm graded epitaxial …
FIG. 19B is a graph illustrating an effect of the polariza- tion charge predicted to result at the c-plane In0.15Ga0.85N/GaN interface according to some …
FIG. 20B is a graph illustrating an effect of an electric field predicted to result at the c-plane In0.15Ga0.85N/GaN 55 interface according to some embodiments …
FIG. 21C is a graph of current density through the channel 65 of the baseline FET compared with that of the non-polar FET. B₂
FIG. 21C is a graph of current density through the channel 65 of the baseline FET compared with that of the non-polar FET. B₂
FIG. 22J are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 23G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 24G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
| 950–1100 °C |
| — |
Temperature | 950–1200 °C | — |
Temperature | 1000–1150 °C | — |
Temperature | 800–1150 °C | — |
Temperature | 850–1100 °C | — |
Temperature | 900–1050 °C | — |
Temperature | 930–970 °C | — |
n-GaN substrate
GaN
III-nitride fins
FIG. 2 is a simplified cross-sectional view of a vertical- fin-based FET device illustrating current flow from a lateral direction along a two-dimensional …
FIG. 3 is a simplified flowchart of a method of fabricating a vertical-fin-based FET device according to an embodiment of the present disclosure.
FIG. 4U are cross-sectional views show- ing intermediate stages of a method of fabricating a vertical- fin-based FET device that can be applied to the first and …
FIG. 5 is a simulation structure of a vertical-fin-based FET device having a 0.2 µm fin thickness.
FIG. 5 is a simulation structure of a vertical-fin-based FET device having a 0.2 µm fin thickness.
FIG. 6 is a graph illustrating a threshold voltage (in V) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 6 is a graph illustrating a threshold voltage (in V) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 7 is a graph illustrating an electric field E (in MV/cm) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 7 is a graph illustrating an electric field E (in MV/cm) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 8 is a graph illustrating channel leakage (in A) of a vertical-fin-based FET device as a function of an etch offset 5 (in µm).
FIG. 8 is a graph illustrating channel leakage (in A) of a vertical-fin-based FET device as a function of an etch offset 5 (in µm).
FIG. 9B is a graph illustrating a current density for a 0.1 µm overetch. 10
FIG. 10B is a graph illustrating an electric field at the gate corner for a 0.1 µm underetch.
FIG. 11 is a graph illustrating the on-resistance Ron as a 20 function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 12 is a graph illustrating a threshold voltage Vt (V) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer. 25
FIG. 13 is a graph illustrating a maximum electric field (MV/cm) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 14 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation 30 (µm) for the 0.2 µm graded epitaxial …
FIG. 15 is a graph illustrating the on-resistance Ron (mΩ) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 16 is a graph illustrating a threshold voltage Vt (V) 35 as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 17 is a graph illustrating an electric field (MV/cm) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer. 40
FIG. 18 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation (µm) for the 0.3 µm graded epitaxial …
FIG. 19B is a graph illustrating an effect of the polariza- tion charge predicted to result at the c-plane In0.15Ga0.85N/GaN interface according to some …
FIG. 20B is a graph illustrating an effect of an electric field predicted to result at the c-plane In0.15Ga0.85N/GaN 55 interface according to some embodiments …
FIG. 21C is a graph of current density through the channel 65 of the baseline FET compared with that of the non-polar FET. B₂
FIG. 21C is a graph of current density through the channel 65 of the baseline FET compared with that of the non-polar FET. B₂
FIG. 22J are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 23G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 24G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
| 950–1100 °C |
| — |
Temperature | 950–1200 °C | — |
Temperature | 1000–1150 °C | — |
Temperature | 800–1150 °C | — |
Temperature | 850–1100 °C | — |
Temperature | 900–1050 °C | — |
Temperature | 930–970 °C | — |
n-GaN substrate
GaN
III-nitride fins
FIG. 2 is a simplified cross-sectional view of a vertical- fin-based FET device illustrating current flow from a lateral direction along a two-dimensional …
FIG. 3 is a simplified flowchart of a method of fabricating a vertical-fin-based FET device according to an embodiment of the present disclosure.
FIG. 4U are cross-sectional views show- ing intermediate stages of a method of fabricating a vertical- fin-based FET device that can be applied to the first and …
FIG. 5 is a simulation structure of a vertical-fin-based FET device having a 0.2 µm fin thickness.
FIG. 5 is a simulation structure of a vertical-fin-based FET device having a 0.2 µm fin thickness.
FIG. 6 is a graph illustrating a threshold voltage (in V) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 6 is a graph illustrating a threshold voltage (in V) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 7 is a graph illustrating an electric field E (in MV/cm) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 7 is a graph illustrating an electric field E (in MV/cm) of a vertical-fin-based FET device as a function of an etch offset (in µm).
FIG. 8 is a graph illustrating channel leakage (in A) of a vertical-fin-based FET device as a function of an etch offset 5 (in µm).
FIG. 8 is a graph illustrating channel leakage (in A) of a vertical-fin-based FET device as a function of an etch offset 5 (in µm).
FIG. 9B is a graph illustrating a current density for a 0.1 µm overetch. 10
FIG. 10B is a graph illustrating an electric field at the gate corner for a 0.1 µm underetch.
FIG. 11 is a graph illustrating the on-resistance Ron as a 20 function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 12 is a graph illustrating a threshold voltage Vt (V) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer. 25
FIG. 13 is a graph illustrating a maximum electric field (MV/cm) as a function of etch variation (µm) for the 0.2 µm graded epitaxial layer.
FIG. 14 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation 30 (µm) for the 0.2 µm graded epitaxial …
FIG. 15 is a graph illustrating the on-resistance Ron (mΩ) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 16 is a graph illustrating a threshold voltage Vt (V) 35 as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer.
FIG. 17 is a graph illustrating an electric field (MV/cm) as a function of etch variation (µm) for the 0.3 µm graded epitaxial layer. 40
FIG. 18 is a graph illustrating a high-voltage drain leakage current Idss (A) at 1200V as a function of etch variation (µm) for the 0.3 µm graded epitaxial …
FIG. 19B is a graph illustrating an effect of the polariza- tion charge predicted to result at the c-plane In0.15Ga0.85N/GaN interface according to some …
FIG. 20B is a graph illustrating an effect of an electric field predicted to result at the c-plane In0.15Ga0.85N/GaN 55 interface according to some embodiments …
FIG. 21C is a graph of current density through the channel 65 of the baseline FET compared with that of the non-polar FET. B₂
FIG. 21C is a graph of current density through the channel 65 of the baseline FET compared with that of the non-polar FET. B₂
FIG. 22J are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 23G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
FIG. 24G are cross-sectional views showing intermediate stages of a method of fabricating a vertical-fin-based FET device according to an embodiment of the …
| 950–1100 °C |
| — |
Temperature | 950–1200 °C | — |
Temperature | 1000–1150 °C | — |
Temperature | 800–1150 °C | — |
Temperature | 850–1100 °C | — |
Temperature | 900–1050 °C | — |
Temperature | 930–970 °C | — |
