Patent
Atlas literature
Patent
US 12,394,742 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is an isometric view of an example module that includes an example planar interconnect structure. 55
FIG. 2 is a schematic of an example GaN switching module.
FIG. 3 is a schematic of an example segmented GaN FET transistor.
FIGS. 4A and 4B illustrates a prior art wire bond inter- 60 connect.
FIG. 5 is an isometric cut-away view that illustrates an example planar interconnect structure in more detail.
FIG. 6B is a cross-sectional view of an example planar interconnect structure. 65
FIGS. 7A-7C are cross-sectional views illustrating fabri- cation of an example planar interconnect structure. B₂
FIG. 8 is a plot illustrating a comparison of inductance between a bond wire interconnect and an example planar interconnect structure.
FIG. 9 is an isometric view of another example module that includes an example planar interconnect structure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A circuit module comprising: a multilayer substrate having a first surface and an oppo-site second surface; a first conductive pad formed within a first one of the layers of the multilayer substrate; an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a semicon-ductor device formed therein, the semiconductor device having a set of bond pads formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; and a first printed ink planar interconnect line coupled to a subset of the set of bond pads and to the conductive pad.
The circuit module of claim 1, wherein the printed ink includes copper particles.
The circuit module of claim 1, wherein the printed ink includes silver or gold particles.
The circuit module of claim 1, wherein a heat dispers-ing layer of the multilayer substrate forms the second surface of the multilayer substrate.
The circuit module of claim 1, wherein the semicon-ductor device is a GaN FET.
The circuit module of claim 1, further comprising: a second IC die mounted to the first surface of the multilayer substrate; at least one passive component coupled to the first surface of the multilayer substrate; and encapsulation material covering the first surface of the multilayer substrate, the IC die, the second IC die, and the passive component.
A circuit module comprising: a multilayer substrate having a first surface and an oppo-site second surface; a first conductive pad formed within a first one of the layers of the multilayer substrate; a second conductive pad formed within a second one of the layers of the multilayer substrate; an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a semicon-ductor device formed therein, the semiconductor device having a set of bond pads formed on the first surface of the IC die, wherein the set of bond pads is a first set of bond pads and the semiconductor device has a second set of bond pads formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; a first printed ink planar interconnect line coupled to the set of bond pads and to the conductive pad; and a second printed ink planar interconnect line coupled to the second set of bond pads and to the second conduc-tive pad.
A circuit module comprising: 25 a multilayer substrate having a first surface and an oppo-site second surface; a first conductive pad formed within a first one of the layers of the multilayer substrate; a second conductive pad formed within a second one of the layers of the multilayer substrate; an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a GaN FET semiconductor device formed therein, the GaN FET having a set of source bond pads, a set of drain bond pads, and a gate bond pad all formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; a first printed ink planar interconnect line coupled to the set of source bond pads and to the first conductive pad; and B₂ a second printed ink planar interconnect line coupled to the set of drain bond pads and to the second conductive pad.
The circuit module of claim 9 further comprising: a second IC die mounted to the first surface of the multilayer substrate, the second IC having an output bond pad; and a third printed ink planar interconnect line coupled between the output bond pad on the second IC and the gate bond pad on the GaN FET.
The circuit module of claim 9, wherein the printed ink includes copper particles.
The circuit module of claim 9, wherein the printed ink includes silver or gold particles.
The circuit module of claim 9, wherein a heat dis-persing layer of the multilayer substrate forms the second surface of the multilayer substrate.
A method for fabricating a module, the method comprising: fabricating a multilayer substrate having an exposed sur-face; patterning a first conductive layer of the multilayer substrate to form a conductive pad; patterning a second conductive layer of the multilayer substrate to form a second conductive pad; bonding an integrated circuit (IC) die to the exposed surface of the multilayer substrate such that a set of bond pads on the IC die face away from the exposed surface of the multilayer substrate; printing a patterned layer of dielectric over the IC die and the conductive pad such that the set of bond pads and the conductive pad are exposed; printing a patterned layer of conductive ink to form a first printed ink planar interconnect line to couple a portion of the set of bond pads to the conductive pad; and wherein printing the patterned layer of conductive ink also forms a second printed ink planar interconnect line to couple a second portion of the set of bond pads to the second conductive pad. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
circuit module with printed ink planar interconnect
Materials described outside the worked examples.
printed conductive ink
copper particle printed ink
Cu
silver or gold particle printed ink
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 14
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,394,742 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is an isometric view of an example module that includes an example planar interconnect structure. 55
FIG. 2 is a schematic of an example GaN switching module.
FIG. 3 is a schematic of an example segmented GaN FET transistor.
FIGS. 4A and 4B illustrates a prior art wire bond inter- 60 connect.
FIG. 5 is an isometric cut-away view that illustrates an example planar interconnect structure in more detail.
FIG. 6B is a cross-sectional view of an example planar interconnect structure. 65
FIGS. 7A-7C are cross-sectional views illustrating fabri- cation of an example planar interconnect structure. B₂
FIG. 8 is a plot illustrating a comparison of inductance between a bond wire interconnect and an example planar interconnect structure.
FIG. 9 is an isometric view of another example module that includes an example planar interconnect structure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A circuit module comprising: a multilayer substrate having a first surface and an oppo-site second surface; a first conductive pad formed within a first one of the layers of the multilayer substrate; an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a semicon-ductor device formed therein, the semiconductor device having a set of bond pads formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; and a first printed ink planar interconnect line coupled to a subset of the set of bond pads and to the conductive pad.
The circuit module of claim 1, wherein the printed ink includes copper particles.
The circuit module of claim 1, wherein the printed ink includes silver or gold particles.
The circuit module of claim 1, wherein a heat dispers-ing layer of the multilayer substrate forms the second surface of the multilayer substrate.
The circuit module of claim 1, wherein the semicon-ductor device is a GaN FET.
The circuit module of claim 1, further comprising: a second IC die mounted to the first surface of the multilayer substrate; at least one passive component coupled to the first surface of the multilayer substrate; and encapsulation material covering the first surface of the multilayer substrate, the IC die, the second IC die, and the passive component.
A circuit module comprising: a multilayer substrate having a first surface and an oppo-site second surface; a first conductive pad formed within a first one of the layers of the multilayer substrate; a second conductive pad formed within a second one of the layers of the multilayer substrate; an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a semicon-ductor device formed therein, the semiconductor device having a set of bond pads formed on the first surface of the IC die, wherein the set of bond pads is a first set of bond pads and the semiconductor device has a second set of bond pads formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; a first printed ink planar interconnect line coupled to the set of bond pads and to the conductive pad; and a second printed ink planar interconnect line coupled to the second set of bond pads and to the second conduc-tive pad.
A circuit module comprising: 25 a multilayer substrate having a first surface and an oppo-site second surface; a first conductive pad formed within a first one of the layers of the multilayer substrate; a second conductive pad formed within a second one of the layers of the multilayer substrate; an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a GaN FET semiconductor device formed therein, the GaN FET having a set of source bond pads, a set of drain bond pads, and a gate bond pad all formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; a first printed ink planar interconnect line coupled to the set of source bond pads and to the first conductive pad; and B₂ a second printed ink planar interconnect line coupled to the set of drain bond pads and to the second conductive pad.
The circuit module of claim 9 further comprising: a second IC die mounted to the first surface of the multilayer substrate, the second IC having an output bond pad; and a third printed ink planar interconnect line coupled between the output bond pad on the second IC and the gate bond pad on the GaN FET.
The circuit module of claim 9, wherein the printed ink includes copper particles.
The circuit module of claim 9, wherein the printed ink includes silver or gold particles.
The circuit module of claim 9, wherein a heat dis-persing layer of the multilayer substrate forms the second surface of the multilayer substrate.
A method for fabricating a module, the method comprising: fabricating a multilayer substrate having an exposed sur-face; patterning a first conductive layer of the multilayer substrate to form a conductive pad; patterning a second conductive layer of the multilayer substrate to form a second conductive pad; bonding an integrated circuit (IC) die to the exposed surface of the multilayer substrate such that a set of bond pads on the IC die face away from the exposed surface of the multilayer substrate; printing a patterned layer of dielectric over the IC die and the conductive pad such that the set of bond pads and the conductive pad are exposed; printing a patterned layer of conductive ink to form a first printed ink planar interconnect line to couple a portion of the set of bond pads to the conductive pad; and wherein printing the patterned layer of conductive ink also forms a second printed ink planar interconnect line to couple a second portion of the set of bond pads to the second conductive pad. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
circuit module with printed ink planar interconnect
Materials described outside the worked examples.
printed conductive ink
copper particle printed ink
Cu
silver or gold particle printed ink
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 14
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,394,742 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is an isometric view of an example module that includes an example planar interconnect structure. 55
FIG. 2 is a schematic of an example GaN switching module.
FIG. 3 is a schematic of an example segmented GaN FET transistor.
FIGS. 4A and 4B illustrates a prior art wire bond inter- 60 connect.
FIG. 5 is an isometric cut-away view that illustrates an example planar interconnect structure in more detail.
FIG. 6B is a cross-sectional view of an example planar interconnect structure. 65
FIGS. 7A-7C are cross-sectional views illustrating fabri- cation of an example planar interconnect structure. B₂
FIG. 8 is a plot illustrating a comparison of inductance between a bond wire interconnect and an example planar interconnect structure.
FIG. 9 is an isometric view of another example module that includes an example planar interconnect structure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A circuit module comprising: a multilayer substrate having a first surface and an oppo-site second surface; a first conductive pad formed within a first one of the layers of the multilayer substrate; an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a semicon-ductor device formed therein, the semiconductor device having a set of bond pads formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; and a first printed ink planar interconnect line coupled to a subset of the set of bond pads and to the conductive pad.
The circuit module of claim 1, wherein the printed ink includes copper particles.
The circuit module of claim 1, wherein the printed ink includes silver or gold particles.
The circuit module of claim 1, wherein a heat dispers-ing layer of the multilayer substrate forms the second surface of the multilayer substrate.
The circuit module of claim 1, wherein the semicon-ductor device is a GaN FET.
The circuit module of claim 1, further comprising: a second IC die mounted to the first surface of the multilayer substrate; at least one passive component coupled to the first surface of the multilayer substrate; and encapsulation material covering the first surface of the multilayer substrate, the IC die, the second IC die, and the passive component.
A circuit module comprising: a multilayer substrate having a first surface and an oppo-site second surface; a first conductive pad formed within a first one of the layers of the multilayer substrate; a second conductive pad formed within a second one of the layers of the multilayer substrate; an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a semicon-ductor device formed therein, the semiconductor device having a set of bond pads formed on the first surface of the IC die, wherein the set of bond pads is a first set of bond pads and the semiconductor device has a second set of bond pads formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; a first printed ink planar interconnect line coupled to the set of bond pads and to the conductive pad; and a second printed ink planar interconnect line coupled to the second set of bond pads and to the second conduc-tive pad.
A circuit module comprising: 25 a multilayer substrate having a first surface and an oppo-site second surface; a first conductive pad formed within a first one of the layers of the multilayer substrate; a second conductive pad formed within a second one of the layers of the multilayer substrate; an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a GaN FET semiconductor device formed therein, the GaN FET having a set of source bond pads, a set of drain bond pads, and a gate bond pad all formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; a first printed ink planar interconnect line coupled to the set of source bond pads and to the first conductive pad; and B₂ a second printed ink planar interconnect line coupled to the set of drain bond pads and to the second conductive pad.
The circuit module of claim 9 further comprising: a second IC die mounted to the first surface of the multilayer substrate, the second IC having an output bond pad; and a third printed ink planar interconnect line coupled between the output bond pad on the second IC and the gate bond pad on the GaN FET.
The circuit module of claim 9, wherein the printed ink includes copper particles.
The circuit module of claim 9, wherein the printed ink includes silver or gold particles.
The circuit module of claim 9, wherein a heat dis-persing layer of the multilayer substrate forms the second surface of the multilayer substrate.
A method for fabricating a module, the method comprising: fabricating a multilayer substrate having an exposed sur-face; patterning a first conductive layer of the multilayer substrate to form a conductive pad; patterning a second conductive layer of the multilayer substrate to form a second conductive pad; bonding an integrated circuit (IC) die to the exposed surface of the multilayer substrate such that a set of bond pads on the IC die face away from the exposed surface of the multilayer substrate; printing a patterned layer of dielectric over the IC die and the conductive pad such that the set of bond pads and the conductive pad are exposed; printing a patterned layer of conductive ink to form a first printed ink planar interconnect line to couple a portion of the set of bond pads to the conductive pad; and wherein printing the patterned layer of conductive ink also forms a second printed ink planar interconnect line to couple a second portion of the set of bond pads to the second conductive pad. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
circuit module with printed ink planar interconnect
Materials described outside the worked examples.
printed conductive ink
copper particle printed ink
Cu
silver or gold particle printed ink
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 14
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,394,742 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is an isometric view of an example module that includes an example planar interconnect structure. 55
FIG. 2 is a schematic of an example GaN switching module.
FIG. 3 is a schematic of an example segmented GaN FET transistor.
FIGS. 4A and 4B illustrates a prior art wire bond inter- 60 connect.
FIG. 5 is an isometric cut-away view that illustrates an example planar interconnect structure in more detail.
FIG. 6B is a cross-sectional view of an example planar interconnect structure. 65
FIGS. 7A-7C are cross-sectional views illustrating fabri- cation of an example planar interconnect structure. B₂
FIG. 8 is a plot illustrating a comparison of inductance between a bond wire interconnect and an example planar interconnect structure.
FIG. 9 is an isometric view of another example module that includes an example planar interconnect structure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A circuit module comprising: a multilayer substrate having a first surface and an oppo-site second surface; a first conductive pad formed within a first one of the layers of the multilayer substrate; an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a semicon-ductor device formed therein, the semiconductor device having a set of bond pads formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; and a first printed ink planar interconnect line coupled to a subset of the set of bond pads and to the conductive pad.
The circuit module of claim 1, wherein the printed ink includes copper particles.
The circuit module of claim 1, wherein the printed ink includes silver or gold particles.
The circuit module of claim 1, wherein a heat dispers-ing layer of the multilayer substrate forms the second surface of the multilayer substrate.
The circuit module of claim 1, wherein the semicon-ductor device is a GaN FET.
The circuit module of claim 1, further comprising: a second IC die mounted to the first surface of the multilayer substrate; at least one passive component coupled to the first surface of the multilayer substrate; and encapsulation material covering the first surface of the multilayer substrate, the IC die, the second IC die, and the passive component.
A circuit module comprising: a multilayer substrate having a first surface and an oppo-site second surface; a first conductive pad formed within a first one of the layers of the multilayer substrate; a second conductive pad formed within a second one of the layers of the multilayer substrate; an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a semicon-ductor device formed therein, the semiconductor device having a set of bond pads formed on the first surface of the IC die, wherein the set of bond pads is a first set of bond pads and the semiconductor device has a second set of bond pads formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; a first printed ink planar interconnect line coupled to the set of bond pads and to the conductive pad; and a second printed ink planar interconnect line coupled to the second set of bond pads and to the second conduc-tive pad.
A circuit module comprising: 25 a multilayer substrate having a first surface and an oppo-site second surface; a first conductive pad formed within a first one of the layers of the multilayer substrate; a second conductive pad formed within a second one of the layers of the multilayer substrate; an integrated circuit (IC) die having a first surface and an opposite second surface, the IC die having a GaN FET semiconductor device formed therein, the GaN FET having a set of source bond pads, a set of drain bond pads, and a gate bond pad all formed on the first surface of the IC die, the second surface of the IC die being bonded to the first surface of the multilayer substrate; a first printed ink planar interconnect line coupled to the set of source bond pads and to the first conductive pad; and B₂ a second printed ink planar interconnect line coupled to the set of drain bond pads and to the second conductive pad.
The circuit module of claim 9 further comprising: a second IC die mounted to the first surface of the multilayer substrate, the second IC having an output bond pad; and a third printed ink planar interconnect line coupled between the output bond pad on the second IC and the gate bond pad on the GaN FET.
The circuit module of claim 9, wherein the printed ink includes copper particles.
The circuit module of claim 9, wherein the printed ink includes silver or gold particles.
The circuit module of claim 9, wherein a heat dis-persing layer of the multilayer substrate forms the second surface of the multilayer substrate.
A method for fabricating a module, the method comprising: fabricating a multilayer substrate having an exposed sur-face; patterning a first conductive layer of the multilayer substrate to form a conductive pad; patterning a second conductive layer of the multilayer substrate to form a second conductive pad; bonding an integrated circuit (IC) die to the exposed surface of the multilayer substrate such that a set of bond pads on the IC die face away from the exposed surface of the multilayer substrate; printing a patterned layer of dielectric over the IC die and the conductive pad such that the set of bond pads and the conductive pad are exposed; printing a patterned layer of conductive ink to form a first printed ink planar interconnect line to couple a portion of the set of bond pads to the conductive pad; and wherein printing the patterned layer of conductive ink also forms a second printed ink planar interconnect line to couple a second portion of the set of bond pads to the second conductive pad. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
circuit module with printed ink planar interconnect
Materials described outside the worked examples.
printed conductive ink
copper particle printed ink
Cu
silver or gold particle printed ink
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 14
Related documents with shared materials, methods, properties, or citations.
GaN FET circuit module with printed ink planar interconnect
gallium nitride (GaN)
GaN
ceramic
mold encapsulation material
Cited non-patent literature · 2
GaN FET circuit module with printed ink planar interconnect
gallium nitride (GaN)
GaN
ceramic
mold encapsulation material
Cited non-patent literature · 2
GaN FET circuit module with printed ink planar interconnect
gallium nitride (GaN)
GaN
ceramic
mold encapsulation material
Cited non-patent literature · 2
GaN FET circuit module with printed ink planar interconnect
gallium nitride (GaN)
GaN
ceramic
mold encapsulation material
Cited non-patent literature · 2
