Patent
US 12,456,707 B2STACKED CLIP DESIGN FOR GaN HALF BRIDGE IPM
Kwang-Soo Kim, Makoto Shibuya, Woochan Kim, Vivek Arora
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)·Oct. 28, 2025·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 12,456,707 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1.
FIG. 2 is a flow diagram of a method of making an electronic device.
FIGS. 3 and 3A are top plan and partial sectional side elevation views of the electronic device undergoing a sub- strate attach process.
FIG. 4 is a partial sectional side elevation view of the electronic device undergoing a die and passive component attach process.
FIG. 5 is a partial sectional side elevation view of the electronic device undergoing a first clip attach process.
FIG. 6 is a partial sectional side elevation view of the electronic device undergoing a second clip attach process.
FIG. 7 is a partial sectional side elevation view of the electronic device undergoing a third clip attach process.
FIG. 8 is a partial sectional side elevation view of the electronic device undergoing a fourth clip attach process.
FIGS. 9 and 9A are top plan and partial sectional side elevation views of the electronic device undergoing a ther- mal reflow process.
FIGS. 10 and 10A are top plan and partial sectional side elevation views of the electronic device undergoing a wire bonding electrical connection process.
FIG. 11 is a top plan view of the electronic device undergoing a molding process.
FIGS. 12 and 12A are top plan and partial sectional side elevation views of the electronic device undergoing a lead forming process.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device, comprising: a substrate having first and second conductive traces; a semiconductor die having a transistor with; a first terminal and a second terminal on a same side of the semiconductor die; a first metal clip having first and second end portions and a middle portion that joins the first and second end portions of the first metal clip, the first end portion of the first metal clip coupled to the first terminal of the transistor, and the second end portion of the first metal clip coupled to the first conductive trace of the substrate; and a second metal clip having first and second end portions and a middle portion that joins the first and second end portions of the second metal clip, the first end portion of the second metal clip coupled to the second terminal of the transistor, the second end portion of the second metal clip coupled to the second conductive trace of the substrate, and the middle portion of the second metal clip spaced apart from and at least partially overlying a portion of the first metal clip.
The electronic device of claim 1, further comprising: 5 a second semiconductor die having a second transistor with a first terminal and a second terminal; a third metal clip having first and second end portions and a middle portion that joins the first and second end portions of the third metal clip, the first end portion of the third metal clip coupled to the first terminal of the second transistor, and the second end portion of the third metal clip coupled to a third conductive trace of the substrate; and a fourth metal clip having first and second end portions and a middle portion that joins the first and second end portions of the fourth metal clip, the first end portion of the fourth metal clip coupled to the second terminal of the second transistor, the second end portion of the fourth metal clip coupled to the first conductive trace of the substrate, and the middle portion of the fourth metal clip spaced apart from and at least partially overlying a portion of the third metal clip.
The electronic device of claim 1, wherein a first transistor current of the transistor flows through the first and second metal clips in opposite respective first and second directions.
The electronic device of claim 1, wherein the transistor is a gallium nitride transistor.
The electronic device of claim 1, further comprising: a circuit board; and bond wires connecting conductive features of the circuit board to respective conductive features of the semicon-ductor die.
A half-bridge circuit, comprising: a first transistor with a first source and a first drain; a second transistor with a second source and a second drain; a first metal clip coupled between the first source and a switching node; a second metal clip at least partially overlying a portion of the first metal clip and coupled between the first drain and a supply node; a third metal clip coupled between the second source and a reference node; and a fourth metal clip at least partially overlying a portion of the third metal clip and coupled between the second drain and the switching node.
The half-bridge circuit of claim 12, wherein: the first metal clip has first and second end portions and a middle portion that joins the first and second end portions of the first metal clip, the first end portion of the first metal clip coupled to the first source, and the second end portion of the first metal clip coupled to the switching node; the second metal clip has first and second end portions and a middle portion that joins the first and second end portions of the second metal clip, the first end portion of the second metal clip coupled to the first drain, the second end portion of the second metal clip coupled to the supply node, and the middle portion of the second metal clip spaced apart from and at least partially overlying a portion of the first metal clip; the third metal clip has first and second end portions and a middle portion that joins the first and second end portions of the third metal clip, the first end portion of the third metal clip coupled to the second source, and the second end portion of the third metal clip coupled to the reference node; and the fourth metal clip has first and second end portions and a middle portion that joins the first and second end portions of the fourth metal clip, the first end portion of the fourth metal clip coupled to the second drain, the second end portion of the fourth metal clip coupled to the switching node, and the middle portion of the fourth metal clip spaced apart from and at least partially overlying a portion of the third metal clip.
The half-bridge circuit of claim 12, comprising: a substrate having first and second and third conductive traces that form the respective switching, supply, and reference nodes; a first semiconductor die mounted to the substrate and including the first transistor; and a second semiconductor die mounted to the substrate and including the second transistor.
A method of fabricating an electronic device, the method comprising: attaching a first end portion of a first metal clip to a first terminal of a transistor of a semiconductor die; attaching a second end portion of the first metal clip to a first conductive trace of a substrate; attaching a first end portion of; a second metal clip to a second terminal of the transistor, the first and second terminals on a same side of the semiconductor die; and attaching a second end portion of the second metal clip to a second conductive trace of the substrate with a middle portion of the second metal clip spaced apart from and at least partially overlying a portion of the first metal clip.
The method of claim 16, further comprising: attaching a first end portion of a third metal clip to a first terminal of a second transistor of a second semicon-ductor die; attaching a second end portion of the third metal clip to a third conductive trace of the substrate; attaching a first end portion of a fourth metal clip to a 15 second terminal of the second transistor; and attaching a second end portion of the fourth metal clip to the first conductive trace of the substrate with a middle B₂ portion of the fourth metal clip spaced apart from and at least partially overlying a portion of the third metal clip.
The method of claim 16, wherein attaching the end portions of the metal clips includes: providing solder to the respective transistor terminals and conductive traces; positioning the end portions of the metal clips on the solder; and reflowing the solder. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
electronic device with stacked metal clips and GaN transistor
half-bridge circuit with stacked metal clips
Materials described outside the worked examples.
first metal clip
second metal clip
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Cited non-patent literature · 2
Related documents with shared materials, methods, properties, or citations.
INTERCONNECT STRUCTURE FOR HIGH POWER GaN MODULE INCLUDING A PRINTED PLANAR INTERCONNECT LINE AND METHOD FOR MAKING THE SAME
GAN HEMT DEVICE FOR IRRADIATION DAMAGE DETECTION AND DETECTION AND MANUFACTURING METHOD THEREFOR
Patent
Atlas literature
Patent
US 12,456,707 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1.
FIG. 2 is a flow diagram of a method of making an electronic device.
FIGS. 3 and 3A are top plan and partial sectional side elevation views of the electronic device undergoing a sub- strate attach process.
FIG. 4 is a partial sectional side elevation view of the electronic device undergoing a die and passive component attach process.
FIG. 5 is a partial sectional side elevation view of the electronic device undergoing a first clip attach process.
FIG. 6 is a partial sectional side elevation view of the electronic device undergoing a second clip attach process.
FIG. 7 is a partial sectional side elevation view of the electronic device undergoing a third clip attach process.
FIG. 8 is a partial sectional side elevation view of the electronic device undergoing a fourth clip attach process.
FIGS. 9 and 9A are top plan and partial sectional side elevation views of the electronic device undergoing a ther- mal reflow process.
FIGS. 10 and 10A are top plan and partial sectional side elevation views of the electronic device undergoing a wire bonding electrical connection process.
FIG. 11 is a top plan view of the electronic device undergoing a molding process.
FIGS. 12 and 12A are top plan and partial sectional side elevation views of the electronic device undergoing a lead forming process.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device, comprising: a substrate having first and second conductive traces; a semiconductor die having a transistor with; a first terminal and a second terminal on a same side of the semiconductor die; a first metal clip having first and second end portions and a middle portion that joins the first and second end portions of the first metal clip, the first end portion of the first metal clip coupled to the first terminal of the transistor, and the second end portion of the first metal clip coupled to the first conductive trace of the substrate; and a second metal clip having first and second end portions and a middle portion that joins the first and second end portions of the second metal clip, the first end portion of the second metal clip coupled to the second terminal of the transistor, the second end portion of the second metal clip coupled to the second conductive trace of the substrate, and the middle portion of the second metal clip spaced apart from and at least partially overlying a portion of the first metal clip.
The electronic device of claim 1, further comprising: 5 a second semiconductor die having a second transistor with a first terminal and a second terminal; a third metal clip having first and second end portions and a middle portion that joins the first and second end portions of the third metal clip, the first end portion of the third metal clip coupled to the first terminal of the second transistor, and the second end portion of the third metal clip coupled to a third conductive trace of the substrate; and a fourth metal clip having first and second end portions and a middle portion that joins the first and second end portions of the fourth metal clip, the first end portion of the fourth metal clip coupled to the second terminal of the second transistor, the second end portion of the fourth metal clip coupled to the first conductive trace of the substrate, and the middle portion of the fourth metal clip spaced apart from and at least partially overlying a portion of the third metal clip.
The electronic device of claim 1, wherein a first transistor current of the transistor flows through the first and second metal clips in opposite respective first and second directions.
The electronic device of claim 1, wherein the transistor is a gallium nitride transistor.
The electronic device of claim 1, further comprising: a circuit board; and bond wires connecting conductive features of the circuit board to respective conductive features of the semicon-ductor die.
A half-bridge circuit, comprising: a first transistor with a first source and a first drain; a second transistor with a second source and a second drain; a first metal clip coupled between the first source and a switching node; a second metal clip at least partially overlying a portion of the first metal clip and coupled between the first drain and a supply node; a third metal clip coupled between the second source and a reference node; and a fourth metal clip at least partially overlying a portion of the third metal clip and coupled between the second drain and the switching node.
The half-bridge circuit of claim 12, wherein: the first metal clip has first and second end portions and a middle portion that joins the first and second end portions of the first metal clip, the first end portion of the first metal clip coupled to the first source, and the second end portion of the first metal clip coupled to the switching node; the second metal clip has first and second end portions and a middle portion that joins the first and second end portions of the second metal clip, the first end portion of the second metal clip coupled to the first drain, the second end portion of the second metal clip coupled to the supply node, and the middle portion of the second metal clip spaced apart from and at least partially overlying a portion of the first metal clip; the third metal clip has first and second end portions and a middle portion that joins the first and second end portions of the third metal clip, the first end portion of the third metal clip coupled to the second source, and the second end portion of the third metal clip coupled to the reference node; and the fourth metal clip has first and second end portions and a middle portion that joins the first and second end portions of the fourth metal clip, the first end portion of the fourth metal clip coupled to the second drain, the second end portion of the fourth metal clip coupled to the switching node, and the middle portion of the fourth metal clip spaced apart from and at least partially overlying a portion of the third metal clip.
The half-bridge circuit of claim 12, comprising: a substrate having first and second and third conductive traces that form the respective switching, supply, and reference nodes; a first semiconductor die mounted to the substrate and including the first transistor; and a second semiconductor die mounted to the substrate and including the second transistor.
A method of fabricating an electronic device, the method comprising: attaching a first end portion of a first metal clip to a first terminal of a transistor of a semiconductor die; attaching a second end portion of the first metal clip to a first conductive trace of a substrate; attaching a first end portion of; a second metal clip to a second terminal of the transistor, the first and second terminals on a same side of the semiconductor die; and attaching a second end portion of the second metal clip to a second conductive trace of the substrate with a middle portion of the second metal clip spaced apart from and at least partially overlying a portion of the first metal clip.
The method of claim 16, further comprising: attaching a first end portion of a third metal clip to a first terminal of a second transistor of a second semicon-ductor die; attaching a second end portion of the third metal clip to a third conductive trace of the substrate; attaching a first end portion of a fourth metal clip to a 15 second terminal of the second transistor; and attaching a second end portion of the fourth metal clip to the first conductive trace of the substrate with a middle B₂ portion of the fourth metal clip spaced apart from and at least partially overlying a portion of the third metal clip.
The method of claim 16, wherein attaching the end portions of the metal clips includes: providing solder to the respective transistor terminals and conductive traces; positioning the end portions of the metal clips on the solder; and reflowing the solder. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
electronic device with stacked metal clips and GaN transistor
half-bridge circuit with stacked metal clips
Materials described outside the worked examples.
first metal clip
second metal clip
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Cited non-patent literature · 2
Related documents with shared materials, methods, properties, or citations.
INTERCONNECT STRUCTURE FOR HIGH POWER GaN MODULE INCLUDING A PRINTED PLANAR INTERCONNECT LINE AND METHOD FOR MAKING THE SAME
GAN HEMT DEVICE FOR IRRADIATION DAMAGE DETECTION AND DETECTION AND MANUFACTURING METHOD THEREFOR
Patent
Atlas literature
Patent
US 12,456,707 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1.
FIG. 2 is a flow diagram of a method of making an electronic device.
FIGS. 3 and 3A are top plan and partial sectional side elevation views of the electronic device undergoing a sub- strate attach process.
FIG. 4 is a partial sectional side elevation view of the electronic device undergoing a die and passive component attach process.
FIG. 5 is a partial sectional side elevation view of the electronic device undergoing a first clip attach process.
FIG. 6 is a partial sectional side elevation view of the electronic device undergoing a second clip attach process.
FIG. 7 is a partial sectional side elevation view of the electronic device undergoing a third clip attach process.
FIG. 8 is a partial sectional side elevation view of the electronic device undergoing a fourth clip attach process.
FIGS. 9 and 9A are top plan and partial sectional side elevation views of the electronic device undergoing a ther- mal reflow process.
FIGS. 10 and 10A are top plan and partial sectional side elevation views of the electronic device undergoing a wire bonding electrical connection process.
FIG. 11 is a top plan view of the electronic device undergoing a molding process.
FIGS. 12 and 12A are top plan and partial sectional side elevation views of the electronic device undergoing a lead forming process.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device, comprising: a substrate having first and second conductive traces; a semiconductor die having a transistor with; a first terminal and a second terminal on a same side of the semiconductor die; a first metal clip having first and second end portions and a middle portion that joins the first and second end portions of the first metal clip, the first end portion of the first metal clip coupled to the first terminal of the transistor, and the second end portion of the first metal clip coupled to the first conductive trace of the substrate; and a second metal clip having first and second end portions and a middle portion that joins the first and second end portions of the second metal clip, the first end portion of the second metal clip coupled to the second terminal of the transistor, the second end portion of the second metal clip coupled to the second conductive trace of the substrate, and the middle portion of the second metal clip spaced apart from and at least partially overlying a portion of the first metal clip.
The electronic device of claim 1, further comprising: 5 a second semiconductor die having a second transistor with a first terminal and a second terminal; a third metal clip having first and second end portions and a middle portion that joins the first and second end portions of the third metal clip, the first end portion of the third metal clip coupled to the first terminal of the second transistor, and the second end portion of the third metal clip coupled to a third conductive trace of the substrate; and a fourth metal clip having first and second end portions and a middle portion that joins the first and second end portions of the fourth metal clip, the first end portion of the fourth metal clip coupled to the second terminal of the second transistor, the second end portion of the fourth metal clip coupled to the first conductive trace of the substrate, and the middle portion of the fourth metal clip spaced apart from and at least partially overlying a portion of the third metal clip.
The electronic device of claim 1, wherein a first transistor current of the transistor flows through the first and second metal clips in opposite respective first and second directions.
The electronic device of claim 1, wherein the transistor is a gallium nitride transistor.
The electronic device of claim 1, further comprising: a circuit board; and bond wires connecting conductive features of the circuit board to respective conductive features of the semicon-ductor die.
A half-bridge circuit, comprising: a first transistor with a first source and a first drain; a second transistor with a second source and a second drain; a first metal clip coupled between the first source and a switching node; a second metal clip at least partially overlying a portion of the first metal clip and coupled between the first drain and a supply node; a third metal clip coupled between the second source and a reference node; and a fourth metal clip at least partially overlying a portion of the third metal clip and coupled between the second drain and the switching node.
The half-bridge circuit of claim 12, wherein: the first metal clip has first and second end portions and a middle portion that joins the first and second end portions of the first metal clip, the first end portion of the first metal clip coupled to the first source, and the second end portion of the first metal clip coupled to the switching node; the second metal clip has first and second end portions and a middle portion that joins the first and second end portions of the second metal clip, the first end portion of the second metal clip coupled to the first drain, the second end portion of the second metal clip coupled to the supply node, and the middle portion of the second metal clip spaced apart from and at least partially overlying a portion of the first metal clip; the third metal clip has first and second end portions and a middle portion that joins the first and second end portions of the third metal clip, the first end portion of the third metal clip coupled to the second source, and the second end portion of the third metal clip coupled to the reference node; and the fourth metal clip has first and second end portions and a middle portion that joins the first and second end portions of the fourth metal clip, the first end portion of the fourth metal clip coupled to the second drain, the second end portion of the fourth metal clip coupled to the switching node, and the middle portion of the fourth metal clip spaced apart from and at least partially overlying a portion of the third metal clip.
The half-bridge circuit of claim 12, comprising: a substrate having first and second and third conductive traces that form the respective switching, supply, and reference nodes; a first semiconductor die mounted to the substrate and including the first transistor; and a second semiconductor die mounted to the substrate and including the second transistor.
A method of fabricating an electronic device, the method comprising: attaching a first end portion of a first metal clip to a first terminal of a transistor of a semiconductor die; attaching a second end portion of the first metal clip to a first conductive trace of a substrate; attaching a first end portion of; a second metal clip to a second terminal of the transistor, the first and second terminals on a same side of the semiconductor die; and attaching a second end portion of the second metal clip to a second conductive trace of the substrate with a middle portion of the second metal clip spaced apart from and at least partially overlying a portion of the first metal clip.
The method of claim 16, further comprising: attaching a first end portion of a third metal clip to a first terminal of a second transistor of a second semicon-ductor die; attaching a second end portion of the third metal clip to a third conductive trace of the substrate; attaching a first end portion of a fourth metal clip to a 15 second terminal of the second transistor; and attaching a second end portion of the fourth metal clip to the first conductive trace of the substrate with a middle B₂ portion of the fourth metal clip spaced apart from and at least partially overlying a portion of the third metal clip.
The method of claim 16, wherein attaching the end portions of the metal clips includes: providing solder to the respective transistor terminals and conductive traces; positioning the end portions of the metal clips on the solder; and reflowing the solder. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
electronic device with stacked metal clips and GaN transistor
half-bridge circuit with stacked metal clips
Materials described outside the worked examples.
first metal clip
second metal clip
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Cited non-patent literature · 2
Related documents with shared materials, methods, properties, or citations.
INTERCONNECT STRUCTURE FOR HIGH POWER GaN MODULE INCLUDING A PRINTED PLANAR INTERCONNECT LINE AND METHOD FOR MAKING THE SAME
GAN HEMT DEVICE FOR IRRADIATION DAMAGE DETECTION AND DETECTION AND MANUFACTURING METHOD THEREFOR
Patent
Atlas literature
Patent
US 12,456,707 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1.
FIG. 2 is a flow diagram of a method of making an electronic device.
FIGS. 3 and 3A are top plan and partial sectional side elevation views of the electronic device undergoing a sub- strate attach process.
FIG. 4 is a partial sectional side elevation view of the electronic device undergoing a die and passive component attach process.
FIG. 5 is a partial sectional side elevation view of the electronic device undergoing a first clip attach process.
FIG. 6 is a partial sectional side elevation view of the electronic device undergoing a second clip attach process.
FIG. 7 is a partial sectional side elevation view of the electronic device undergoing a third clip attach process.
FIG. 8 is a partial sectional side elevation view of the electronic device undergoing a fourth clip attach process.
FIGS. 9 and 9A are top plan and partial sectional side elevation views of the electronic device undergoing a ther- mal reflow process.
FIGS. 10 and 10A are top plan and partial sectional side elevation views of the electronic device undergoing a wire bonding electrical connection process.
FIG. 11 is a top plan view of the electronic device undergoing a molding process.
FIGS. 12 and 12A are top plan and partial sectional side elevation views of the electronic device undergoing a lead forming process.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device, comprising: a substrate having first and second conductive traces; a semiconductor die having a transistor with; a first terminal and a second terminal on a same side of the semiconductor die; a first metal clip having first and second end portions and a middle portion that joins the first and second end portions of the first metal clip, the first end portion of the first metal clip coupled to the first terminal of the transistor, and the second end portion of the first metal clip coupled to the first conductive trace of the substrate; and a second metal clip having first and second end portions and a middle portion that joins the first and second end portions of the second metal clip, the first end portion of the second metal clip coupled to the second terminal of the transistor, the second end portion of the second metal clip coupled to the second conductive trace of the substrate, and the middle portion of the second metal clip spaced apart from and at least partially overlying a portion of the first metal clip.
The electronic device of claim 1, further comprising: 5 a second semiconductor die having a second transistor with a first terminal and a second terminal; a third metal clip having first and second end portions and a middle portion that joins the first and second end portions of the third metal clip, the first end portion of the third metal clip coupled to the first terminal of the second transistor, and the second end portion of the third metal clip coupled to a third conductive trace of the substrate; and a fourth metal clip having first and second end portions and a middle portion that joins the first and second end portions of the fourth metal clip, the first end portion of the fourth metal clip coupled to the second terminal of the second transistor, the second end portion of the fourth metal clip coupled to the first conductive trace of the substrate, and the middle portion of the fourth metal clip spaced apart from and at least partially overlying a portion of the third metal clip.
The electronic device of claim 1, wherein a first transistor current of the transistor flows through the first and second metal clips in opposite respective first and second directions.
The electronic device of claim 1, wherein the transistor is a gallium nitride transistor.
The electronic device of claim 1, further comprising: a circuit board; and bond wires connecting conductive features of the circuit board to respective conductive features of the semicon-ductor die.
A half-bridge circuit, comprising: a first transistor with a first source and a first drain; a second transistor with a second source and a second drain; a first metal clip coupled between the first source and a switching node; a second metal clip at least partially overlying a portion of the first metal clip and coupled between the first drain and a supply node; a third metal clip coupled between the second source and a reference node; and a fourth metal clip at least partially overlying a portion of the third metal clip and coupled between the second drain and the switching node.
The half-bridge circuit of claim 12, wherein: the first metal clip has first and second end portions and a middle portion that joins the first and second end portions of the first metal clip, the first end portion of the first metal clip coupled to the first source, and the second end portion of the first metal clip coupled to the switching node; the second metal clip has first and second end portions and a middle portion that joins the first and second end portions of the second metal clip, the first end portion of the second metal clip coupled to the first drain, the second end portion of the second metal clip coupled to the supply node, and the middle portion of the second metal clip spaced apart from and at least partially overlying a portion of the first metal clip; the third metal clip has first and second end portions and a middle portion that joins the first and second end portions of the third metal clip, the first end portion of the third metal clip coupled to the second source, and the second end portion of the third metal clip coupled to the reference node; and the fourth metal clip has first and second end portions and a middle portion that joins the first and second end portions of the fourth metal clip, the first end portion of the fourth metal clip coupled to the second drain, the second end portion of the fourth metal clip coupled to the switching node, and the middle portion of the fourth metal clip spaced apart from and at least partially overlying a portion of the third metal clip.
The half-bridge circuit of claim 12, comprising: a substrate having first and second and third conductive traces that form the respective switching, supply, and reference nodes; a first semiconductor die mounted to the substrate and including the first transistor; and a second semiconductor die mounted to the substrate and including the second transistor.
A method of fabricating an electronic device, the method comprising: attaching a first end portion of a first metal clip to a first terminal of a transistor of a semiconductor die; attaching a second end portion of the first metal clip to a first conductive trace of a substrate; attaching a first end portion of; a second metal clip to a second terminal of the transistor, the first and second terminals on a same side of the semiconductor die; and attaching a second end portion of the second metal clip to a second conductive trace of the substrate with a middle portion of the second metal clip spaced apart from and at least partially overlying a portion of the first metal clip.
The method of claim 16, further comprising: attaching a first end portion of a third metal clip to a first terminal of a second transistor of a second semicon-ductor die; attaching a second end portion of the third metal clip to a third conductive trace of the substrate; attaching a first end portion of a fourth metal clip to a 15 second terminal of the second transistor; and attaching a second end portion of the fourth metal clip to the first conductive trace of the substrate with a middle B₂ portion of the fourth metal clip spaced apart from and at least partially overlying a portion of the third metal clip.
The method of claim 16, wherein attaching the end portions of the metal clips includes: providing solder to the respective transistor terminals and conductive traces; positioning the end portions of the metal clips on the solder; and reflowing the solder. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
electronic device with stacked metal clips and GaN transistor
half-bridge circuit with stacked metal clips
Materials described outside the worked examples.
first metal clip
second metal clip
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Cited non-patent literature · 2
Related documents with shared materials, methods, properties, or citations.
INTERCONNECT STRUCTURE FOR HIGH POWER GaN MODULE INCLUDING A PRINTED PLANAR INTERCONNECT LINE AND METHOD FOR MAKING THE SAME
GAN HEMT DEVICE FOR IRRADIATION DAMAGE DETECTION AND DETECTION AND MANUFACTURING METHOD THEREFOR
integrated power module (IPM) half bridge with GaN transistors
gallium nitride
GaN
solder
aluminum or copper
FIGS. 10 and 10A are top plan and partial sectional side elevation views of the electronic device undergoing a wire bonding electrical connection process.
integrated power module (IPM) half bridge with GaN transistors
gallium nitride
GaN
solder
aluminum or copper
FIGS. 10 and 10A are top plan and partial sectional side elevation views of the electronic device undergoing a wire bonding electrical connection process.
integrated power module (IPM) half bridge with GaN transistors
gallium nitride
GaN
solder
aluminum or copper
FIGS. 10 and 10A are top plan and partial sectional side elevation views of the electronic device undergoing a wire bonding electrical connection process.
integrated power module (IPM) half bridge with GaN transistors
gallium nitride
GaN
solder
aluminum or copper
FIGS. 10 and 10A are top plan and partial sectional side elevation views of the electronic device undergoing a wire bonding electrical connection process.