Patent
US 8,895,372GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE
Dechao Guo
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,895,372Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1 (a) through 1 (h) are a series of cross-sectional views illustrating an exemplary method of forming a graphene based, three-dimensional (3 D) integrated circuit, in accordance with an embodiment of the invention; and
Figures 2(a) through 2(k) are a series of cross-sectional views illustrating an exemplary method of forming a graphene based, 3D integrated circuit, in accordance with an alternative embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
AMENDMENTS TO THE CLAIMS 1. canceled
A method of forming a three-dimensional (3D) integrated circuit (IC) structure, the method comprising: forming a first layer of graphene over a substrate; forming a first level of one or more active devices using the first layer of graphene; forming an insulating layer over the first level of one or more active devices; forming a second layer of graphene over the insulating layer; and forming a second level of one or more active devices using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices; wherein the one or more active devices of the first and second levels comprises field effect transistors having a bottom gate orientation relationship with respect to the associated graphene layer, and wherein the bottom gate orientation field effect transistors are formed by: forming openings in an associated insulating layer in accordance with a desired gate pattern; filling the openings in the associated insulating layer with a gate electrode material and planarizing the gate electrode material to form individual gate electrodes; forming a gate dielectric layer over the individual gate electrodes; forming the associated graphene layer over the gate dielectric layer; 2 patterning the associated graphene layer and gate dielectric layer in accordance with a desired active layout area; forming one or more first level conductive pad structures adjacent the first layer of graphene such that a bottom surface of the one or more first level conductive pad structures is substantially co-planar with a bottom surface of the first layer of graphene; and forming one or more second level conductive pad structures adjacent the second layer of graphene such that a bottom surface of the one or more second level conductive pad structures is substantially co-planar with a bottom surface of the second layer of graphene; and forming a plurality of source and drain contacts disposed on the graphene la yers, above bottom oriented g ate electrodes under the graphene la yers.
The method of claim 2,wherein forming the first and second graphene layers comprises a dry thermal release tape process.
The method of claim 2, wherein the first and
The method of claim 2, wherein the one or different function with respect to the one or more second layers of graphene comprise monolayers. more field effect transistors of the first level has a field effect transistors of the second level. 3
canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based 3D integrated circuit with bottom-gate FETs
Materials described outside the worked examples.
graphene
gate dielectric
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,895,372Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1 (a) through 1 (h) are a series of cross-sectional views illustrating an exemplary method of forming a graphene based, three-dimensional (3 D) integrated circuit, in accordance with an embodiment of the invention; and
Figures 2(a) through 2(k) are a series of cross-sectional views illustrating an exemplary method of forming a graphene based, 3D integrated circuit, in accordance with an alternative embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
AMENDMENTS TO THE CLAIMS 1. canceled
A method of forming a three-dimensional (3D) integrated circuit (IC) structure, the method comprising: forming a first layer of graphene over a substrate; forming a first level of one or more active devices using the first layer of graphene; forming an insulating layer over the first level of one or more active devices; forming a second layer of graphene over the insulating layer; and forming a second level of one or more active devices using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices; wherein the one or more active devices of the first and second levels comprises field effect transistors having a bottom gate orientation relationship with respect to the associated graphene layer, and wherein the bottom gate orientation field effect transistors are formed by: forming openings in an associated insulating layer in accordance with a desired gate pattern; filling the openings in the associated insulating layer with a gate electrode material and planarizing the gate electrode material to form individual gate electrodes; forming a gate dielectric layer over the individual gate electrodes; forming the associated graphene layer over the gate dielectric layer; 2 patterning the associated graphene layer and gate dielectric layer in accordance with a desired active layout area; forming one or more first level conductive pad structures adjacent the first layer of graphene such that a bottom surface of the one or more first level conductive pad structures is substantially co-planar with a bottom surface of the first layer of graphene; and forming one or more second level conductive pad structures adjacent the second layer of graphene such that a bottom surface of the one or more second level conductive pad structures is substantially co-planar with a bottom surface of the second layer of graphene; and forming a plurality of source and drain contacts disposed on the graphene la yers, above bottom oriented g ate electrodes under the graphene la yers.
The method of claim 2,wherein forming the first and second graphene layers comprises a dry thermal release tape process.
The method of claim 2, wherein the first and
The method of claim 2, wherein the one or different function with respect to the one or more second layers of graphene comprise monolayers. more field effect transistors of the first level has a field effect transistors of the second level. 3
canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based 3D integrated circuit with bottom-gate FETs
Materials described outside the worked examples.
graphene
gate dielectric
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,895,372Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1 (a) through 1 (h) are a series of cross-sectional views illustrating an exemplary method of forming a graphene based, three-dimensional (3 D) integrated circuit, in accordance with an embodiment of the invention; and
Figures 2(a) through 2(k) are a series of cross-sectional views illustrating an exemplary method of forming a graphene based, 3D integrated circuit, in accordance with an alternative embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
AMENDMENTS TO THE CLAIMS 1. canceled
A method of forming a three-dimensional (3D) integrated circuit (IC) structure, the method comprising: forming a first layer of graphene over a substrate; forming a first level of one or more active devices using the first layer of graphene; forming an insulating layer over the first level of one or more active devices; forming a second layer of graphene over the insulating layer; and forming a second level of one or more active devices using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices; wherein the one or more active devices of the first and second levels comprises field effect transistors having a bottom gate orientation relationship with respect to the associated graphene layer, and wherein the bottom gate orientation field effect transistors are formed by: forming openings in an associated insulating layer in accordance with a desired gate pattern; filling the openings in the associated insulating layer with a gate electrode material and planarizing the gate electrode material to form individual gate electrodes; forming a gate dielectric layer over the individual gate electrodes; forming the associated graphene layer over the gate dielectric layer; 2 patterning the associated graphene layer and gate dielectric layer in accordance with a desired active layout area; forming one or more first level conductive pad structures adjacent the first layer of graphene such that a bottom surface of the one or more first level conductive pad structures is substantially co-planar with a bottom surface of the first layer of graphene; and forming one or more second level conductive pad structures adjacent the second layer of graphene such that a bottom surface of the one or more second level conductive pad structures is substantially co-planar with a bottom surface of the second layer of graphene; and forming a plurality of source and drain contacts disposed on the graphene la yers, above bottom oriented g ate electrodes under the graphene la yers.
The method of claim 2,wherein forming the first and second graphene layers comprises a dry thermal release tape process.
The method of claim 2, wherein the first and
The method of claim 2, wherein the one or different function with respect to the one or more second layers of graphene comprise monolayers. more field effect transistors of the first level has a field effect transistors of the second level. 3
canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based 3D integrated circuit with bottom-gate FETs
Materials described outside the worked examples.
graphene
gate dielectric
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,895,372Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1 (a) through 1 (h) are a series of cross-sectional views illustrating an exemplary method of forming a graphene based, three-dimensional (3 D) integrated circuit, in accordance with an embodiment of the invention; and
Figures 2(a) through 2(k) are a series of cross-sectional views illustrating an exemplary method of forming a graphene based, 3D integrated circuit, in accordance with an alternative embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
AMENDMENTS TO THE CLAIMS 1. canceled
A method of forming a three-dimensional (3D) integrated circuit (IC) structure, the method comprising: forming a first layer of graphene over a substrate; forming a first level of one or more active devices using the first layer of graphene; forming an insulating layer over the first level of one or more active devices; forming a second layer of graphene over the insulating layer; and forming a second level of one or more active devices using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices; wherein the one or more active devices of the first and second levels comprises field effect transistors having a bottom gate orientation relationship with respect to the associated graphene layer, and wherein the bottom gate orientation field effect transistors are formed by: forming openings in an associated insulating layer in accordance with a desired gate pattern; filling the openings in the associated insulating layer with a gate electrode material and planarizing the gate electrode material to form individual gate electrodes; forming a gate dielectric layer over the individual gate electrodes; forming the associated graphene layer over the gate dielectric layer; 2 patterning the associated graphene layer and gate dielectric layer in accordance with a desired active layout area; forming one or more first level conductive pad structures adjacent the first layer of graphene such that a bottom surface of the one or more first level conductive pad structures is substantially co-planar with a bottom surface of the first layer of graphene; and forming one or more second level conductive pad structures adjacent the second layer of graphene such that a bottom surface of the one or more second level conductive pad structures is substantially co-planar with a bottom surface of the second layer of graphene; and forming a plurality of source and drain contacts disposed on the graphene la yers, above bottom oriented g ate electrodes under the graphene la yers.
The method of claim 2,wherein forming the first and second graphene layers comprises a dry thermal release tape process.
The method of claim 2, wherein the first and
The method of claim 2, wherein the one or different function with respect to the one or more second layers of graphene comprise monolayers. more field effect transistors of the first level has a field effect transistors of the second level. 3
canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based 3D integrated circuit with bottom-gate FETs
Materials described outside the worked examples.
graphene
gate dielectric
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
gate electrode material
high-k gate dielectric
hafnium oxide
hafnium silicate
zirconium oxide
ZrO₂
zirconium silicate
polysilicon gate electrode
titanium source/drain contact
Ti
palladium source/drain contact
Pd
aluminum source/drain contact
Al
tungsten source/drain contact
W
insulating layer (oxide)
silicon dioxide insulating layer
SiO₂
PROVIDING A TEMPORARY PROTECTIVE LAYER ON A GRAPHENE SHEET
Methods of manufacturing and transferring larger-sized graphene
gate electrode material
high-k gate dielectric
hafnium oxide
hafnium silicate
zirconium oxide
ZrO₂
zirconium silicate
polysilicon gate electrode
titanium source/drain contact
Ti
palladium source/drain contact
Pd
aluminum source/drain contact
Al
tungsten source/drain contact
W
insulating layer (oxide)
silicon dioxide insulating layer
SiO₂
PROVIDING A TEMPORARY PROTECTIVE LAYER ON A GRAPHENE SHEET
Methods of manufacturing and transferring larger-sized graphene
gate electrode material
high-k gate dielectric
hafnium oxide
hafnium silicate
zirconium oxide
ZrO₂
zirconium silicate
polysilicon gate electrode
titanium source/drain contact
Ti
palladium source/drain contact
Pd
aluminum source/drain contact
Al
tungsten source/drain contact
W
insulating layer (oxide)
silicon dioxide insulating layer
SiO₂
PROVIDING A TEMPORARY PROTECTIVE LAYER ON A GRAPHENE SHEET
Methods of manufacturing and transferring larger-sized graphene
gate electrode material
high-k gate dielectric
hafnium oxide
hafnium silicate
zirconium oxide
ZrO₂
zirconium silicate
polysilicon gate electrode
titanium source/drain contact
Ti
palladium source/drain contact
Pd
aluminum source/drain contact
Al
tungsten source/drain contact
W
insulating layer (oxide)
silicon dioxide insulating layer
SiO₂
PROVIDING A TEMPORARY PROTECTIVE LAYER ON A GRAPHENE SHEET