Patent
US 10,170,580STRUCTURE OF GaN-BASED TRANSISTOR AND METHOD OF FABRICATING THE SAME
Kan-Hsueh Tsai
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,170,580Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 to
FIG. 2. As shown, a part of the channel layer 120 is exposed. Also, the barrier layer 130 and the passivation layer 140 expose a first side wall 101 and a …
FIG. 3, an electrode layer 160 is formed after patterning the barrier layer 130, the passivation layer 140, and the barrier barrier metal layer 150. The …
FIG. 4, the electrode layer 160 and the barrier metal layer 150 are patterned after the electrode layer 160 is formed. As shown, a first opening 103 is formed, …
FIG. 5 are illustrating a manufacturing process of a GaN-based transistor device of an embodiment of the disclosure. [0009]
FIG. 6 to
FIG. 7. As shown, a part of the channel layer 120 is exposed. Also, the barrier layer 130 and the passivation layer 140 expose the first side wall 101 and the …
FIG. 8, a second barrier metal layer 250b is formed after patterning the barrier layer 130 and the passivation layer 140. The second barrier metal layer 250b …
FIG. 9, the second barrier metal layer 250b is etched to remove a part of the second barrier metal layer 250b covered the channel layer 120 and another part of …
FIG. 10. The method of forming the electrode layer 260 is physical vaper deposition, for example. The material of the electrode layer 260 is a stacked layer of …
FIG. 11, the electrode layer 260 and the barrier metal layer 250 are patterned after the electrode layer 260 is formed. As a result, a first opening 203 is …
FIG. 12 are illustrating a manufacturing process of a GaN-based transistor device of another embodiment of the disclosure. [0010]
FIG. 13A is a cross section view of a GaN-based transistor device of still another embodiment of the disclosure. [0011]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based transistor device, comprising: a substrate; a buffer layer, disposed on the substrate; a channel layer, disposed on the buffer layer; a barrier layer, disposed on a part of the channel layer; a passivation layer, disposed on the barrier layer, wherein the barrier layer and the passivation layer comprise a first side wall and a second side wall, and the first side wall and the second side wall are corresponding to each other; a barrier metal layer, disposed on the passivation layer, wherein the barrier metal layer has a first opening that exposes a part of the passivation layer, and the passivation layer has a second opening located in the first opening to expose a part of the barrier layer; a gate electrode, disposed on the exposed part of the barrier layer; a source electrode, disposed on the channel layer, wherein the source electrode covers the first side wall and a part of the barrier metal layer adjacent to the first side wall; and Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA a drain electrode, disposed on the channel layer, wherein the drain electrode covers the second side wall and another part of the barrier metal layer adjacent to the second side wall; wherein the gate electrode is disposed between the source electrode and the drain electrode; wherein an interface between the source electrode and the channel layer is an Ohmic contact; wherein an interface between the drain electrode and the channel layer is another Ohmic contact; wherein an interface between the gate electrode and the barrier layer is a Schottky contact.
The GaN-based transistor device as claimed in claim 1, wherein the barrier metal layer further extends to cover the first side wall and the second side wall, the barrier metal layer is disposed between the source electrode and the first side wall, and the barrier metal layer is disposed between the drain electrode and the second side wall.
The GaN-based transistor device as claimed in claim 1, further comprising a nucleation layer disposed between the substrate and the buffer layer.
The GaN-based transistor device as claimed in claim 1, wherein a material of the substrate is Si.
The GaN-based transistor device as claimed in claim 1, wherein a material of the buffer layer is AIGaN.
The GaN-based transistor device as claimed in claim 1, wherein a material of the channel layer is GaN.
The GaN-based transistor device as claimed in claim 1, wherein the barrier layer comprises an AIGaN layer and a GaN layer, and the GaN layer is disposed on the AIGaN layer.
The GaN-based transistor device as claimed in claim 1, wherein the passivation layer comprises a low temperature nitride layer and a low temperature oxide layer, and the low temperature oxide layer is disposed on the low temperature nitride layer.
The GaN-based transistor device as claimed in claim 1, wherein a material of the barrier metal layer comprises AIN, A 1 2 0 3, a stacked layer of Ti/TiN, a stacked layer of Ti/TiN/Ti/TiN, or a stacked layer of Ta/TaN; wherein Ti/TiN represents that a TiN layer is disposed on a Ti layer; and Ta/TaN represents that a TaN layer is disposed on a Ta layer.
A manufacturing method of a GaN-based transistor device, comprising: providing a substrate; Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA forming a buffer layer on the substrate; forming a channel layer on the buffer layer; forming a barrier layer on the channel layer; forming a passivation layer on the barrier layer; forming a barrier metal layer on the passivation layer; patterning the barrier layer, the passivation layer, and the barrier metal layer to expose a part of the channel layer, wherein the barrier layer and the passivation layer expose a first side wall and a second side wall, wherein the first side wall and the second side wall are corresponding to each other, wherein the first side wall, the second side wall, and the barrier metal layer forms a mesa structure; forming an electrode layer to cover the channel layer, the barrier metal layer, the first side wall, and the second side wall; patterning the electrode layer and the barrier metal layer to form a first opening, wherein the first opening exposes a part of the passivation layer and divides the electrode layer into a source electrode and a drain electrode; performing a rapid thermal process; patterning the passivation layer to form a second opening, wherein the Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA second opening is located in the first opening and exposes a part of the barrier layer, wherein the source electrode is disposed on the part of the exposed channel layer and covers the first side wall, wherein the drain electrode is disposed on the part of the exposed channel layer and covers the second side wall; and forming a gate electrode on the exposed part of the barrier layer; wherein the gate electrode is disposed between the source electrode and the drain electrode; wherein an interface between the source electrode and the channel layer is an Ohmic contact; wherein an interface between the drain electrode and the channel layer is another Ohmic contact; wherein an interface between the gate electrode and the barrier layer is a Schottky contact.
The manufacturing method of the GaN-based transistor device of claim 11, wherein after the barrier layer, the passivation layer, and the barrier metal layer are patterned to expose the channel layer, and the barrier metal layer is formed to extend to cover the first side wall and the second side wall; wherein the barrier metal layer is disposed between the source electrode and the first side wall; wherein the barrier metal layer is disposed between the drain electrode and the second side wall.
The manufacturing method of the GaN-based transistor device of claim 11, wherein before forming the buffer layer, a nucleation layer is formed Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA on the substrate, and the nucleation layer is disposed between the substrate and the buffer layer.
The manufacturing method of the GaN-based transistor device of claim 11, wherein a material of the substrate is Si.
The manufacturing method of the GaN-based transistor device of claim 11, wherein a material of the buffer layer is AIGaN.
The manufacturing method of the GaN-based transistor device of claim 11, wherein a material of the channel layer is GaN.
The manufacturing method of the GaN-based transistor device of claim 11, wherein forming the barrier layer comprises: forming an AIGaN layer, and forming a GaN layer on the AIGaN layer.
The manufacturing method of the GaN-based transistor device of claim 11, wherein forming the passivation layer comprises: forming a low temperature nitride layer, and forming a low temperature oxide layer on the low temperature nitride layer, wherein a temperature of forming the low temperature nitride layer and the low temperature oxide layer is lower than 250 *C.
The manufacturing method of the GaN-based transistor device of claim 11, wherein forming the barrier metal layer comprises: forming an AIN layer, forming an A 1 2 0 3 layer, forming a stacked layer of Ti/TiN, forming a Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA stacked layer of Ti/TiN/Ti/TiN, or forming a stacked layer of Ta/TaN; wherein Ti/TiN represents that a TiN layer is disposed on a Ti layer; and Ta/TaN represents that a TaN layer is disposed on a Ta layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based transistor (HEMT)
Materials described outside the worked examples.
GaN
AlGaN
passivation layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 are illustrating a manufacturing process of a GaN-based transistor device of an embodiment of the disclosure. [0009]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Duration | ≥ 60 seconds | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,170,580Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 to
FIG. 2. As shown, a part of the channel layer 120 is exposed. Also, the barrier layer 130 and the passivation layer 140 expose a first side wall 101 and a …
FIG. 3, an electrode layer 160 is formed after patterning the barrier layer 130, the passivation layer 140, and the barrier barrier metal layer 150. The …
FIG. 4, the electrode layer 160 and the barrier metal layer 150 are patterned after the electrode layer 160 is formed. As shown, a first opening 103 is formed, …
FIG. 5 are illustrating a manufacturing process of a GaN-based transistor device of an embodiment of the disclosure. [0009]
FIG. 6 to
FIG. 7. As shown, a part of the channel layer 120 is exposed. Also, the barrier layer 130 and the passivation layer 140 expose the first side wall 101 and the …
FIG. 8, a second barrier metal layer 250b is formed after patterning the barrier layer 130 and the passivation layer 140. The second barrier metal layer 250b …
FIG. 9, the second barrier metal layer 250b is etched to remove a part of the second barrier metal layer 250b covered the channel layer 120 and another part of …
FIG. 10. The method of forming the electrode layer 260 is physical vaper deposition, for example. The material of the electrode layer 260 is a stacked layer of …
FIG. 11, the electrode layer 260 and the barrier metal layer 250 are patterned after the electrode layer 260 is formed. As a result, a first opening 203 is …
FIG. 12 are illustrating a manufacturing process of a GaN-based transistor device of another embodiment of the disclosure. [0010]
FIG. 13A is a cross section view of a GaN-based transistor device of still another embodiment of the disclosure. [0011]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based transistor device, comprising: a substrate; a buffer layer, disposed on the substrate; a channel layer, disposed on the buffer layer; a barrier layer, disposed on a part of the channel layer; a passivation layer, disposed on the barrier layer, wherein the barrier layer and the passivation layer comprise a first side wall and a second side wall, and the first side wall and the second side wall are corresponding to each other; a barrier metal layer, disposed on the passivation layer, wherein the barrier metal layer has a first opening that exposes a part of the passivation layer, and the passivation layer has a second opening located in the first opening to expose a part of the barrier layer; a gate electrode, disposed on the exposed part of the barrier layer; a source electrode, disposed on the channel layer, wherein the source electrode covers the first side wall and a part of the barrier metal layer adjacent to the first side wall; and Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA a drain electrode, disposed on the channel layer, wherein the drain electrode covers the second side wall and another part of the barrier metal layer adjacent to the second side wall; wherein the gate electrode is disposed between the source electrode and the drain electrode; wherein an interface between the source electrode and the channel layer is an Ohmic contact; wherein an interface between the drain electrode and the channel layer is another Ohmic contact; wherein an interface between the gate electrode and the barrier layer is a Schottky contact.
The GaN-based transistor device as claimed in claim 1, wherein the barrier metal layer further extends to cover the first side wall and the second side wall, the barrier metal layer is disposed between the source electrode and the first side wall, and the barrier metal layer is disposed between the drain electrode and the second side wall.
The GaN-based transistor device as claimed in claim 1, further comprising a nucleation layer disposed between the substrate and the buffer layer.
The GaN-based transistor device as claimed in claim 1, wherein a material of the substrate is Si.
The GaN-based transistor device as claimed in claim 1, wherein a material of the buffer layer is AIGaN.
The GaN-based transistor device as claimed in claim 1, wherein a material of the channel layer is GaN.
The GaN-based transistor device as claimed in claim 1, wherein the barrier layer comprises an AIGaN layer and a GaN layer, and the GaN layer is disposed on the AIGaN layer.
The GaN-based transistor device as claimed in claim 1, wherein the passivation layer comprises a low temperature nitride layer and a low temperature oxide layer, and the low temperature oxide layer is disposed on the low temperature nitride layer.
The GaN-based transistor device as claimed in claim 1, wherein a material of the barrier metal layer comprises AIN, A 1 2 0 3, a stacked layer of Ti/TiN, a stacked layer of Ti/TiN/Ti/TiN, or a stacked layer of Ta/TaN; wherein Ti/TiN represents that a TiN layer is disposed on a Ti layer; and Ta/TaN represents that a TaN layer is disposed on a Ta layer.
A manufacturing method of a GaN-based transistor device, comprising: providing a substrate; Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA forming a buffer layer on the substrate; forming a channel layer on the buffer layer; forming a barrier layer on the channel layer; forming a passivation layer on the barrier layer; forming a barrier metal layer on the passivation layer; patterning the barrier layer, the passivation layer, and the barrier metal layer to expose a part of the channel layer, wherein the barrier layer and the passivation layer expose a first side wall and a second side wall, wherein the first side wall and the second side wall are corresponding to each other, wherein the first side wall, the second side wall, and the barrier metal layer forms a mesa structure; forming an electrode layer to cover the channel layer, the barrier metal layer, the first side wall, and the second side wall; patterning the electrode layer and the barrier metal layer to form a first opening, wherein the first opening exposes a part of the passivation layer and divides the electrode layer into a source electrode and a drain electrode; performing a rapid thermal process; patterning the passivation layer to form a second opening, wherein the Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA second opening is located in the first opening and exposes a part of the barrier layer, wherein the source electrode is disposed on the part of the exposed channel layer and covers the first side wall, wherein the drain electrode is disposed on the part of the exposed channel layer and covers the second side wall; and forming a gate electrode on the exposed part of the barrier layer; wherein the gate electrode is disposed between the source electrode and the drain electrode; wherein an interface between the source electrode and the channel layer is an Ohmic contact; wherein an interface between the drain electrode and the channel layer is another Ohmic contact; wherein an interface between the gate electrode and the barrier layer is a Schottky contact.
The manufacturing method of the GaN-based transistor device of claim 11, wherein after the barrier layer, the passivation layer, and the barrier metal layer are patterned to expose the channel layer, and the barrier metal layer is formed to extend to cover the first side wall and the second side wall; wherein the barrier metal layer is disposed between the source electrode and the first side wall; wherein the barrier metal layer is disposed between the drain electrode and the second side wall.
The manufacturing method of the GaN-based transistor device of claim 11, wherein before forming the buffer layer, a nucleation layer is formed Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA on the substrate, and the nucleation layer is disposed between the substrate and the buffer layer.
The manufacturing method of the GaN-based transistor device of claim 11, wherein a material of the substrate is Si.
The manufacturing method of the GaN-based transistor device of claim 11, wherein a material of the buffer layer is AIGaN.
The manufacturing method of the GaN-based transistor device of claim 11, wherein a material of the channel layer is GaN.
The manufacturing method of the GaN-based transistor device of claim 11, wherein forming the barrier layer comprises: forming an AIGaN layer, and forming a GaN layer on the AIGaN layer.
The manufacturing method of the GaN-based transistor device of claim 11, wherein forming the passivation layer comprises: forming a low temperature nitride layer, and forming a low temperature oxide layer on the low temperature nitride layer, wherein a temperature of forming the low temperature nitride layer and the low temperature oxide layer is lower than 250 *C.
The manufacturing method of the GaN-based transistor device of claim 11, wherein forming the barrier metal layer comprises: forming an AIN layer, forming an A 1 2 0 3 layer, forming a stacked layer of Ti/TiN, forming a Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA stacked layer of Ti/TiN/Ti/TiN, or forming a stacked layer of Ta/TaN; wherein Ti/TiN represents that a TiN layer is disposed on a Ti layer; and Ta/TaN represents that a TaN layer is disposed on a Ta layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based transistor (HEMT)
Materials described outside the worked examples.
GaN
AlGaN
passivation layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 are illustrating a manufacturing process of a GaN-based transistor device of an embodiment of the disclosure. [0009]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Duration | ≥ 60 seconds | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,170,580Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 to
FIG. 2. As shown, a part of the channel layer 120 is exposed. Also, the barrier layer 130 and the passivation layer 140 expose a first side wall 101 and a …
FIG. 3, an electrode layer 160 is formed after patterning the barrier layer 130, the passivation layer 140, and the barrier barrier metal layer 150. The …
FIG. 4, the electrode layer 160 and the barrier metal layer 150 are patterned after the electrode layer 160 is formed. As shown, a first opening 103 is formed, …
FIG. 5 are illustrating a manufacturing process of a GaN-based transistor device of an embodiment of the disclosure. [0009]
FIG. 6 to
FIG. 7. As shown, a part of the channel layer 120 is exposed. Also, the barrier layer 130 and the passivation layer 140 expose the first side wall 101 and the …
FIG. 8, a second barrier metal layer 250b is formed after patterning the barrier layer 130 and the passivation layer 140. The second barrier metal layer 250b …
FIG. 9, the second barrier metal layer 250b is etched to remove a part of the second barrier metal layer 250b covered the channel layer 120 and another part of …
FIG. 10. The method of forming the electrode layer 260 is physical vaper deposition, for example. The material of the electrode layer 260 is a stacked layer of …
FIG. 11, the electrode layer 260 and the barrier metal layer 250 are patterned after the electrode layer 260 is formed. As a result, a first opening 203 is …
FIG. 12 are illustrating a manufacturing process of a GaN-based transistor device of another embodiment of the disclosure. [0010]
FIG. 13A is a cross section view of a GaN-based transistor device of still another embodiment of the disclosure. [0011]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based transistor device, comprising: a substrate; a buffer layer, disposed on the substrate; a channel layer, disposed on the buffer layer; a barrier layer, disposed on a part of the channel layer; a passivation layer, disposed on the barrier layer, wherein the barrier layer and the passivation layer comprise a first side wall and a second side wall, and the first side wall and the second side wall are corresponding to each other; a barrier metal layer, disposed on the passivation layer, wherein the barrier metal layer has a first opening that exposes a part of the passivation layer, and the passivation layer has a second opening located in the first opening to expose a part of the barrier layer; a gate electrode, disposed on the exposed part of the barrier layer; a source electrode, disposed on the channel layer, wherein the source electrode covers the first side wall and a part of the barrier metal layer adjacent to the first side wall; and Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA a drain electrode, disposed on the channel layer, wherein the drain electrode covers the second side wall and another part of the barrier metal layer adjacent to the second side wall; wherein the gate electrode is disposed between the source electrode and the drain electrode; wherein an interface between the source electrode and the channel layer is an Ohmic contact; wherein an interface between the drain electrode and the channel layer is another Ohmic contact; wherein an interface between the gate electrode and the barrier layer is a Schottky contact.
The GaN-based transistor device as claimed in claim 1, wherein the barrier metal layer further extends to cover the first side wall and the second side wall, the barrier metal layer is disposed between the source electrode and the first side wall, and the barrier metal layer is disposed between the drain electrode and the second side wall.
The GaN-based transistor device as claimed in claim 1, further comprising a nucleation layer disposed between the substrate and the buffer layer.
The GaN-based transistor device as claimed in claim 1, wherein a material of the substrate is Si.
The GaN-based transistor device as claimed in claim 1, wherein a material of the buffer layer is AIGaN.
The GaN-based transistor device as claimed in claim 1, wherein a material of the channel layer is GaN.
The GaN-based transistor device as claimed in claim 1, wherein the barrier layer comprises an AIGaN layer and a GaN layer, and the GaN layer is disposed on the AIGaN layer.
The GaN-based transistor device as claimed in claim 1, wherein the passivation layer comprises a low temperature nitride layer and a low temperature oxide layer, and the low temperature oxide layer is disposed on the low temperature nitride layer.
The GaN-based transistor device as claimed in claim 1, wherein a material of the barrier metal layer comprises AIN, A 1 2 0 3, a stacked layer of Ti/TiN, a stacked layer of Ti/TiN/Ti/TiN, or a stacked layer of Ta/TaN; wherein Ti/TiN represents that a TiN layer is disposed on a Ti layer; and Ta/TaN represents that a TaN layer is disposed on a Ta layer.
A manufacturing method of a GaN-based transistor device, comprising: providing a substrate; Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA forming a buffer layer on the substrate; forming a channel layer on the buffer layer; forming a barrier layer on the channel layer; forming a passivation layer on the barrier layer; forming a barrier metal layer on the passivation layer; patterning the barrier layer, the passivation layer, and the barrier metal layer to expose a part of the channel layer, wherein the barrier layer and the passivation layer expose a first side wall and a second side wall, wherein the first side wall and the second side wall are corresponding to each other, wherein the first side wall, the second side wall, and the barrier metal layer forms a mesa structure; forming an electrode layer to cover the channel layer, the barrier metal layer, the first side wall, and the second side wall; patterning the electrode layer and the barrier metal layer to form a first opening, wherein the first opening exposes a part of the passivation layer and divides the electrode layer into a source electrode and a drain electrode; performing a rapid thermal process; patterning the passivation layer to form a second opening, wherein the Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA second opening is located in the first opening and exposes a part of the barrier layer, wherein the source electrode is disposed on the part of the exposed channel layer and covers the first side wall, wherein the drain electrode is disposed on the part of the exposed channel layer and covers the second side wall; and forming a gate electrode on the exposed part of the barrier layer; wherein the gate electrode is disposed between the source electrode and the drain electrode; wherein an interface between the source electrode and the channel layer is an Ohmic contact; wherein an interface between the drain electrode and the channel layer is another Ohmic contact; wherein an interface between the gate electrode and the barrier layer is a Schottky contact.
The manufacturing method of the GaN-based transistor device of claim 11, wherein after the barrier layer, the passivation layer, and the barrier metal layer are patterned to expose the channel layer, and the barrier metal layer is formed to extend to cover the first side wall and the second side wall; wherein the barrier metal layer is disposed between the source electrode and the first side wall; wherein the barrier metal layer is disposed between the drain electrode and the second side wall.
The manufacturing method of the GaN-based transistor device of claim 11, wherein before forming the buffer layer, a nucleation layer is formed Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA on the substrate, and the nucleation layer is disposed between the substrate and the buffer layer.
The manufacturing method of the GaN-based transistor device of claim 11, wherein a material of the substrate is Si.
The manufacturing method of the GaN-based transistor device of claim 11, wherein a material of the buffer layer is AIGaN.
The manufacturing method of the GaN-based transistor device of claim 11, wherein a material of the channel layer is GaN.
The manufacturing method of the GaN-based transistor device of claim 11, wherein forming the barrier layer comprises: forming an AIGaN layer, and forming a GaN layer on the AIGaN layer.
The manufacturing method of the GaN-based transistor device of claim 11, wherein forming the passivation layer comprises: forming a low temperature nitride layer, and forming a low temperature oxide layer on the low temperature nitride layer, wherein a temperature of forming the low temperature nitride layer and the low temperature oxide layer is lower than 250 *C.
The manufacturing method of the GaN-based transistor device of claim 11, wherein forming the barrier metal layer comprises: forming an AIN layer, forming an A 1 2 0 3 layer, forming a stacked layer of Ti/TiN, forming a Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA stacked layer of Ti/TiN/Ti/TiN, or forming a stacked layer of Ta/TaN; wherein Ti/TiN represents that a TiN layer is disposed on a Ti layer; and Ta/TaN represents that a TaN layer is disposed on a Ta layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based transistor (HEMT)
Materials described outside the worked examples.
GaN
AlGaN
passivation layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 are illustrating a manufacturing process of a GaN-based transistor device of an embodiment of the disclosure. [0009]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Duration | ≥ 60 seconds | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,170,580Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 to
FIG. 2. As shown, a part of the channel layer 120 is exposed. Also, the barrier layer 130 and the passivation layer 140 expose a first side wall 101 and a …
FIG. 3, an electrode layer 160 is formed after patterning the barrier layer 130, the passivation layer 140, and the barrier barrier metal layer 150. The …
FIG. 4, the electrode layer 160 and the barrier metal layer 150 are patterned after the electrode layer 160 is formed. As shown, a first opening 103 is formed, …
FIG. 5 are illustrating a manufacturing process of a GaN-based transistor device of an embodiment of the disclosure. [0009]
FIG. 6 to
FIG. 7. As shown, a part of the channel layer 120 is exposed. Also, the barrier layer 130 and the passivation layer 140 expose the first side wall 101 and the …
FIG. 8, a second barrier metal layer 250b is formed after patterning the barrier layer 130 and the passivation layer 140. The second barrier metal layer 250b …
FIG. 9, the second barrier metal layer 250b is etched to remove a part of the second barrier metal layer 250b covered the channel layer 120 and another part of …
FIG. 10. The method of forming the electrode layer 260 is physical vaper deposition, for example. The material of the electrode layer 260 is a stacked layer of …
FIG. 11, the electrode layer 260 and the barrier metal layer 250 are patterned after the electrode layer 260 is formed. As a result, a first opening 203 is …
FIG. 12 are illustrating a manufacturing process of a GaN-based transistor device of another embodiment of the disclosure. [0010]
FIG. 13A is a cross section view of a GaN-based transistor device of still another embodiment of the disclosure. [0011]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based transistor device, comprising: a substrate; a buffer layer, disposed on the substrate; a channel layer, disposed on the buffer layer; a barrier layer, disposed on a part of the channel layer; a passivation layer, disposed on the barrier layer, wherein the barrier layer and the passivation layer comprise a first side wall and a second side wall, and the first side wall and the second side wall are corresponding to each other; a barrier metal layer, disposed on the passivation layer, wherein the barrier metal layer has a first opening that exposes a part of the passivation layer, and the passivation layer has a second opening located in the first opening to expose a part of the barrier layer; a gate electrode, disposed on the exposed part of the barrier layer; a source electrode, disposed on the channel layer, wherein the source electrode covers the first side wall and a part of the barrier metal layer adjacent to the first side wall; and Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA a drain electrode, disposed on the channel layer, wherein the drain electrode covers the second side wall and another part of the barrier metal layer adjacent to the second side wall; wherein the gate electrode is disposed between the source electrode and the drain electrode; wherein an interface between the source electrode and the channel layer is an Ohmic contact; wherein an interface between the drain electrode and the channel layer is another Ohmic contact; wherein an interface between the gate electrode and the barrier layer is a Schottky contact.
The GaN-based transistor device as claimed in claim 1, wherein the barrier metal layer further extends to cover the first side wall and the second side wall, the barrier metal layer is disposed between the source electrode and the first side wall, and the barrier metal layer is disposed between the drain electrode and the second side wall.
The GaN-based transistor device as claimed in claim 1, further comprising a nucleation layer disposed between the substrate and the buffer layer.
The GaN-based transistor device as claimed in claim 1, wherein a material of the substrate is Si.
The GaN-based transistor device as claimed in claim 1, wherein a material of the buffer layer is AIGaN.
The GaN-based transistor device as claimed in claim 1, wherein a material of the channel layer is GaN.
The GaN-based transistor device as claimed in claim 1, wherein the barrier layer comprises an AIGaN layer and a GaN layer, and the GaN layer is disposed on the AIGaN layer.
The GaN-based transistor device as claimed in claim 1, wherein the passivation layer comprises a low temperature nitride layer and a low temperature oxide layer, and the low temperature oxide layer is disposed on the low temperature nitride layer.
The GaN-based transistor device as claimed in claim 1, wherein a material of the barrier metal layer comprises AIN, A 1 2 0 3, a stacked layer of Ti/TiN, a stacked layer of Ti/TiN/Ti/TiN, or a stacked layer of Ta/TaN; wherein Ti/TiN represents that a TiN layer is disposed on a Ti layer; and Ta/TaN represents that a TaN layer is disposed on a Ta layer.
A manufacturing method of a GaN-based transistor device, comprising: providing a substrate; Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA forming a buffer layer on the substrate; forming a channel layer on the buffer layer; forming a barrier layer on the channel layer; forming a passivation layer on the barrier layer; forming a barrier metal layer on the passivation layer; patterning the barrier layer, the passivation layer, and the barrier metal layer to expose a part of the channel layer, wherein the barrier layer and the passivation layer expose a first side wall and a second side wall, wherein the first side wall and the second side wall are corresponding to each other, wherein the first side wall, the second side wall, and the barrier metal layer forms a mesa structure; forming an electrode layer to cover the channel layer, the barrier metal layer, the first side wall, and the second side wall; patterning the electrode layer and the barrier metal layer to form a first opening, wherein the first opening exposes a part of the passivation layer and divides the electrode layer into a source electrode and a drain electrode; performing a rapid thermal process; patterning the passivation layer to form a second opening, wherein the Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA second opening is located in the first opening and exposes a part of the barrier layer, wherein the source electrode is disposed on the part of the exposed channel layer and covers the first side wall, wherein the drain electrode is disposed on the part of the exposed channel layer and covers the second side wall; and forming a gate electrode on the exposed part of the barrier layer; wherein the gate electrode is disposed between the source electrode and the drain electrode; wherein an interface between the source electrode and the channel layer is an Ohmic contact; wherein an interface between the drain electrode and the channel layer is another Ohmic contact; wherein an interface between the gate electrode and the barrier layer is a Schottky contact.
The manufacturing method of the GaN-based transistor device of claim 11, wherein after the barrier layer, the passivation layer, and the barrier metal layer are patterned to expose the channel layer, and the barrier metal layer is formed to extend to cover the first side wall and the second side wall; wherein the barrier metal layer is disposed between the source electrode and the first side wall; wherein the barrier metal layer is disposed between the drain electrode and the second side wall.
The manufacturing method of the GaN-based transistor device of claim 11, wherein before forming the buffer layer, a nucleation layer is formed Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA on the substrate, and the nucleation layer is disposed between the substrate and the buffer layer.
The manufacturing method of the GaN-based transistor device of claim 11, wherein a material of the substrate is Si.
The manufacturing method of the GaN-based transistor device of claim 11, wherein a material of the buffer layer is AIGaN.
The manufacturing method of the GaN-based transistor device of claim 11, wherein a material of the channel layer is GaN.
The manufacturing method of the GaN-based transistor device of claim 11, wherein forming the barrier layer comprises: forming an AIGaN layer, and forming a GaN layer on the AIGaN layer.
The manufacturing method of the GaN-based transistor device of claim 11, wherein forming the passivation layer comprises: forming a low temperature nitride layer, and forming a low temperature oxide layer on the low temperature nitride layer, wherein a temperature of forming the low temperature nitride layer and the low temperature oxide layer is lower than 250 *C.
The manufacturing method of the GaN-based transistor device of claim 11, wherein forming the barrier metal layer comprises: forming an AIN layer, forming an A 1 2 0 3 layer, forming a stacked layer of Ti/TiN, forming a Reference of Assignee: P₅₁₀₆₀₀₀₉US/Reference of SUNDIAL: US₁₂₇₂₄PA stacked layer of Ti/TiN/Ti/TiN, or forming a stacked layer of Ta/TaN; wherein Ti/TiN represents that a TiN layer is disposed on a Ti layer; and Ta/TaN represents that a TaN layer is disposed on a Ta layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based transistor (HEMT)
Materials described outside the worked examples.
GaN
AlGaN
passivation layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 are illustrating a manufacturing process of a GaN-based transistor device of an embodiment of the disclosure. [0009]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Duration | ≥ 60 seconds | — |
Related documents with shared materials, methods, properties, or citations.
barrier metal layer
Si
low temperature nitride
low temperature oxide
AlN
Al₂O₃
Ti/TiN stacked layer
Ti/TiN/Ti/TiN stacked layer
Ta/TaN stacked layer
Ti/Al/TiN stacked layer
TiN/Ti/Al/TiN stacked layer
FIG. 12 are illustrating a manufacturing process of a GaN-based transistor device of another embodiment of the disclosure. [0010]
FIG. 13A is a cross section view of a GaN-based transistor device of still another embodiment of the disclosure. [0011]
barrier metal layer
Si
low temperature nitride
low temperature oxide
AlN
Al₂O₃
Ti/TiN stacked layer
Ti/TiN/Ti/TiN stacked layer
Ta/TaN stacked layer
Ti/Al/TiN stacked layer
TiN/Ti/Al/TiN stacked layer
FIG. 12 are illustrating a manufacturing process of a GaN-based transistor device of another embodiment of the disclosure. [0010]
FIG. 13A is a cross section view of a GaN-based transistor device of still another embodiment of the disclosure. [0011]
barrier metal layer
Si
low temperature nitride
low temperature oxide
AlN
Al₂O₃
Ti/TiN stacked layer
Ti/TiN/Ti/TiN stacked layer
Ta/TaN stacked layer
Ti/Al/TiN stacked layer
TiN/Ti/Al/TiN stacked layer
FIG. 12 are illustrating a manufacturing process of a GaN-based transistor device of another embodiment of the disclosure. [0010]
FIG. 13A is a cross section view of a GaN-based transistor device of still another embodiment of the disclosure. [0011]
barrier metal layer
Si
low temperature nitride
low temperature oxide
AlN
Al₂O₃
Ti/TiN stacked layer
Ti/TiN/Ti/TiN stacked layer
Ta/TaN stacked layer
Ti/Al/TiN stacked layer
TiN/Ti/Al/TiN stacked layer
FIG. 12 are illustrating a manufacturing process of a GaN-based transistor device of another embodiment of the disclosure. [0010]
FIG. 13A is a cross section view of a GaN-based transistor device of still another embodiment of the disclosure. [0011]