ON-CHIP DC-DC POWER CONVERTERS WITH FULLY INTEGRATED GaN POWER SWITCHES, SILICON CMOS TRANSISTORS AND MAGNETIC INDUCTORS

Hariklia Deligianni

Patent

Atlas literature

Patent

US 10,396,665

ON-CHIP DC-DC POWER CONVERTERS WITH FULLY INTEGRATED GaN POWER SWITCHES, SILICON CMOS TRANSISTORS AND MAGNETIC INDUCTORS

Hariklia Deligianni

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1. In the power converter layout shown in

FIG. 2

FIG. 2 is a cross- sectional diagram illustrating a starting platform for fabricating the present fully integrated DC-DC power converter which includes a …

FIG. 3

FIG. 3. Any suitable hardmask or softmask material patterned using standard lithography and etching techniques may be employed for mask 302. [0029] As shown in

FIG. 4

FIG. 4. For illustrative purposes only, a single GaN transistor is shown in the ﬁgures. After completion of the GaN transistor(s), the mask 302 can be removed. …

FIG. 5

FIG. 5. Any suitable hardmask or softmask material patterned using standard lithography and etching techniques may be employed for mask 502. [0035] Next, as …

FIG. 6

FIG. 6, one or more CMOS transistors are formed on the SOI layer 202 outside of the window. For ease and clarity of description, the portion(s) of the SOI …

FIG. 7

FIG. 7. To form the interconnects 704, a dielectric (s) 702 can be deposited onto the wafer, covering the CMOS and GaN transistors, patterned, and the pattern …

FIG. 8

FIG. 8. As shown in

FIG. 9

FIG. 9. As shown in

FIG. 10

FIG. 10. Suitable magnetic materials for the bottom (and top) yolk include, but are not limited to, iron (Fe)-based materials, such as iron-tantalum nitride …

FIG. 11

FIG. 11. By way of example only, a standard resist mask plating technique can be used to form the Cu wires, wherein a conventional photolithography and etching …

FIG. 12

FIG. 12 is a cross-sectional diagram illustrating the Cu wires having been covered with a hard baked photoresist, and magnetic vias having been opened to the …

FIG. 13

FIG. 13 is a cross-sectional diagram illustrating a top yolk TY of the magnetic inductor having been formed according to an embodiment of the present …

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

4 independent · 16 dependent

1
IndependentGaNSiburied insulatordielectricfully integrated on-chip DC-DC power converter
A DC-DC power converter, comprising: a silicon-on-insulator (SOI) wafer having a SO I layer separated from a substrate by a buried insulator, wherein the SOI layer and the buried insulator are selectively removed from at least one ﬁrst portion of the SOI wafer, and wherein the SOI layer and the buried insulator remain present in at least one second portion of the SOI wafer; at least one gallium nitride (GaN) transistor formed on the substrate in the at least one ﬁrst portion of the SO I wafer; at least one complementary metal-oxide semiconductor (CMOS) transistor, formed on the SO I layer in the at least one second portion of the SO I wafer, connected to a gate of the GaN transistor; a dielectric covering the GaN and CMOS transistors; at least one magnetic inductor formed on the dielectric; and metal wiring in the dielectric directly connecting a drain of the GaN transistor with the magnetic inductor. Currently amended
1. 2
  Dependent← claim 1buried insulatorfully integrated on-chip DC-DC power converter
  The DC-DC power converter of claim 1, wherein the buried insulator is an oxide. Original
2. 3
  Dependent← claim 1SiSiCsapphirefully integrated on-chip DC-DC power converter
  The DC-DC power converter of claim 1, wherein the substrate comprises a material selected from the group consisting of: silicon (111), silicon carbide, sapphire, and combinations thereof. Original
3. 4
  Dependent← claim 1GaNAlGaNfully integrated on-chip DC-DC power converter
  The DC-DC power converter of claim 1, wherein the GaN transistor comprises: a ﬁrst active material on the substrate; and a second active material on the ﬁrst active material, wherein the second active material has a higher band gap than the ﬁrst active material. Original
4. 9
  Dependent← claim 1fully integrated on-chip DC-DC power converter
  The DC-DC power converter of claim 1, wherein the magnetic inductor is a closed-yoke magnetic inductor. Original
8
Independent
. Canceled
10
IndependentGaNSiburied insulatordielectricfully integrated on-chip DC-DC power converter
A method of forming a DC-DC power converter, the method comprising: providing a SOI wafer having a SOI layer separated from a substrate by a buried insulator; selectively removing the S OI layer and the buried insulator from at least one ﬁrst portion of the SOI wafer such that the SOI layer and the buried insulator remain present in at least one second portion of the SOI wafer; forming at least one GaN transistor on the substrate in the at least one ﬁrst portion of the SOI wafer; forming at least one CMOS transistor on the SOI layer in the at least one second portion of the SOI wafer connected to a gate of the GaN transistor; depositing a dielectric that covers the GaN and CMOS transistors; forming at least one magnetic inductor on the dielectric; and forming metal wiring in the dielectric that directly connects a drain of the GaN transistor with the magnetic inductor. Currently amended
1. 11
  Dependent← claim 10
  The method of claim 10, wherein selectively removing the SOI layer and the buried insulator from the at least one ﬁrst portion of the SOI wafer comprises: forming a mask that covers only the at least one second portion of the SO I wafer; and etching the SO I wafer using the mask to selectively remove the SOI layer and the buried insulator from the at least one ﬁrst portion of the SOI wafer. Original
2. 13
  Dependent← claim 10GaNAlGaN
  The method of claim 10, further comprising: depositing a ﬁrst active material on the substrate; and depositing a second active material on the ﬁrst active material, wherein the second active material has a higher band gap than the ﬁrst active material. Original
3. 17
  Dependent← claim 10
  The method of claim 10, further comprising: forming a mask that covers the GaN transistor prior to forming the CMOS transistor. Original
4. 19
  Dependent← claim 10SiSiCsapphire
  The method of claim 10, wherein the substrate comprises a material selected from the group consisting of: silicon (111), silicon carbide, sapphire, and combinations thereof. Original
5. 20
  Dependent← claim 10
  The method of claim 10, wherein the magnetic inductor is a closed- yoke magnetic inductor. Original
18
Independent
. Canceled

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

fully integrated on-chip DC-DC power converter

dielectricinterlayer dielectric / BEOL dielectric

AlGaNGaN transistor second active layer (higher band gap)

GaNGaN transistor first active layer

SiSOI layer (CMOS active layer)

buried insulatorburied insulator (BOX)

Sisubstrate

Materials

Materials described outside the worked examples.

gallium nitride

GaN

GaN Transistor Active Channel Layer (First Active Material)

SOI layer (silicon)

SOI Layer For CMOS Transistor Formation

Process steps

Additional fabrication and treatment steps described in the patent.

Selective Etch

Step 1

Process details

steps:first RIE with Si-selective chemistry to remove SOI layer, second RIE with oxide-selective chemistry to remove buried insulator

method:reactive ion etching (RIE)

etch stop:Si substrate

Materials:

Characterization

Measurements and analyses referenced in the patent, with their drawing references.

fet electrical

Fet Electrical

FIG. 1. In the power converter layout shown in

Figure references

FIG. 1

GaNGaN

Why these are connected

Related documents with shared materials, methods, properties, or citations.

ON-CHIP DC-DC POWER CONVERTERS WITH FULLY INTEGRATED GaN POWER SWITCHES, SILICON CMOS TRANSISTORS AND MAGNETIC INDUCTORS | Matter42 Literature