Patent
US 11,289,594GAN-BASED SUPERJUNCTION VERTICAL POWER TRANSISTOR AND MANUFACTURING METHOD THEREOF
Sen HUANG
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-19 are schematic diagrams of a manufacturing process of a GaN- based superjunction vertical power transistor in accordance with some embodiments of the …
FIG. 2 is a structural schematic diagram of forming a mask layer on P-type GaN. [0025]
FIG. 3 is a structural schematic diagram of forming a gate region opening by patterning an upper surface mask layer. [0026]
FIG. 4 is a structural schematic diagram of forming a gate region window by etching the current blocking layer based on the gate region opening in FIG 3. …
FIG. 5. [0089] In this embodiment, the first dielectric layer 4 is used as the upper surface mask layer 4, and is represented by SiO 2 material, and the …
FIG. 6 is a structural schematic diagram of a conformal growth of a thin barrier AI(I n, Ga)N/GaN heterostructure on the current blocking layer. [0029]
FIG. 7 is a structural schematic diagram of removing the substrate such that the N--GaN layer is exposed to the surface when the substrate is a non-GaN …
FIG. 8 is a structural schematic diagram of depositing a second dielectric layer as a passivation layer on an upper surface of the thin barrier A I(I n, …
FIG. 9 is a structural schematic diagram of forming an etched groove by performing selective etching in the N--GaN layer by using the third dielectric layer as …
FIG. 10 is a structural schematic diagram of completely or partially filling a second P-type GaN layer in the etched groove. [0033]
FIG. 11 is a structural schematic diagram of removing the mask layer under the N--GaN layer. [0034]
FIG. 12 is a structural schematic diagram of manufacturing an N + -GaN layer under the second P-type GaN layer. [0035]
FIG. 13 is a structural schematic diagram of manufacturing a source region window by a gate trench etching technique. [0036]
FIG. 14 is a structural schematic diagram of depositing a source metal layer on the sidewalls and the bottom of the source region window and depositing a drain …
FIG. 15 is a structural schematic diagram of growing a passivation protective layer, as an isolation layer for device isolation, on the source metal layer and …
FIG. 16 is a schematic diagram of performing isolation using high energy ion injection in an active region of the device. [0039]
FIG. 17 is a structural schematic diagram of etching the isolation layer and the second dielectric layer of the gate region to an upper surface of the thin …
FIG. 18 is a structural schematic diagram of a conformal growth of a gate dielectric layer on an upper surface of the thin barrier layer A I(I n, Ga)N and an …
FIG. 19 is a structural schematic diagram of a GaN-based superjunction vertical power transistor obtained after growing a gate metal layer on the gate …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based superjunction vertical power transistor, comprising: an N--GaN layer; a first P-GaN layer, as a current blocking layer, formed on the N--GaN layer, and having a gate region window; and a thin barrier A I(I n, Ga)N/GaN heterostructure, conformally formed on the current blocking layer and filling a bottom of the g ate re g ion window as well as one or more sidewalls of the gate region window, wherein the N--GaN layer has an etched groove completely or partially filled with a second P-type GaN layer, wherein an N + -GaN layer is formed under the second P- type GaN layer, and wherein the N + -GaN layer is in direct contact with the second P-type GaN layer and the N--GaN layer to form a super j unction composite structure. Currently amended
The GaN-based super j unction vertical power transistor according to claim 1, further comprising: a source, a drain, and a gate. Original
The GaN-based super j unction vertical power transistor according to claim 1, wherein an A I (In, Ga)N barrier layer in the thin barrier A I (In, Ga)N/GaN heterostructure comprises one or more selected from: a ternary alloy comprising AIGaN or AIInN; or a quaternary alloy comprising AI I nGaN. Previously presented
The GaN-based super j unction vertical power transistor according to claim 1, wherein the second P-type GaN layer has a concentration ranging from 10 16 cm⁻³ to 10 20 cm -3. Previously presented
The GaN-based super j unction vertical power transistor according to claim 1, wherein the etched groove has a depth between a surface of the N--GaN layer and an interface between the N-- GaN layer and the first P-GaN layer, or is etched to the interface between the N--GaN layer and the first P-GaN layer. Previously presented
A manufacturing method of a GaN-based superjunction vertical power transistor, the method comprising: epitaxially growing an N--GaN layer on a substrate; epitaxially growing a first P-GaN layer on the N--GaN layer, as a current blocking layer; forming a gate region window in the current blocking layer by a gate trench etching technique; conformally growing a thin barrier A I (In, Ga)N/GaN heterostructure on the current blocking layer, the heterostructure filling a bottom of the g ate re g ion window as well as one or more sidewalls of the gate region window; forming an etched groove in the N--GaN layer; completely or partially filling the etched groove with a second P-type GaN layer; and forming an N + -GaN layer under the second P-type GaN layer, the N + -GaN layer being in direct contact with the second P-type GaN layer and the N--GaN layer to form a super j unction composite structure. Currently amended
The manufacturing method according to claim 8, wherein: the forming the etched groove comprises: depositing a first dielectric layer on an upper surface of the thin barrier AI (In, Ga)N/GaN heterostructure, as a passivation layer, and depositing a second dielectric layer on a lower surface of the N--GaN layer or the substrate when the substrate comprises [[a]] GaN; and forming an etched groove by performing selective etching in the N--GaN layer by using the second dielectric layer as a mask layer; and the manufacturing method further comprises forming a source, a drain, and a gate, and forming the source, the drain, and the gate comprises: etching the first dielectric layer and the thin barrier A I (In, Ga)N/GaN heterostructure of the source region to the first P-GaN layer by a gate trench etching technique to obtain a source region window; depositing a source metal layer on a bottom of the source re g ion window as well as one or more sidewalls of the source region window; depositing a drain metal layer under the N + -GaN layer; growing a passivation protective layer on the source metal layer and the first dielectric layer, as an isolation layer for device isolation; performing isolation using high energy ion injection in an active region of the device; etching the isolation layer and the first dielectric layer of the gate region to an upper surface of a thin barrier layer A I (In, Ga)N by a gate trench etching technique; conformally growing a gate dielectric layer on the upper surface of the thin barrier layer A I (In, Ga)N and the upper surface of the isolation layer; and growing a gate metal layer on the gate dielectric layer. Currently amended
The manufacturing method according to claim 8 [[9]], wherein the first dielectric layer and the second dielectric layer have a thickness between 10 nm and 120 nm. Currently amended
The manufacturing method according to claim 8 [[9]], wherein the etched groove has a depth between a surface of the N--GaN layer and an interface between the N--GaN layer and the first P-GaN layer, or is etched to the interface between the N--GaN layer and the first P-GaN layer. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based superjunction vertical power transistor
Materials described outside the worked examples.
N--GaN layer
GaN
thin barrier Al(In,Ga)N/GaN heterostructure
gate dielectric layer
gate metal layer
source metal layer
drain metal layer
isolation layer
SiNx
SiO₂
SiON
polarized AlN
AlN
AIGaN barrier layer
AlGaN
AIInN barrier layer
AlInN
AIInGaN barrier layer
AlInGaN
Si substrate
Si
SiC substrate
SiC
sapphire substrate
Al₂O₃
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-19 are schematic diagrams of a manufacturing process of a GaN- based superjunction vertical power transistor in accordance with some embodiments of the …
FIG. 19 is a structural schematic diagram of a GaN-based superjunction vertical power transistor obtained after growing a gate metal layer on the gate …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
second P-type GaN layer acceptor concentration range | 10000000000000000–100000000000000000000 cm⁻³ | GaN |
Al(In,Ga)N barrier layer thickness range | 0.5–5 nm | thin barrier Al(In,Ga)N/GaN heterostructure |
first and second dielectric layer thickness range | 10–120 nm | — |
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-19 are schematic diagrams of a manufacturing process of a GaN- based superjunction vertical power transistor in accordance with some embodiments of the …
FIG. 2 is a structural schematic diagram of forming a mask layer on P-type GaN. [0025]
FIG. 3 is a structural schematic diagram of forming a gate region opening by patterning an upper surface mask layer. [0026]
FIG. 4 is a structural schematic diagram of forming a gate region window by etching the current blocking layer based on the gate region opening in FIG 3. …
FIG. 5. [0089] In this embodiment, the first dielectric layer 4 is used as the upper surface mask layer 4, and is represented by SiO 2 material, and the …
FIG. 6 is a structural schematic diagram of a conformal growth of a thin barrier AI(I n, Ga)N/GaN heterostructure on the current blocking layer. [0029]
FIG. 7 is a structural schematic diagram of removing the substrate such that the N--GaN layer is exposed to the surface when the substrate is a non-GaN …
FIG. 8 is a structural schematic diagram of depositing a second dielectric layer as a passivation layer on an upper surface of the thin barrier A I(I n, …
FIG. 9 is a structural schematic diagram of forming an etched groove by performing selective etching in the N--GaN layer by using the third dielectric layer as …
FIG. 10 is a structural schematic diagram of completely or partially filling a second P-type GaN layer in the etched groove. [0033]
FIG. 11 is a structural schematic diagram of removing the mask layer under the N--GaN layer. [0034]
FIG. 12 is a structural schematic diagram of manufacturing an N + -GaN layer under the second P-type GaN layer. [0035]
FIG. 13 is a structural schematic diagram of manufacturing a source region window by a gate trench etching technique. [0036]
FIG. 14 is a structural schematic diagram of depositing a source metal layer on the sidewalls and the bottom of the source region window and depositing a drain …
FIG. 15 is a structural schematic diagram of growing a passivation protective layer, as an isolation layer for device isolation, on the source metal layer and …
FIG. 16 is a schematic diagram of performing isolation using high energy ion injection in an active region of the device. [0039]
FIG. 17 is a structural schematic diagram of etching the isolation layer and the second dielectric layer of the gate region to an upper surface of the thin …
FIG. 18 is a structural schematic diagram of a conformal growth of a gate dielectric layer on an upper surface of the thin barrier layer A I(I n, Ga)N and an …
FIG. 19 is a structural schematic diagram of a GaN-based superjunction vertical power transistor obtained after growing a gate metal layer on the gate …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based superjunction vertical power transistor, comprising: an N--GaN layer; a first P-GaN layer, as a current blocking layer, formed on the N--GaN layer, and having a gate region window; and a thin barrier A I(I n, Ga)N/GaN heterostructure, conformally formed on the current blocking layer and filling a bottom of the g ate re g ion window as well as one or more sidewalls of the gate region window, wherein the N--GaN layer has an etched groove completely or partially filled with a second P-type GaN layer, wherein an N + -GaN layer is formed under the second P- type GaN layer, and wherein the N + -GaN layer is in direct contact with the second P-type GaN layer and the N--GaN layer to form a super j unction composite structure. Currently amended
The GaN-based super j unction vertical power transistor according to claim 1, further comprising: a source, a drain, and a gate. Original
The GaN-based super j unction vertical power transistor according to claim 1, wherein an A I (In, Ga)N barrier layer in the thin barrier A I (In, Ga)N/GaN heterostructure comprises one or more selected from: a ternary alloy comprising AIGaN or AIInN; or a quaternary alloy comprising AI I nGaN. Previously presented
The GaN-based super j unction vertical power transistor according to claim 1, wherein the second P-type GaN layer has a concentration ranging from 10 16 cm⁻³ to 10 20 cm -3. Previously presented
The GaN-based super j unction vertical power transistor according to claim 1, wherein the etched groove has a depth between a surface of the N--GaN layer and an interface between the N-- GaN layer and the first P-GaN layer, or is etched to the interface between the N--GaN layer and the first P-GaN layer. Previously presented
A manufacturing method of a GaN-based superjunction vertical power transistor, the method comprising: epitaxially growing an N--GaN layer on a substrate; epitaxially growing a first P-GaN layer on the N--GaN layer, as a current blocking layer; forming a gate region window in the current blocking layer by a gate trench etching technique; conformally growing a thin barrier A I (In, Ga)N/GaN heterostructure on the current blocking layer, the heterostructure filling a bottom of the g ate re g ion window as well as one or more sidewalls of the gate region window; forming an etched groove in the N--GaN layer; completely or partially filling the etched groove with a second P-type GaN layer; and forming an N + -GaN layer under the second P-type GaN layer, the N + -GaN layer being in direct contact with the second P-type GaN layer and the N--GaN layer to form a super j unction composite structure. Currently amended
The manufacturing method according to claim 8, wherein: the forming the etched groove comprises: depositing a first dielectric layer on an upper surface of the thin barrier AI (In, Ga)N/GaN heterostructure, as a passivation layer, and depositing a second dielectric layer on a lower surface of the N--GaN layer or the substrate when the substrate comprises [[a]] GaN; and forming an etched groove by performing selective etching in the N--GaN layer by using the second dielectric layer as a mask layer; and the manufacturing method further comprises forming a source, a drain, and a gate, and forming the source, the drain, and the gate comprises: etching the first dielectric layer and the thin barrier A I (In, Ga)N/GaN heterostructure of the source region to the first P-GaN layer by a gate trench etching technique to obtain a source region window; depositing a source metal layer on a bottom of the source re g ion window as well as one or more sidewalls of the source region window; depositing a drain metal layer under the N + -GaN layer; growing a passivation protective layer on the source metal layer and the first dielectric layer, as an isolation layer for device isolation; performing isolation using high energy ion injection in an active region of the device; etching the isolation layer and the first dielectric layer of the gate region to an upper surface of a thin barrier layer A I (In, Ga)N by a gate trench etching technique; conformally growing a gate dielectric layer on the upper surface of the thin barrier layer A I (In, Ga)N and the upper surface of the isolation layer; and growing a gate metal layer on the gate dielectric layer. Currently amended
The manufacturing method according to claim 8 [[9]], wherein the first dielectric layer and the second dielectric layer have a thickness between 10 nm and 120 nm. Currently amended
The manufacturing method according to claim 8 [[9]], wherein the etched groove has a depth between a surface of the N--GaN layer and an interface between the N--GaN layer and the first P-GaN layer, or is etched to the interface between the N--GaN layer and the first P-GaN layer. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based superjunction vertical power transistor
Materials described outside the worked examples.
N--GaN layer
GaN
thin barrier Al(In,Ga)N/GaN heterostructure
gate dielectric layer
gate metal layer
source metal layer
drain metal layer
isolation layer
SiNx
SiO₂
SiON
polarized AlN
AlN
AIGaN barrier layer
AlGaN
AIInN barrier layer
AlInN
AIInGaN barrier layer
AlInGaN
Si substrate
Si
SiC substrate
SiC
sapphire substrate
Al₂O₃
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-19 are schematic diagrams of a manufacturing process of a GaN- based superjunction vertical power transistor in accordance with some embodiments of the …
FIG. 19 is a structural schematic diagram of a GaN-based superjunction vertical power transistor obtained after growing a gate metal layer on the gate …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
second P-type GaN layer acceptor concentration range | 10000000000000000–100000000000000000000 cm⁻³ | GaN |
Al(In,Ga)N barrier layer thickness range | 0.5–5 nm | thin barrier Al(In,Ga)N/GaN heterostructure |
first and second dielectric layer thickness range | 10–120 nm | — |
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-19 are schematic diagrams of a manufacturing process of a GaN- based superjunction vertical power transistor in accordance with some embodiments of the …
FIG. 2 is a structural schematic diagram of forming a mask layer on P-type GaN. [0025]
FIG. 3 is a structural schematic diagram of forming a gate region opening by patterning an upper surface mask layer. [0026]
FIG. 4 is a structural schematic diagram of forming a gate region window by etching the current blocking layer based on the gate region opening in FIG 3. …
FIG. 5. [0089] In this embodiment, the first dielectric layer 4 is used as the upper surface mask layer 4, and is represented by SiO 2 material, and the …
FIG. 6 is a structural schematic diagram of a conformal growth of a thin barrier AI(I n, Ga)N/GaN heterostructure on the current blocking layer. [0029]
FIG. 7 is a structural schematic diagram of removing the substrate such that the N--GaN layer is exposed to the surface when the substrate is a non-GaN …
FIG. 8 is a structural schematic diagram of depositing a second dielectric layer as a passivation layer on an upper surface of the thin barrier A I(I n, …
FIG. 9 is a structural schematic diagram of forming an etched groove by performing selective etching in the N--GaN layer by using the third dielectric layer as …
FIG. 10 is a structural schematic diagram of completely or partially filling a second P-type GaN layer in the etched groove. [0033]
FIG. 11 is a structural schematic diagram of removing the mask layer under the N--GaN layer. [0034]
FIG. 12 is a structural schematic diagram of manufacturing an N + -GaN layer under the second P-type GaN layer. [0035]
FIG. 13 is a structural schematic diagram of manufacturing a source region window by a gate trench etching technique. [0036]
FIG. 14 is a structural schematic diagram of depositing a source metal layer on the sidewalls and the bottom of the source region window and depositing a drain …
FIG. 15 is a structural schematic diagram of growing a passivation protective layer, as an isolation layer for device isolation, on the source metal layer and …
FIG. 16 is a schematic diagram of performing isolation using high energy ion injection in an active region of the device. [0039]
FIG. 17 is a structural schematic diagram of etching the isolation layer and the second dielectric layer of the gate region to an upper surface of the thin …
FIG. 18 is a structural schematic diagram of a conformal growth of a gate dielectric layer on an upper surface of the thin barrier layer A I(I n, Ga)N and an …
FIG. 19 is a structural schematic diagram of a GaN-based superjunction vertical power transistor obtained after growing a gate metal layer on the gate …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based superjunction vertical power transistor, comprising: an N--GaN layer; a first P-GaN layer, as a current blocking layer, formed on the N--GaN layer, and having a gate region window; and a thin barrier A I(I n, Ga)N/GaN heterostructure, conformally formed on the current blocking layer and filling a bottom of the g ate re g ion window as well as one or more sidewalls of the gate region window, wherein the N--GaN layer has an etched groove completely or partially filled with a second P-type GaN layer, wherein an N + -GaN layer is formed under the second P- type GaN layer, and wherein the N + -GaN layer is in direct contact with the second P-type GaN layer and the N--GaN layer to form a super j unction composite structure. Currently amended
The GaN-based super j unction vertical power transistor according to claim 1, further comprising: a source, a drain, and a gate. Original
The GaN-based super j unction vertical power transistor according to claim 1, wherein an A I (In, Ga)N barrier layer in the thin barrier A I (In, Ga)N/GaN heterostructure comprises one or more selected from: a ternary alloy comprising AIGaN or AIInN; or a quaternary alloy comprising AI I nGaN. Previously presented
The GaN-based super j unction vertical power transistor according to claim 1, wherein the second P-type GaN layer has a concentration ranging from 10 16 cm⁻³ to 10 20 cm -3. Previously presented
The GaN-based super j unction vertical power transistor according to claim 1, wherein the etched groove has a depth between a surface of the N--GaN layer and an interface between the N-- GaN layer and the first P-GaN layer, or is etched to the interface between the N--GaN layer and the first P-GaN layer. Previously presented
A manufacturing method of a GaN-based superjunction vertical power transistor, the method comprising: epitaxially growing an N--GaN layer on a substrate; epitaxially growing a first P-GaN layer on the N--GaN layer, as a current blocking layer; forming a gate region window in the current blocking layer by a gate trench etching technique; conformally growing a thin barrier A I (In, Ga)N/GaN heterostructure on the current blocking layer, the heterostructure filling a bottom of the g ate re g ion window as well as one or more sidewalls of the gate region window; forming an etched groove in the N--GaN layer; completely or partially filling the etched groove with a second P-type GaN layer; and forming an N + -GaN layer under the second P-type GaN layer, the N + -GaN layer being in direct contact with the second P-type GaN layer and the N--GaN layer to form a super j unction composite structure. Currently amended
The manufacturing method according to claim 8, wherein: the forming the etched groove comprises: depositing a first dielectric layer on an upper surface of the thin barrier AI (In, Ga)N/GaN heterostructure, as a passivation layer, and depositing a second dielectric layer on a lower surface of the N--GaN layer or the substrate when the substrate comprises [[a]] GaN; and forming an etched groove by performing selective etching in the N--GaN layer by using the second dielectric layer as a mask layer; and the manufacturing method further comprises forming a source, a drain, and a gate, and forming the source, the drain, and the gate comprises: etching the first dielectric layer and the thin barrier A I (In, Ga)N/GaN heterostructure of the source region to the first P-GaN layer by a gate trench etching technique to obtain a source region window; depositing a source metal layer on a bottom of the source re g ion window as well as one or more sidewalls of the source region window; depositing a drain metal layer under the N + -GaN layer; growing a passivation protective layer on the source metal layer and the first dielectric layer, as an isolation layer for device isolation; performing isolation using high energy ion injection in an active region of the device; etching the isolation layer and the first dielectric layer of the gate region to an upper surface of a thin barrier layer A I (In, Ga)N by a gate trench etching technique; conformally growing a gate dielectric layer on the upper surface of the thin barrier layer A I (In, Ga)N and the upper surface of the isolation layer; and growing a gate metal layer on the gate dielectric layer. Currently amended
The manufacturing method according to claim 8 [[9]], wherein the first dielectric layer and the second dielectric layer have a thickness between 10 nm and 120 nm. Currently amended
The manufacturing method according to claim 8 [[9]], wherein the etched groove has a depth between a surface of the N--GaN layer and an interface between the N--GaN layer and the first P-GaN layer, or is etched to the interface between the N--GaN layer and the first P-GaN layer. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based superjunction vertical power transistor
Materials described outside the worked examples.
N--GaN layer
GaN
thin barrier Al(In,Ga)N/GaN heterostructure
gate dielectric layer
gate metal layer
source metal layer
drain metal layer
isolation layer
SiNx
SiO₂
SiON
polarized AlN
AlN
AIGaN barrier layer
AlGaN
AIInN barrier layer
AlInN
AIInGaN barrier layer
AlInGaN
Si substrate
Si
SiC substrate
SiC
sapphire substrate
Al₂O₃
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-19 are schematic diagrams of a manufacturing process of a GaN- based superjunction vertical power transistor in accordance with some embodiments of the …
FIG. 19 is a structural schematic diagram of a GaN-based superjunction vertical power transistor obtained after growing a gate metal layer on the gate …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
second P-type GaN layer acceptor concentration range | 10000000000000000–100000000000000000000 cm⁻³ | GaN |
Al(In,Ga)N barrier layer thickness range | 0.5–5 nm | thin barrier Al(In,Ga)N/GaN heterostructure |
first and second dielectric layer thickness range | 10–120 nm | — |
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-19 are schematic diagrams of a manufacturing process of a GaN- based superjunction vertical power transistor in accordance with some embodiments of the …
FIG. 2 is a structural schematic diagram of forming a mask layer on P-type GaN. [0025]
FIG. 3 is a structural schematic diagram of forming a gate region opening by patterning an upper surface mask layer. [0026]
FIG. 4 is a structural schematic diagram of forming a gate region window by etching the current blocking layer based on the gate region opening in FIG 3. …
FIG. 5. [0089] In this embodiment, the first dielectric layer 4 is used as the upper surface mask layer 4, and is represented by SiO 2 material, and the …
FIG. 6 is a structural schematic diagram of a conformal growth of a thin barrier AI(I n, Ga)N/GaN heterostructure on the current blocking layer. [0029]
FIG. 7 is a structural schematic diagram of removing the substrate such that the N--GaN layer is exposed to the surface when the substrate is a non-GaN …
FIG. 8 is a structural schematic diagram of depositing a second dielectric layer as a passivation layer on an upper surface of the thin barrier A I(I n, …
FIG. 9 is a structural schematic diagram of forming an etched groove by performing selective etching in the N--GaN layer by using the third dielectric layer as …
FIG. 10 is a structural schematic diagram of completely or partially filling a second P-type GaN layer in the etched groove. [0033]
FIG. 11 is a structural schematic diagram of removing the mask layer under the N--GaN layer. [0034]
FIG. 12 is a structural schematic diagram of manufacturing an N + -GaN layer under the second P-type GaN layer. [0035]
FIG. 13 is a structural schematic diagram of manufacturing a source region window by a gate trench etching technique. [0036]
FIG. 14 is a structural schematic diagram of depositing a source metal layer on the sidewalls and the bottom of the source region window and depositing a drain …
FIG. 15 is a structural schematic diagram of growing a passivation protective layer, as an isolation layer for device isolation, on the source metal layer and …
FIG. 16 is a schematic diagram of performing isolation using high energy ion injection in an active region of the device. [0039]
FIG. 17 is a structural schematic diagram of etching the isolation layer and the second dielectric layer of the gate region to an upper surface of the thin …
FIG. 18 is a structural schematic diagram of a conformal growth of a gate dielectric layer on an upper surface of the thin barrier layer A I(I n, Ga)N and an …
FIG. 19 is a structural schematic diagram of a GaN-based superjunction vertical power transistor obtained after growing a gate metal layer on the gate …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based superjunction vertical power transistor, comprising: an N--GaN layer; a first P-GaN layer, as a current blocking layer, formed on the N--GaN layer, and having a gate region window; and a thin barrier A I(I n, Ga)N/GaN heterostructure, conformally formed on the current blocking layer and filling a bottom of the g ate re g ion window as well as one or more sidewalls of the gate region window, wherein the N--GaN layer has an etched groove completely or partially filled with a second P-type GaN layer, wherein an N + -GaN layer is formed under the second P- type GaN layer, and wherein the N + -GaN layer is in direct contact with the second P-type GaN layer and the N--GaN layer to form a super j unction composite structure. Currently amended
The GaN-based super j unction vertical power transistor according to claim 1, further comprising: a source, a drain, and a gate. Original
The GaN-based super j unction vertical power transistor according to claim 1, wherein an A I (In, Ga)N barrier layer in the thin barrier A I (In, Ga)N/GaN heterostructure comprises one or more selected from: a ternary alloy comprising AIGaN or AIInN; or a quaternary alloy comprising AI I nGaN. Previously presented
The GaN-based super j unction vertical power transistor according to claim 1, wherein the second P-type GaN layer has a concentration ranging from 10 16 cm⁻³ to 10 20 cm -3. Previously presented
The GaN-based super j unction vertical power transistor according to claim 1, wherein the etched groove has a depth between a surface of the N--GaN layer and an interface between the N-- GaN layer and the first P-GaN layer, or is etched to the interface between the N--GaN layer and the first P-GaN layer. Previously presented
A manufacturing method of a GaN-based superjunction vertical power transistor, the method comprising: epitaxially growing an N--GaN layer on a substrate; epitaxially growing a first P-GaN layer on the N--GaN layer, as a current blocking layer; forming a gate region window in the current blocking layer by a gate trench etching technique; conformally growing a thin barrier A I (In, Ga)N/GaN heterostructure on the current blocking layer, the heterostructure filling a bottom of the g ate re g ion window as well as one or more sidewalls of the gate region window; forming an etched groove in the N--GaN layer; completely or partially filling the etched groove with a second P-type GaN layer; and forming an N + -GaN layer under the second P-type GaN layer, the N + -GaN layer being in direct contact with the second P-type GaN layer and the N--GaN layer to form a super j unction composite structure. Currently amended
The manufacturing method according to claim 8, wherein: the forming the etched groove comprises: depositing a first dielectric layer on an upper surface of the thin barrier AI (In, Ga)N/GaN heterostructure, as a passivation layer, and depositing a second dielectric layer on a lower surface of the N--GaN layer or the substrate when the substrate comprises [[a]] GaN; and forming an etched groove by performing selective etching in the N--GaN layer by using the second dielectric layer as a mask layer; and the manufacturing method further comprises forming a source, a drain, and a gate, and forming the source, the drain, and the gate comprises: etching the first dielectric layer and the thin barrier A I (In, Ga)N/GaN heterostructure of the source region to the first P-GaN layer by a gate trench etching technique to obtain a source region window; depositing a source metal layer on a bottom of the source re g ion window as well as one or more sidewalls of the source region window; depositing a drain metal layer under the N + -GaN layer; growing a passivation protective layer on the source metal layer and the first dielectric layer, as an isolation layer for device isolation; performing isolation using high energy ion injection in an active region of the device; etching the isolation layer and the first dielectric layer of the gate region to an upper surface of a thin barrier layer A I (In, Ga)N by a gate trench etching technique; conformally growing a gate dielectric layer on the upper surface of the thin barrier layer A I (In, Ga)N and the upper surface of the isolation layer; and growing a gate metal layer on the gate dielectric layer. Currently amended
The manufacturing method according to claim 8 [[9]], wherein the first dielectric layer and the second dielectric layer have a thickness between 10 nm and 120 nm. Currently amended
The manufacturing method according to claim 8 [[9]], wherein the etched groove has a depth between a surface of the N--GaN layer and an interface between the N--GaN layer and the first P-GaN layer, or is etched to the interface between the N--GaN layer and the first P-GaN layer. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based superjunction vertical power transistor
Materials described outside the worked examples.
N--GaN layer
GaN
thin barrier Al(In,Ga)N/GaN heterostructure
gate dielectric layer
gate metal layer
source metal layer
drain metal layer
isolation layer
SiNx
SiO₂
SiON
polarized AlN
AlN
AIGaN barrier layer
AlGaN
AIInN barrier layer
AlInN
AIInGaN barrier layer
AlInGaN
Si substrate
Si
SiC substrate
SiC
sapphire substrate
Al₂O₃
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-19 are schematic diagrams of a manufacturing process of a GaN- based superjunction vertical power transistor in accordance with some embodiments of the …
FIG. 19 is a structural schematic diagram of a GaN-based superjunction vertical power transistor obtained after growing a gate metal layer on the gate …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
second P-type GaN layer acceptor concentration range | 10000000000000000–100000000000000000000 cm⁻³ | GaN |
Al(In,Ga)N barrier layer thickness range | 0.5–5 nm | thin barrier Al(In,Ga)N/GaN heterostructure |
first and second dielectric layer thickness range | 10–120 nm | — |
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