Patent
US 9,269,784Gallium Arsenide Based Device Having Non-Gold Ohmic Contacts
Yuefei Yang
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,269,784Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a semiconductor device, in accordance with some embodiments. [0045]
FIG. 2 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0046]
FIG. 3 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0047]
FIG. 4A is a schematic cross-sectional view of a monolithically integrated semiconductor device, in accordance with some embodiments. [0048]
FIG. 5 is a schematic cross-sectional view of a monolithically integrated semiconductor device, in accordance with some embodiments. [0050]
FIG. 6A illustrates a schematic diagram of a top view of a circuit disposed on a semiconductor die, in accordance with some embodiments. [0051]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a semiconductor die that includes: a plurality of semiconductor layers disposed on a GaAs substrate, including a first semiconductor layer having a first band-gap and a second semiconductor layer having a second band-gap; a contact layer disposed epitaxially upon the first semiconductor layer, wherein: the contact layer has a thickness that is less than a critical thickness, wherein the critical thickness is a thickness below which the contact layer remains epitaxial with the first semiconductor layer; the second semiconductor layer is epitaxially disposed upon the contact layer; and the contact layer has a third band-gap that is less than the first band- gap and the second band-gap; and a conductive layer disposed upon the contact layer to form an ohmic contact, wherein the conductive layer comprises one or more metal layers compatible with silicon processing techniques.
The device of claim 19, wherein the conductive layer does not comprise gold.
The device of claim 19, further comprising metal interconnections between circuit components of a circuit disposed on the GaAs substrate of the semiconductor die.
The device of claim 3, wherein the metal interconnections comprise aluminum-based metal interconnections or copper-based metal interconnections.
The device of claim 3 [[19]], further comprising: a flip chip module mechanically and electrically coupled to the semiconductor die, the flip chip module including a ground plane that, together with the metal interconnections, forms one or more transmission lines, and a plurality of metal connectors mechanically and 20762-5002-US 3 electrically coupled to a plurality of metal contacts of the circuit disposed on the GaAs substrate of the semiconductor die; wherein the plurality of metal contacts includes a metal contact electrically coupled to the ohmic contact.
canceled
(Withdrawn, Previously Presented) The device of claim 19, wherein the device further comprises a field effect transistor (FET), having a gate, source, and drain; the FET further including: first and second distinct instances of the contact layer, the first instance of the contact layer comprising the source and the second instance of the contact layer comprising the drain; and first and second distinct instances of the conductive layer, the first instance of the conductive layer disposed upon the first instance of contact layer to form an ohmic source contact, the second instance of the conductive layer disposed upon the second instance of the contact layer to form an ohmic drain contact. withdrawn
The device of claim 8, wherein the FET is a metal semiconductor field effect transistor (MESFET). withdrawn
The device of claim 8, wherein the FET is a high electron-mobility transistor (HEMT). withdrawn
The device of claim 8, further comprising one or more additional active circuit components monolithically integrated onto the semiconductor die, wherein the device is a monolithically integrated circuit. withdrawn
62-5002-US 4
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor die with non-gold ohmic contact on GaAs substrate
Materials described outside the worked examples.
GaAs substrate
GaAs
contact layer (InxGa₁-xAs, InxGa₁-xSb, or Ge)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0046]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,269,784Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a semiconductor device, in accordance with some embodiments. [0045]
FIG. 2 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0046]
FIG. 3 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0047]
FIG. 4A is a schematic cross-sectional view of a monolithically integrated semiconductor device, in accordance with some embodiments. [0048]
FIG. 5 is a schematic cross-sectional view of a monolithically integrated semiconductor device, in accordance with some embodiments. [0050]
FIG. 6A illustrates a schematic diagram of a top view of a circuit disposed on a semiconductor die, in accordance with some embodiments. [0051]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a semiconductor die that includes: a plurality of semiconductor layers disposed on a GaAs substrate, including a first semiconductor layer having a first band-gap and a second semiconductor layer having a second band-gap; a contact layer disposed epitaxially upon the first semiconductor layer, wherein: the contact layer has a thickness that is less than a critical thickness, wherein the critical thickness is a thickness below which the contact layer remains epitaxial with the first semiconductor layer; the second semiconductor layer is epitaxially disposed upon the contact layer; and the contact layer has a third band-gap that is less than the first band- gap and the second band-gap; and a conductive layer disposed upon the contact layer to form an ohmic contact, wherein the conductive layer comprises one or more metal layers compatible with silicon processing techniques.
The device of claim 19, wherein the conductive layer does not comprise gold.
The device of claim 19, further comprising metal interconnections between circuit components of a circuit disposed on the GaAs substrate of the semiconductor die.
The device of claim 3, wherein the metal interconnections comprise aluminum-based metal interconnections or copper-based metal interconnections.
The device of claim 3 [[19]], further comprising: a flip chip module mechanically and electrically coupled to the semiconductor die, the flip chip module including a ground plane that, together with the metal interconnections, forms one or more transmission lines, and a plurality of metal connectors mechanically and 20762-5002-US 3 electrically coupled to a plurality of metal contacts of the circuit disposed on the GaAs substrate of the semiconductor die; wherein the plurality of metal contacts includes a metal contact electrically coupled to the ohmic contact.
canceled
(Withdrawn, Previously Presented) The device of claim 19, wherein the device further comprises a field effect transistor (FET), having a gate, source, and drain; the FET further including: first and second distinct instances of the contact layer, the first instance of the contact layer comprising the source and the second instance of the contact layer comprising the drain; and first and second distinct instances of the conductive layer, the first instance of the conductive layer disposed upon the first instance of contact layer to form an ohmic source contact, the second instance of the conductive layer disposed upon the second instance of the contact layer to form an ohmic drain contact. withdrawn
The device of claim 8, wherein the FET is a metal semiconductor field effect transistor (MESFET). withdrawn
The device of claim 8, wherein the FET is a high electron-mobility transistor (HEMT). withdrawn
The device of claim 8, further comprising one or more additional active circuit components monolithically integrated onto the semiconductor die, wherein the device is a monolithically integrated circuit. withdrawn
62-5002-US 4
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor die with non-gold ohmic contact on GaAs substrate
Materials described outside the worked examples.
GaAs substrate
GaAs
contact layer (InxGa₁-xAs, InxGa₁-xSb, or Ge)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0046]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,269,784Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a semiconductor device, in accordance with some embodiments. [0045]
FIG. 2 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0046]
FIG. 3 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0047]
FIG. 4A is a schematic cross-sectional view of a monolithically integrated semiconductor device, in accordance with some embodiments. [0048]
FIG. 5 is a schematic cross-sectional view of a monolithically integrated semiconductor device, in accordance with some embodiments. [0050]
FIG. 6A illustrates a schematic diagram of a top view of a circuit disposed on a semiconductor die, in accordance with some embodiments. [0051]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a semiconductor die that includes: a plurality of semiconductor layers disposed on a GaAs substrate, including a first semiconductor layer having a first band-gap and a second semiconductor layer having a second band-gap; a contact layer disposed epitaxially upon the first semiconductor layer, wherein: the contact layer has a thickness that is less than a critical thickness, wherein the critical thickness is a thickness below which the contact layer remains epitaxial with the first semiconductor layer; the second semiconductor layer is epitaxially disposed upon the contact layer; and the contact layer has a third band-gap that is less than the first band- gap and the second band-gap; and a conductive layer disposed upon the contact layer to form an ohmic contact, wherein the conductive layer comprises one or more metal layers compatible with silicon processing techniques.
The device of claim 19, wherein the conductive layer does not comprise gold.
The device of claim 19, further comprising metal interconnections between circuit components of a circuit disposed on the GaAs substrate of the semiconductor die.
The device of claim 3, wherein the metal interconnections comprise aluminum-based metal interconnections or copper-based metal interconnections.
The device of claim 3 [[19]], further comprising: a flip chip module mechanically and electrically coupled to the semiconductor die, the flip chip module including a ground plane that, together with the metal interconnections, forms one or more transmission lines, and a plurality of metal connectors mechanically and 20762-5002-US 3 electrically coupled to a plurality of metal contacts of the circuit disposed on the GaAs substrate of the semiconductor die; wherein the plurality of metal contacts includes a metal contact electrically coupled to the ohmic contact.
canceled
(Withdrawn, Previously Presented) The device of claim 19, wherein the device further comprises a field effect transistor (FET), having a gate, source, and drain; the FET further including: first and second distinct instances of the contact layer, the first instance of the contact layer comprising the source and the second instance of the contact layer comprising the drain; and first and second distinct instances of the conductive layer, the first instance of the conductive layer disposed upon the first instance of contact layer to form an ohmic source contact, the second instance of the conductive layer disposed upon the second instance of the contact layer to form an ohmic drain contact. withdrawn
The device of claim 8, wherein the FET is a metal semiconductor field effect transistor (MESFET). withdrawn
The device of claim 8, wherein the FET is a high electron-mobility transistor (HEMT). withdrawn
The device of claim 8, further comprising one or more additional active circuit components monolithically integrated onto the semiconductor die, wherein the device is a monolithically integrated circuit. withdrawn
62-5002-US 4
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor die with non-gold ohmic contact on GaAs substrate
Materials described outside the worked examples.
GaAs substrate
GaAs
contact layer (InxGa₁-xAs, InxGa₁-xSb, or Ge)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0046]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,269,784Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a semiconductor device, in accordance with some embodiments. [0045]
FIG. 2 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0046]
FIG. 3 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0047]
FIG. 4A is a schematic cross-sectional view of a monolithically integrated semiconductor device, in accordance with some embodiments. [0048]
FIG. 5 is a schematic cross-sectional view of a monolithically integrated semiconductor device, in accordance with some embodiments. [0050]
FIG. 6A illustrates a schematic diagram of a top view of a circuit disposed on a semiconductor die, in accordance with some embodiments. [0051]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a semiconductor die that includes: a plurality of semiconductor layers disposed on a GaAs substrate, including a first semiconductor layer having a first band-gap and a second semiconductor layer having a second band-gap; a contact layer disposed epitaxially upon the first semiconductor layer, wherein: the contact layer has a thickness that is less than a critical thickness, wherein the critical thickness is a thickness below which the contact layer remains epitaxial with the first semiconductor layer; the second semiconductor layer is epitaxially disposed upon the contact layer; and the contact layer has a third band-gap that is less than the first band- gap and the second band-gap; and a conductive layer disposed upon the contact layer to form an ohmic contact, wherein the conductive layer comprises one or more metal layers compatible with silicon processing techniques.
The device of claim 19, wherein the conductive layer does not comprise gold.
The device of claim 19, further comprising metal interconnections between circuit components of a circuit disposed on the GaAs substrate of the semiconductor die.
The device of claim 3, wherein the metal interconnections comprise aluminum-based metal interconnections or copper-based metal interconnections.
The device of claim 3 [[19]], further comprising: a flip chip module mechanically and electrically coupled to the semiconductor die, the flip chip module including a ground plane that, together with the metal interconnections, forms one or more transmission lines, and a plurality of metal connectors mechanically and 20762-5002-US 3 electrically coupled to a plurality of metal contacts of the circuit disposed on the GaAs substrate of the semiconductor die; wherein the plurality of metal contacts includes a metal contact electrically coupled to the ohmic contact.
canceled
(Withdrawn, Previously Presented) The device of claim 19, wherein the device further comprises a field effect transistor (FET), having a gate, source, and drain; the FET further including: first and second distinct instances of the contact layer, the first instance of the contact layer comprising the source and the second instance of the contact layer comprising the drain; and first and second distinct instances of the conductive layer, the first instance of the conductive layer disposed upon the first instance of contact layer to form an ohmic source contact, the second instance of the conductive layer disposed upon the second instance of the contact layer to form an ohmic drain contact. withdrawn
The device of claim 8, wherein the FET is a metal semiconductor field effect transistor (MESFET). withdrawn
The device of claim 8, wherein the FET is a high electron-mobility transistor (HEMT). withdrawn
The device of claim 8, further comprising one or more additional active circuit components monolithically integrated onto the semiconductor die, wherein the device is a monolithically integrated circuit. withdrawn
62-5002-US 4
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor die with non-gold ohmic contact on GaAs substrate
Materials described outside the worked examples.
GaAs substrate
GaAs
contact layer (InxGa₁-xAs, InxGa₁-xSb, or Ge)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0046]
Related documents with shared materials, methods, properties, or citations.
No layer stack recorded.
field effect transistor (FET/MESFET) on GaAs with non-gold ohmic source/drain contacts
high electron-mobility transistor (HEMT/pHEMT) on GaAs with non-gold ohmic contacts
heterojunction bipolar transistor (HBT) on GaAs with non-gold ohmic collector contact
InxGa₁-xAs contact layer
InxGa₁-xAs
InxGa₁-xSb contact layer
InxGa₁-xSb
Ge contact layer
Ge
non-gold ohmic contact metal layers
conductive layer metals (Ti, Al, Ni, W, Ge, Pd, Pt, Cu, combinations and alloys)
aluminum-based metal interconnections
copper-based metal interconnections
dielectric filler
FIG. 3 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0047]
PSEUDOMORPHIC INGAAS ON GAAS FOR GATE-ALL-AROUND TRANSISTORS
No layer stack recorded.
field effect transistor (FET/MESFET) on GaAs with non-gold ohmic source/drain contacts
high electron-mobility transistor (HEMT/pHEMT) on GaAs with non-gold ohmic contacts
heterojunction bipolar transistor (HBT) on GaAs with non-gold ohmic collector contact
InxGa₁-xAs contact layer
InxGa₁-xAs
InxGa₁-xSb contact layer
InxGa₁-xSb
Ge contact layer
Ge
non-gold ohmic contact metal layers
conductive layer metals (Ti, Al, Ni, W, Ge, Pd, Pt, Cu, combinations and alloys)
aluminum-based metal interconnections
copper-based metal interconnections
dielectric filler
FIG. 3 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0047]
PSEUDOMORPHIC INGAAS ON GAAS FOR GATE-ALL-AROUND TRANSISTORS
No layer stack recorded.
field effect transistor (FET/MESFET) on GaAs with non-gold ohmic source/drain contacts
high electron-mobility transistor (HEMT/pHEMT) on GaAs with non-gold ohmic contacts
heterojunction bipolar transistor (HBT) on GaAs with non-gold ohmic collector contact
InxGa₁-xAs contact layer
InxGa₁-xAs
InxGa₁-xSb contact layer
InxGa₁-xSb
Ge contact layer
Ge
non-gold ohmic contact metal layers
conductive layer metals (Ti, Al, Ni, W, Ge, Pd, Pt, Cu, combinations and alloys)
aluminum-based metal interconnections
copper-based metal interconnections
dielectric filler
FIG. 3 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0047]
PSEUDOMORPHIC INGAAS ON GAAS FOR GATE-ALL-AROUND TRANSISTORS
No layer stack recorded.
field effect transistor (FET/MESFET) on GaAs with non-gold ohmic source/drain contacts
high electron-mobility transistor (HEMT/pHEMT) on GaAs with non-gold ohmic contacts
heterojunction bipolar transistor (HBT) on GaAs with non-gold ohmic collector contact
InxGa₁-xAs contact layer
InxGa₁-xAs
InxGa₁-xSb contact layer
InxGa₁-xSb
Ge contact layer
Ge
non-gold ohmic contact metal layers
conductive layer metals (Ti, Al, Ni, W, Ge, Pd, Pt, Cu, combinations and alloys)
aluminum-based metal interconnections
copper-based metal interconnections
dielectric filler
FIG. 3 is a schematic cross-sectional view of a heterojunction bipolar transistor, in accordance with some embodiments. [0047]