Patent
US 8,217,424SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Yasuyuki YOSHINAGA
US
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US 8,217,424Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross sectional view of a semiconductor device for explaining a pr o blem related 25 to the present invention;
FIG. 2B is an explanatory diagram of the semiconductor device for explaining a problem related to the present invention; 5 FI.G, 3A is a cross sectional view …
FIG. 3A is a cross sectional view of a semiconductor device according to the first embodiment. 25 The semiconductor device is a depletion-type field effect …
FIG. 4 is a cross sectional view of a semiconductor device according to the second embodiment. The semiconductor device is an enhancement-type field effect …
FIG. 5 is a cross sectional view of a semiconductor device according to the third embodiment. The semiconductor device includes a depletion-type field effect …
FIG. 6B. In the present embodiment, a p-type impurity is doped to ma k e an underlying GaAs layer as a p-type semiconductor. As a 10 result, a conduction band …
FIG. 7A, the corresponding GaAs layer 2 4 is delta doped with a p-type impurity on the side of the InGa P layer 10. The present embodiment will be described …
FIG. 8, an 5 embedded-type gate in any one of the first, second, third, fourth, or fifth embodiment are made as a gate electrode 25 of an enhancement-type FET …
FIG. 9 is a cross sectional view of a semiconductor device according to the seventh 10 embodiment;
FIG. 10, a c hannel layer in any one of the first, second, third, fourth, fifth, sixth or seventh embodiment is made as. 25 an n-InGaAs layer 2 8, and an …
FIG. 11 shows a structure of the ninth 5 emb o diment in which a field-effect transistor in any one of the first, second, third, fourth, fifth, sixth or seventh …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a channel layer configured to flow a current; a gate electrode formed to control the current; and a two-layer structure in which an InGaP layer and a p- type GaAs layer being doped to be a p-type are contacted to one another, which is arranged on the channel layer in the same side to the gate electrode such that the p-type GaAs layer separates the channel layer from the InGaP layer.
The semiconductor device according to claim 1, wherein the two-layer structure is arranged between the channel layer and the gate electrode.
The semiconductor device according to claim 1, wherein the gate electrode is contacted with a recess formed in a part of the two-layer structure.
A semiconductor device in which a plural kinds of semiconductor devices are stacked on a single substrate, 2 Docket No. 8022-1229 Appln. No. 12/549,023 wherein a first kind semiconductor device among the plural kinds of semiconductor devices is the semiconductor device according to claim 1 and the two-layer structure is formed between the channel layer and the gate electrode, and a second kind semiconductor device among the plural kinds of semiconductor devices is a semiconductor device having another gate electrode being contacted with a recess formed in a part of the two-layer structure.
The semiconductor device according to claim 1, wherein the InGaP layer is an order type.
The semiconductor device according to claim 1, wherein the InGaP layer is a disorder type.
The semiconductor device according to claim 1, wherein the p-type GaAs layer is p-type doped evenly.
The semiconductor device according to 3 Docket No. 8022-1229 Appln. No. 12/549,023 claim 1, wherein the p-type GaAs layer is p-type delta doped.
The semiconductor device according to claim 1, wherein the channel layer is an undoped InGaAs layer, and the semiconductor device further comprises: an n-type doped A l GaAs layer on an one side or on both sides of the channel layer and configured to be a layer supplying electrons.
The semiconductor device according to claim GaAs layer.
The semiconductor device according to claim InGaAs layer, and the semiconductor device further an one side or on both sides of the channel layer
The semiconductor device according to claim whose anode is the gate electrode.
The semiconductor device according to claim
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with InGaP/p-type GaAs two-layer structure
enhancement-type FET with recess gate
Materials described outside the worked examples.
InGaP layer
InGaP
p-type GaAs layer
GaAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A is a cross sectional view of a semiconductor device according to the first embodiment. 25 The semiconductor device is a depletion-type field effect …
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US 8,217,424Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross sectional view of a semiconductor device for explaining a pr o blem related 25 to the present invention;
FIG. 2B is an explanatory diagram of the semiconductor device for explaining a problem related to the present invention; 5 FI.G, 3A is a cross sectional view …
FIG. 3A is a cross sectional view of a semiconductor device according to the first embodiment. 25 The semiconductor device is a depletion-type field effect …
FIG. 4 is a cross sectional view of a semiconductor device according to the second embodiment. The semiconductor device is an enhancement-type field effect …
FIG. 5 is a cross sectional view of a semiconductor device according to the third embodiment. The semiconductor device includes a depletion-type field effect …
FIG. 6B. In the present embodiment, a p-type impurity is doped to ma k e an underlying GaAs layer as a p-type semiconductor. As a 10 result, a conduction band …
FIG. 7A, the corresponding GaAs layer 2 4 is delta doped with a p-type impurity on the side of the InGa P layer 10. The present embodiment will be described …
FIG. 8, an 5 embedded-type gate in any one of the first, second, third, fourth, or fifth embodiment are made as a gate electrode 25 of an enhancement-type FET …
FIG. 9 is a cross sectional view of a semiconductor device according to the seventh 10 embodiment;
FIG. 10, a c hannel layer in any one of the first, second, third, fourth, fifth, sixth or seventh embodiment is made as. 25 an n-InGaAs layer 2 8, and an …
FIG. 11 shows a structure of the ninth 5 emb o diment in which a field-effect transistor in any one of the first, second, third, fourth, fifth, sixth or seventh …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a channel layer configured to flow a current; a gate electrode formed to control the current; and a two-layer structure in which an InGaP layer and a p- type GaAs layer being doped to be a p-type are contacted to one another, which is arranged on the channel layer in the same side to the gate electrode such that the p-type GaAs layer separates the channel layer from the InGaP layer.
The semiconductor device according to claim 1, wherein the two-layer structure is arranged between the channel layer and the gate electrode.
The semiconductor device according to claim 1, wherein the gate electrode is contacted with a recess formed in a part of the two-layer structure.
A semiconductor device in which a plural kinds of semiconductor devices are stacked on a single substrate, 2 Docket No. 8022-1229 Appln. No. 12/549,023 wherein a first kind semiconductor device among the plural kinds of semiconductor devices is the semiconductor device according to claim 1 and the two-layer structure is formed between the channel layer and the gate electrode, and a second kind semiconductor device among the plural kinds of semiconductor devices is a semiconductor device having another gate electrode being contacted with a recess formed in a part of the two-layer structure.
The semiconductor device according to claim 1, wherein the InGaP layer is an order type.
The semiconductor device according to claim 1, wherein the InGaP layer is a disorder type.
The semiconductor device according to claim 1, wherein the p-type GaAs layer is p-type doped evenly.
The semiconductor device according to 3 Docket No. 8022-1229 Appln. No. 12/549,023 claim 1, wherein the p-type GaAs layer is p-type delta doped.
The semiconductor device according to claim 1, wherein the channel layer is an undoped InGaAs layer, and the semiconductor device further comprises: an n-type doped A l GaAs layer on an one side or on both sides of the channel layer and configured to be a layer supplying electrons.
The semiconductor device according to claim GaAs layer.
The semiconductor device according to claim InGaAs layer, and the semiconductor device further an one side or on both sides of the channel layer
The semiconductor device according to claim whose anode is the gate electrode.
The semiconductor device according to claim
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with InGaP/p-type GaAs two-layer structure
enhancement-type FET with recess gate
Materials described outside the worked examples.
InGaP layer
InGaP
p-type GaAs layer
GaAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A is a cross sectional view of a semiconductor device according to the first embodiment. 25 The semiconductor device is a depletion-type field effect …
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Patent
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US 8,217,424Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross sectional view of a semiconductor device for explaining a pr o blem related 25 to the present invention;
FIG. 2B is an explanatory diagram of the semiconductor device for explaining a problem related to the present invention; 5 FI.G, 3A is a cross sectional view …
FIG. 3A is a cross sectional view of a semiconductor device according to the first embodiment. 25 The semiconductor device is a depletion-type field effect …
FIG. 4 is a cross sectional view of a semiconductor device according to the second embodiment. The semiconductor device is an enhancement-type field effect …
FIG. 5 is a cross sectional view of a semiconductor device according to the third embodiment. The semiconductor device includes a depletion-type field effect …
FIG. 6B. In the present embodiment, a p-type impurity is doped to ma k e an underlying GaAs layer as a p-type semiconductor. As a 10 result, a conduction band …
FIG. 7A, the corresponding GaAs layer 2 4 is delta doped with a p-type impurity on the side of the InGa P layer 10. The present embodiment will be described …
FIG. 8, an 5 embedded-type gate in any one of the first, second, third, fourth, or fifth embodiment are made as a gate electrode 25 of an enhancement-type FET …
FIG. 9 is a cross sectional view of a semiconductor device according to the seventh 10 embodiment;
FIG. 10, a c hannel layer in any one of the first, second, third, fourth, fifth, sixth or seventh embodiment is made as. 25 an n-InGaAs layer 2 8, and an …
FIG. 11 shows a structure of the ninth 5 emb o diment in which a field-effect transistor in any one of the first, second, third, fourth, fifth, sixth or seventh …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a channel layer configured to flow a current; a gate electrode formed to control the current; and a two-layer structure in which an InGaP layer and a p- type GaAs layer being doped to be a p-type are contacted to one another, which is arranged on the channel layer in the same side to the gate electrode such that the p-type GaAs layer separates the channel layer from the InGaP layer.
The semiconductor device according to claim 1, wherein the two-layer structure is arranged between the channel layer and the gate electrode.
The semiconductor device according to claim 1, wherein the gate electrode is contacted with a recess formed in a part of the two-layer structure.
A semiconductor device in which a plural kinds of semiconductor devices are stacked on a single substrate, 2 Docket No. 8022-1229 Appln. No. 12/549,023 wherein a first kind semiconductor device among the plural kinds of semiconductor devices is the semiconductor device according to claim 1 and the two-layer structure is formed between the channel layer and the gate electrode, and a second kind semiconductor device among the plural kinds of semiconductor devices is a semiconductor device having another gate electrode being contacted with a recess formed in a part of the two-layer structure.
The semiconductor device according to claim 1, wherein the InGaP layer is an order type.
The semiconductor device according to claim 1, wherein the InGaP layer is a disorder type.
The semiconductor device according to claim 1, wherein the p-type GaAs layer is p-type doped evenly.
The semiconductor device according to 3 Docket No. 8022-1229 Appln. No. 12/549,023 claim 1, wherein the p-type GaAs layer is p-type delta doped.
The semiconductor device according to claim 1, wherein the channel layer is an undoped InGaAs layer, and the semiconductor device further comprises: an n-type doped A l GaAs layer on an one side or on both sides of the channel layer and configured to be a layer supplying electrons.
The semiconductor device according to claim GaAs layer.
The semiconductor device according to claim InGaAs layer, and the semiconductor device further an one side or on both sides of the channel layer
The semiconductor device according to claim whose anode is the gate electrode.
The semiconductor device according to claim
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with InGaP/p-type GaAs two-layer structure
enhancement-type FET with recess gate
Materials described outside the worked examples.
InGaP layer
InGaP
p-type GaAs layer
GaAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A is a cross sectional view of a semiconductor device according to the first embodiment. 25 The semiconductor device is a depletion-type field effect …
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Patent
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US 8,217,424Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross sectional view of a semiconductor device for explaining a pr o blem related 25 to the present invention;
FIG. 2B is an explanatory diagram of the semiconductor device for explaining a problem related to the present invention; 5 FI.G, 3A is a cross sectional view …
FIG. 3A is a cross sectional view of a semiconductor device according to the first embodiment. 25 The semiconductor device is a depletion-type field effect …
FIG. 4 is a cross sectional view of a semiconductor device according to the second embodiment. The semiconductor device is an enhancement-type field effect …
FIG. 5 is a cross sectional view of a semiconductor device according to the third embodiment. The semiconductor device includes a depletion-type field effect …
FIG. 6B. In the present embodiment, a p-type impurity is doped to ma k e an underlying GaAs layer as a p-type semiconductor. As a 10 result, a conduction band …
FIG. 7A, the corresponding GaAs layer 2 4 is delta doped with a p-type impurity on the side of the InGa P layer 10. The present embodiment will be described …
FIG. 8, an 5 embedded-type gate in any one of the first, second, third, fourth, or fifth embodiment are made as a gate electrode 25 of an enhancement-type FET …
FIG. 9 is a cross sectional view of a semiconductor device according to the seventh 10 embodiment;
FIG. 10, a c hannel layer in any one of the first, second, third, fourth, fifth, sixth or seventh embodiment is made as. 25 an n-InGaAs layer 2 8, and an …
FIG. 11 shows a structure of the ninth 5 emb o diment in which a field-effect transistor in any one of the first, second, third, fourth, fifth, sixth or seventh …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a channel layer configured to flow a current; a gate electrode formed to control the current; and a two-layer structure in which an InGaP layer and a p- type GaAs layer being doped to be a p-type are contacted to one another, which is arranged on the channel layer in the same side to the gate electrode such that the p-type GaAs layer separates the channel layer from the InGaP layer.
The semiconductor device according to claim 1, wherein the two-layer structure is arranged between the channel layer and the gate electrode.
The semiconductor device according to claim 1, wherein the gate electrode is contacted with a recess formed in a part of the two-layer structure.
A semiconductor device in which a plural kinds of semiconductor devices are stacked on a single substrate, 2 Docket No. 8022-1229 Appln. No. 12/549,023 wherein a first kind semiconductor device among the plural kinds of semiconductor devices is the semiconductor device according to claim 1 and the two-layer structure is formed between the channel layer and the gate electrode, and a second kind semiconductor device among the plural kinds of semiconductor devices is a semiconductor device having another gate electrode being contacted with a recess formed in a part of the two-layer structure.
The semiconductor device according to claim 1, wherein the InGaP layer is an order type.
The semiconductor device according to claim 1, wherein the InGaP layer is a disorder type.
The semiconductor device according to claim 1, wherein the p-type GaAs layer is p-type doped evenly.
The semiconductor device according to 3 Docket No. 8022-1229 Appln. No. 12/549,023 claim 1, wherein the p-type GaAs layer is p-type delta doped.
The semiconductor device according to claim 1, wherein the channel layer is an undoped InGaAs layer, and the semiconductor device further comprises: an n-type doped A l GaAs layer on an one side or on both sides of the channel layer and configured to be a layer supplying electrons.
The semiconductor device according to claim GaAs layer.
The semiconductor device according to claim InGaAs layer, and the semiconductor device further an one side or on both sides of the channel layer
The semiconductor device according to claim whose anode is the gate electrode.
The semiconductor device according to claim
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with InGaP/p-type GaAs two-layer structure
enhancement-type FET with recess gate
Materials described outside the worked examples.
InGaP layer
InGaP
p-type GaAs layer
GaAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A is a cross sectional view of a semiconductor device according to the first embodiment. 25 The semiconductor device is a depletion-type field effect …
Related documents with shared materials, methods, properties, or citations.
undoped InGaAs channel layer
InGaAs
n-type doped AlGaAs electron supply layer
AlGaAs
FIG. 4 is a cross sectional view of a semiconductor device according to the second embodiment. The semiconductor device is an enhancement-type field effect …
FIG. 5 is a cross sectional view of a semiconductor device according to the third embodiment. The semiconductor device includes a depletion-type field effect …
FIG. 8, an 5 embedded-type gate in any one of the first, second, third, fourth, or fifth embodiment are made as a gate electrode 25 of an enhancement-type FET …
FIG. 11 shows a structure of the ninth 5 emb o diment in which a field-effect transistor in any one of the first, second, third, fourth, fifth, sixth or seventh …
undoped InGaAs channel layer
InGaAs
n-type doped AlGaAs electron supply layer
AlGaAs
FIG. 4 is a cross sectional view of a semiconductor device according to the second embodiment. The semiconductor device is an enhancement-type field effect …
FIG. 5 is a cross sectional view of a semiconductor device according to the third embodiment. The semiconductor device includes a depletion-type field effect …
FIG. 8, an 5 embedded-type gate in any one of the first, second, third, fourth, or fifth embodiment are made as a gate electrode 25 of an enhancement-type FET …
FIG. 11 shows a structure of the ninth 5 emb o diment in which a field-effect transistor in any one of the first, second, third, fourth, fifth, sixth or seventh …
undoped InGaAs channel layer
InGaAs
n-type doped AlGaAs electron supply layer
AlGaAs
FIG. 4 is a cross sectional view of a semiconductor device according to the second embodiment. The semiconductor device is an enhancement-type field effect …
FIG. 5 is a cross sectional view of a semiconductor device according to the third embodiment. The semiconductor device includes a depletion-type field effect …
FIG. 8, an 5 embedded-type gate in any one of the first, second, third, fourth, or fifth embodiment are made as a gate electrode 25 of an enhancement-type FET …
FIG. 11 shows a structure of the ninth 5 emb o diment in which a field-effect transistor in any one of the first, second, third, fourth, fifth, sixth or seventh …
undoped InGaAs channel layer
InGaAs
n-type doped AlGaAs electron supply layer
AlGaAs
FIG. 4 is a cross sectional view of a semiconductor device according to the second embodiment. The semiconductor device is an enhancement-type field effect …
FIG. 5 is a cross sectional view of a semiconductor device according to the third embodiment. The semiconductor device includes a depletion-type field effect …
FIG. 8, an 5 embedded-type gate in any one of the first, second, third, fourth, or fifth embodiment are made as a gate electrode 25 of an enhancement-type FET …
FIG. 11 shows a structure of the ninth 5 emb o diment in which a field-effect transistor in any one of the first, second, third, fourth, fifth, sixth or seventh …