Patent
US 9,780,223GALLIUM ARSENIDE BASED MATERIALS USED IN THIN FILM TRANSISTOR APPLICATIONS
KAUSHAL K. SINGH, ROBERT JAN VISSER, BHASKAR KUMAR
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 -6 are cross sectional views of various embodiments of thin film transistor device structure;
Figure 7 is a flow chart of methods to manufacture a GaAs based solar cell according to embodiments of the invention;
Figure 8 depicts a simplified sectional perspective view of one embodiment of an aerosol assisted chemical vapor deposition (AACVD); 4573807 4 PATENT APPLICATION Attorney Docket No. 015444.02 D₁/CTO/ATG/ESONG
Figure 9 depicts a simplified sectional perspective view of one embodiment of a rapid thermal processing chamber; and
Figure 10 depicts a simplified sectional perspective view of one embodiment of an electrohydrodynamic jet (E-jet) printing system. [0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a thin film transistor structure, comprising: transferring a substrate having a dielectric layer disposed thereon into a processing chamber, supplying a GaAs containing precursor disposed in a solvent to the processing chamber; evaporating the GaAs containing precursor solvent in the processing chamber to form a GaAs based layer on the substrate; and forming a source-drain metal electrode layer adjacent to the GaAs based layer to form a thin film transistor structure.
The method of claim 1, wherein the GaAs containing precursor is selected from a group consisting of (NMe 2) 2 GaAs t BuH, Me 2 GaAs(NMe 2) 2, Me 2 GaAs(SiMePh 2) 2, Me 2 GaAs(Si Ph 3) 2, Et 2 GaAs(S i Me 2 Cy) 2, and Me 2 GaAs(SiMe 2 Cy) 2.
The method of claim 1, wherein evaporating the GaAs containing precursor solvent further comprises: annealing the GaAs based layer formed on the substrate.
The method of claim 1, further comprising: forming a doped GaAs layer on the GaAs based layer prior to forming the source-drain metal electrode layer.
The method of claim 1, wherein the source-drain metal electrode layer is fabricated by a metallic material selected from a group consisting of copper (Cu), gold (Au), silver (Ag), aluminum(AI), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), cobalt (Co), germanium (Ge), tantalum (Ta), titanium (Ti), gold (Au), alloy of titanium (Ti) and gold (Au), alloy of tantalum (Ta) and gold (Au), alloy of germanium (Ge) and gold (Au), alloy of aluminum(AI) and cobalt (Co), composite layers including a film stack having aluminum layer (A l) sandwiched between molybdenum (Mo), alloys thereof and combination thereof.
A method for forming a GaAs based material in a thin film transistor structure further comprising: forming a semiconductor layer on a dielectric layer disposed on a substrate, wherein the semiconductor layer is fabricated from a solution based GaAs based layer; and forming a source-drain metal electrode layer adjacent to the semiconductor layer.
The method of claim 8, further comprising: forming a doped semiconductor layer between the semiconductor layer and the source-drain metal electrode layer.
The method of claim 8, wherein the solution based GaAs based layer is fabricated from a GaAs containing precursor is selected from a group consisting of (NMe 2) 2 GaAs t BuH, Me 2 GaAs(NMe 2) 2, Me 2 GaAs(SiMePh 2) 2, Me 2 GaAs(SiPh 3) 2, Et 2 GaAs(SiMe 2 Cy) 2, and Me 2 GaAs(SiMe 2 Cy) 2.
3807 27 PATENT APPLICATION Attorney Docket No. 015444.02 D₁/CTO/ATG/ESONG
Layer stacks claimed or described, ordered top of device to substrate.
thin film transistor (TFT)
bottom gate thin film transistor (TFT) device 100
Materials described outside the worked examples.
GaAs based layer
GaAs
source-drain metal electrode layer
(NMe₂)2GaAstBuH
Me₂GaAs(NMe₂)2
Me₂GaAs(SiMePh₂)2
Me₂GaAs(SiPh₃)2
Et₂GaAs(SiMe₂Cy)2
Me₂GaAs(SiMe₂Cy)2
doped GaAs layer
metallic zinc dopants
Zn
dimethyl zinc (DMZ)
Zn(CH₃)2
diethyl zinc (DEZ)
Zn(C₂H₅)2
metallic magnesium dopants
Mg
cyclopentadienyl magnesium
carbon tetrachloride (CCl₄)
CCl₄
carbon tetrabromide (CBr₄)
CBr₄
hydrogen sulfide (H₂S)
H₂S
sulfur
S
silane (SiH₄)
SiH₄
disilane (Si₂H₆)
Si₂H₆
source-drain metal electrode materials
gate insulator layer
passivation layer
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 -6 are cross sectional views of various embodiments of thin film transistor device structure;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 400–4000 nm | — |
Thickness | 700–1000 nm | — |
Thickness | ≤ 700 nm | — |
Related documents with shared materials, methods, properties, or citations.
SYSTEM AND METHOD IN INDIUM-GALLIUM-ARSENIDE CHANNEL HEIGHT CONTROL FOR SUB 7NM FINFET
GALLIUM ARSENIDE BASED DEVICE HAVING A NARROW BAND-GAP SEMICONDUCTOR CONTACT LAYER
INXGA1-XASYP1-Y QUATERNARY ETCH STOP FOR IMPROVED CHEMICAL RESISTIVITY OF GALLIUM ARSENIDE FIELD EFFECT TRANSISTORS
Multiplexed Multi-stage Low Noise Amplifier Uses Gallium Arsenide and CMOS Dice
HIGH VALUE RESISTORS IN GALLIUM ARSENIDE
INDIUM GALLIUM ARSENIDE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAVING A LOW CONTACT RESISTANCE TO METAL ELECTRODE
INDIUM GALLIUM ARSENIDE SURFACE PASSIVATION BY SULFUR VAPOR TREATMENT
SEMICONDUCTOR DEVICE HAVING STACKED INGAP AND GAAS LAYERS, AND METHOD OF MAKING SAME
PSEUDOMORPHIC INGAAS ON GAAS FOR GATE-ALL-AROUND TRANSISTORS
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 -6 are cross sectional views of various embodiments of thin film transistor device structure;
Figure 7 is a flow chart of methods to manufacture a GaAs based solar cell according to embodiments of the invention;
Figure 8 depicts a simplified sectional perspective view of one embodiment of an aerosol assisted chemical vapor deposition (AACVD); 4573807 4 PATENT APPLICATION Attorney Docket No. 015444.02 D₁/CTO/ATG/ESONG
Figure 9 depicts a simplified sectional perspective view of one embodiment of a rapid thermal processing chamber; and
Figure 10 depicts a simplified sectional perspective view of one embodiment of an electrohydrodynamic jet (E-jet) printing system. [0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a thin film transistor structure, comprising: transferring a substrate having a dielectric layer disposed thereon into a processing chamber, supplying a GaAs containing precursor disposed in a solvent to the processing chamber; evaporating the GaAs containing precursor solvent in the processing chamber to form a GaAs based layer on the substrate; and forming a source-drain metal electrode layer adjacent to the GaAs based layer to form a thin film transistor structure.
The method of claim 1, wherein the GaAs containing precursor is selected from a group consisting of (NMe 2) 2 GaAs t BuH, Me 2 GaAs(NMe 2) 2, Me 2 GaAs(SiMePh 2) 2, Me 2 GaAs(Si Ph 3) 2, Et 2 GaAs(S i Me 2 Cy) 2, and Me 2 GaAs(SiMe 2 Cy) 2.
The method of claim 1, wherein evaporating the GaAs containing precursor solvent further comprises: annealing the GaAs based layer formed on the substrate.
The method of claim 1, further comprising: forming a doped GaAs layer on the GaAs based layer prior to forming the source-drain metal electrode layer.
The method of claim 1, wherein the source-drain metal electrode layer is fabricated by a metallic material selected from a group consisting of copper (Cu), gold (Au), silver (Ag), aluminum(AI), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), cobalt (Co), germanium (Ge), tantalum (Ta), titanium (Ti), gold (Au), alloy of titanium (Ti) and gold (Au), alloy of tantalum (Ta) and gold (Au), alloy of germanium (Ge) and gold (Au), alloy of aluminum(AI) and cobalt (Co), composite layers including a film stack having aluminum layer (A l) sandwiched between molybdenum (Mo), alloys thereof and combination thereof.
A method for forming a GaAs based material in a thin film transistor structure further comprising: forming a semiconductor layer on a dielectric layer disposed on a substrate, wherein the semiconductor layer is fabricated from a solution based GaAs based layer; and forming a source-drain metal electrode layer adjacent to the semiconductor layer.
The method of claim 8, further comprising: forming a doped semiconductor layer between the semiconductor layer and the source-drain metal electrode layer.
The method of claim 8, wherein the solution based GaAs based layer is fabricated from a GaAs containing precursor is selected from a group consisting of (NMe 2) 2 GaAs t BuH, Me 2 GaAs(NMe 2) 2, Me 2 GaAs(SiMePh 2) 2, Me 2 GaAs(SiPh 3) 2, Et 2 GaAs(SiMe 2 Cy) 2, and Me 2 GaAs(SiMe 2 Cy) 2.
3807 27 PATENT APPLICATION Attorney Docket No. 015444.02 D₁/CTO/ATG/ESONG
Layer stacks claimed or described, ordered top of device to substrate.
thin film transistor (TFT)
bottom gate thin film transistor (TFT) device 100
Materials described outside the worked examples.
GaAs based layer
GaAs
source-drain metal electrode layer
(NMe₂)2GaAstBuH
Me₂GaAs(NMe₂)2
Me₂GaAs(SiMePh₂)2
Me₂GaAs(SiPh₃)2
Et₂GaAs(SiMe₂Cy)2
Me₂GaAs(SiMe₂Cy)2
doped GaAs layer
metallic zinc dopants
Zn
dimethyl zinc (DMZ)
Zn(CH₃)2
diethyl zinc (DEZ)
Zn(C₂H₅)2
metallic magnesium dopants
Mg
cyclopentadienyl magnesium
carbon tetrachloride (CCl₄)
CCl₄
carbon tetrabromide (CBr₄)
CBr₄
hydrogen sulfide (H₂S)
H₂S
sulfur
S
silane (SiH₄)
SiH₄
disilane (Si₂H₆)
Si₂H₆
source-drain metal electrode materials
gate insulator layer
passivation layer
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 -6 are cross sectional views of various embodiments of thin film transistor device structure;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 400–4000 nm | — |
Thickness | 700–1000 nm | — |
Thickness | ≤ 700 nm | — |
Related documents with shared materials, methods, properties, or citations.
SYSTEM AND METHOD IN INDIUM-GALLIUM-ARSENIDE CHANNEL HEIGHT CONTROL FOR SUB 7NM FINFET
GALLIUM ARSENIDE BASED DEVICE HAVING A NARROW BAND-GAP SEMICONDUCTOR CONTACT LAYER
INXGA1-XASYP1-Y QUATERNARY ETCH STOP FOR IMPROVED CHEMICAL RESISTIVITY OF GALLIUM ARSENIDE FIELD EFFECT TRANSISTORS
Multiplexed Multi-stage Low Noise Amplifier Uses Gallium Arsenide and CMOS Dice
HIGH VALUE RESISTORS IN GALLIUM ARSENIDE
INDIUM GALLIUM ARSENIDE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAVING A LOW CONTACT RESISTANCE TO METAL ELECTRODE
INDIUM GALLIUM ARSENIDE SURFACE PASSIVATION BY SULFUR VAPOR TREATMENT
SEMICONDUCTOR DEVICE HAVING STACKED INGAP AND GAAS LAYERS, AND METHOD OF MAKING SAME
PSEUDOMORPHIC INGAAS ON GAAS FOR GATE-ALL-AROUND TRANSISTORS
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 -6 are cross sectional views of various embodiments of thin film transistor device structure;
Figure 7 is a flow chart of methods to manufacture a GaAs based solar cell according to embodiments of the invention;
Figure 8 depicts a simplified sectional perspective view of one embodiment of an aerosol assisted chemical vapor deposition (AACVD); 4573807 4 PATENT APPLICATION Attorney Docket No. 015444.02 D₁/CTO/ATG/ESONG
Figure 9 depicts a simplified sectional perspective view of one embodiment of a rapid thermal processing chamber; and
Figure 10 depicts a simplified sectional perspective view of one embodiment of an electrohydrodynamic jet (E-jet) printing system. [0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a thin film transistor structure, comprising: transferring a substrate having a dielectric layer disposed thereon into a processing chamber, supplying a GaAs containing precursor disposed in a solvent to the processing chamber; evaporating the GaAs containing precursor solvent in the processing chamber to form a GaAs based layer on the substrate; and forming a source-drain metal electrode layer adjacent to the GaAs based layer to form a thin film transistor structure.
The method of claim 1, wherein the GaAs containing precursor is selected from a group consisting of (NMe 2) 2 GaAs t BuH, Me 2 GaAs(NMe 2) 2, Me 2 GaAs(SiMePh 2) 2, Me 2 GaAs(Si Ph 3) 2, Et 2 GaAs(S i Me 2 Cy) 2, and Me 2 GaAs(SiMe 2 Cy) 2.
The method of claim 1, wherein evaporating the GaAs containing precursor solvent further comprises: annealing the GaAs based layer formed on the substrate.
The method of claim 1, further comprising: forming a doped GaAs layer on the GaAs based layer prior to forming the source-drain metal electrode layer.
The method of claim 1, wherein the source-drain metal electrode layer is fabricated by a metallic material selected from a group consisting of copper (Cu), gold (Au), silver (Ag), aluminum(AI), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), cobalt (Co), germanium (Ge), tantalum (Ta), titanium (Ti), gold (Au), alloy of titanium (Ti) and gold (Au), alloy of tantalum (Ta) and gold (Au), alloy of germanium (Ge) and gold (Au), alloy of aluminum(AI) and cobalt (Co), composite layers including a film stack having aluminum layer (A l) sandwiched between molybdenum (Mo), alloys thereof and combination thereof.
A method for forming a GaAs based material in a thin film transistor structure further comprising: forming a semiconductor layer on a dielectric layer disposed on a substrate, wherein the semiconductor layer is fabricated from a solution based GaAs based layer; and forming a source-drain metal electrode layer adjacent to the semiconductor layer.
The method of claim 8, further comprising: forming a doped semiconductor layer between the semiconductor layer and the source-drain metal electrode layer.
The method of claim 8, wherein the solution based GaAs based layer is fabricated from a GaAs containing precursor is selected from a group consisting of (NMe 2) 2 GaAs t BuH, Me 2 GaAs(NMe 2) 2, Me 2 GaAs(SiMePh 2) 2, Me 2 GaAs(SiPh 3) 2, Et 2 GaAs(SiMe 2 Cy) 2, and Me 2 GaAs(SiMe 2 Cy) 2.
3807 27 PATENT APPLICATION Attorney Docket No. 015444.02 D₁/CTO/ATG/ESONG
Layer stacks claimed or described, ordered top of device to substrate.
thin film transistor (TFT)
bottom gate thin film transistor (TFT) device 100
Materials described outside the worked examples.
GaAs based layer
GaAs
source-drain metal electrode layer
(NMe₂)2GaAstBuH
Me₂GaAs(NMe₂)2
Me₂GaAs(SiMePh₂)2
Me₂GaAs(SiPh₃)2
Et₂GaAs(SiMe₂Cy)2
Me₂GaAs(SiMe₂Cy)2
doped GaAs layer
metallic zinc dopants
Zn
dimethyl zinc (DMZ)
Zn(CH₃)2
diethyl zinc (DEZ)
Zn(C₂H₅)2
metallic magnesium dopants
Mg
cyclopentadienyl magnesium
carbon tetrachloride (CCl₄)
CCl₄
carbon tetrabromide (CBr₄)
CBr₄
hydrogen sulfide (H₂S)
H₂S
sulfur
S
silane (SiH₄)
SiH₄
disilane (Si₂H₆)
Si₂H₆
source-drain metal electrode materials
gate insulator layer
passivation layer
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 -6 are cross sectional views of various embodiments of thin film transistor device structure;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 400–4000 nm | — |
Thickness | 700–1000 nm | — |
Thickness | ≤ 700 nm | — |
Related documents with shared materials, methods, properties, or citations.
SYSTEM AND METHOD IN INDIUM-GALLIUM-ARSENIDE CHANNEL HEIGHT CONTROL FOR SUB 7NM FINFET
GALLIUM ARSENIDE BASED DEVICE HAVING A NARROW BAND-GAP SEMICONDUCTOR CONTACT LAYER
INXGA1-XASYP1-Y QUATERNARY ETCH STOP FOR IMPROVED CHEMICAL RESISTIVITY OF GALLIUM ARSENIDE FIELD EFFECT TRANSISTORS
Multiplexed Multi-stage Low Noise Amplifier Uses Gallium Arsenide and CMOS Dice
HIGH VALUE RESISTORS IN GALLIUM ARSENIDE
INDIUM GALLIUM ARSENIDE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAVING A LOW CONTACT RESISTANCE TO METAL ELECTRODE
INDIUM GALLIUM ARSENIDE SURFACE PASSIVATION BY SULFUR VAPOR TREATMENT
SEMICONDUCTOR DEVICE HAVING STACKED INGAP AND GAAS LAYERS, AND METHOD OF MAKING SAME
PSEUDOMORPHIC INGAAS ON GAAS FOR GATE-ALL-AROUND TRANSISTORS
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 -6 are cross sectional views of various embodiments of thin film transistor device structure;
Figure 7 is a flow chart of methods to manufacture a GaAs based solar cell according to embodiments of the invention;
Figure 8 depicts a simplified sectional perspective view of one embodiment of an aerosol assisted chemical vapor deposition (AACVD); 4573807 4 PATENT APPLICATION Attorney Docket No. 015444.02 D₁/CTO/ATG/ESONG
Figure 9 depicts a simplified sectional perspective view of one embodiment of a rapid thermal processing chamber; and
Figure 10 depicts a simplified sectional perspective view of one embodiment of an electrohydrodynamic jet (E-jet) printing system. [0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a thin film transistor structure, comprising: transferring a substrate having a dielectric layer disposed thereon into a processing chamber, supplying a GaAs containing precursor disposed in a solvent to the processing chamber; evaporating the GaAs containing precursor solvent in the processing chamber to form a GaAs based layer on the substrate; and forming a source-drain metal electrode layer adjacent to the GaAs based layer to form a thin film transistor structure.
The method of claim 1, wherein the GaAs containing precursor is selected from a group consisting of (NMe 2) 2 GaAs t BuH, Me 2 GaAs(NMe 2) 2, Me 2 GaAs(SiMePh 2) 2, Me 2 GaAs(Si Ph 3) 2, Et 2 GaAs(S i Me 2 Cy) 2, and Me 2 GaAs(SiMe 2 Cy) 2.
The method of claim 1, wherein evaporating the GaAs containing precursor solvent further comprises: annealing the GaAs based layer formed on the substrate.
The method of claim 1, further comprising: forming a doped GaAs layer on the GaAs based layer prior to forming the source-drain metal electrode layer.
The method of claim 1, wherein the source-drain metal electrode layer is fabricated by a metallic material selected from a group consisting of copper (Cu), gold (Au), silver (Ag), aluminum(AI), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), cobalt (Co), germanium (Ge), tantalum (Ta), titanium (Ti), gold (Au), alloy of titanium (Ti) and gold (Au), alloy of tantalum (Ta) and gold (Au), alloy of germanium (Ge) and gold (Au), alloy of aluminum(AI) and cobalt (Co), composite layers including a film stack having aluminum layer (A l) sandwiched between molybdenum (Mo), alloys thereof and combination thereof.
A method for forming a GaAs based material in a thin film transistor structure further comprising: forming a semiconductor layer on a dielectric layer disposed on a substrate, wherein the semiconductor layer is fabricated from a solution based GaAs based layer; and forming a source-drain metal electrode layer adjacent to the semiconductor layer.
The method of claim 8, further comprising: forming a doped semiconductor layer between the semiconductor layer and the source-drain metal electrode layer.
The method of claim 8, wherein the solution based GaAs based layer is fabricated from a GaAs containing precursor is selected from a group consisting of (NMe 2) 2 GaAs t BuH, Me 2 GaAs(NMe 2) 2, Me 2 GaAs(SiMePh 2) 2, Me 2 GaAs(SiPh 3) 2, Et 2 GaAs(SiMe 2 Cy) 2, and Me 2 GaAs(SiMe 2 Cy) 2.
3807 27 PATENT APPLICATION Attorney Docket No. 015444.02 D₁/CTO/ATG/ESONG
Layer stacks claimed or described, ordered top of device to substrate.
thin film transistor (TFT)
bottom gate thin film transistor (TFT) device 100
Materials described outside the worked examples.
GaAs based layer
GaAs
source-drain metal electrode layer
(NMe₂)2GaAstBuH
Me₂GaAs(NMe₂)2
Me₂GaAs(SiMePh₂)2
Me₂GaAs(SiPh₃)2
Et₂GaAs(SiMe₂Cy)2
Me₂GaAs(SiMe₂Cy)2
doped GaAs layer
metallic zinc dopants
Zn
dimethyl zinc (DMZ)
Zn(CH₃)2
diethyl zinc (DEZ)
Zn(C₂H₅)2
metallic magnesium dopants
Mg
cyclopentadienyl magnesium
carbon tetrachloride (CCl₄)
CCl₄
carbon tetrabromide (CBr₄)
CBr₄
hydrogen sulfide (H₂S)
H₂S
sulfur
S
silane (SiH₄)
SiH₄
disilane (Si₂H₆)
Si₂H₆
source-drain metal electrode materials
gate insulator layer
passivation layer
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 -6 are cross sectional views of various embodiments of thin film transistor device structure;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 400–4000 nm | — |
Thickness | 700–1000 nm | — |
Thickness | ≤ 700 nm | — |
Related documents with shared materials, methods, properties, or citations.
SYSTEM AND METHOD IN INDIUM-GALLIUM-ARSENIDE CHANNEL HEIGHT CONTROL FOR SUB 7NM FINFET
GALLIUM ARSENIDE BASED DEVICE HAVING A NARROW BAND-GAP SEMICONDUCTOR CONTACT LAYER
INXGA1-XASYP1-Y QUATERNARY ETCH STOP FOR IMPROVED CHEMICAL RESISTIVITY OF GALLIUM ARSENIDE FIELD EFFECT TRANSISTORS
Multiplexed Multi-stage Low Noise Amplifier Uses Gallium Arsenide and CMOS Dice
HIGH VALUE RESISTORS IN GALLIUM ARSENIDE
INDIUM GALLIUM ARSENIDE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAVING A LOW CONTACT RESISTANCE TO METAL ELECTRODE
INDIUM GALLIUM ARSENIDE SURFACE PASSIVATION BY SULFUR VAPOR TREATMENT
SEMICONDUCTOR DEVICE HAVING STACKED INGAP AND GAAS LAYERS, AND METHOD OF MAKING SAME
PSEUDOMORPHIC INGAAS ON GAAS FOR GATE-ALL-AROUND TRANSISTORS