Patent
US 10,559,669INDIUM GALLIUM ARSENIDE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR HAVING A LOW CONTACT RESISTANCE TO METAL ELECTRODE
Ning Li
US
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US 10,559,669Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a side cross-sectional view of a metal oxide semiconductor field effect transistor device that includes at least one of a source region and a drain …
FIG. 2 is a side cross-sectional view of forming a surface passivation layer on an interface surface of at least one of the source region and the drain region, …
FIG. 3 is a side cross-sectional view of forming a metal fill and corresponding metal layer on the n-type zin c oxide layer that is depicted in
FIG. 4 is a side cross-sectional view of planarizing the structure depicted in
FIG. 5 is a plot of the contact resistivity of a contact to a source/drain region including a type I II -V semiconductor material and an n-type conductivity, …
FIG. 6 is a plot of a band alignment between an n-type zin c oxide layer and a type I II-V semiconductor material of indium gallium arsenide (InGaAs), in …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a semiconductor device comprising: providing a field effect transistor including a region composed of a type I II-V semiconductor material and an n-type conductivity; forming at least one of sulfur passivation layer and an aluminum containing layer on an interface surface of the at least one of the type I II -V semiconductor material to provide a passivated surface; forming an n-type zinc oxide containing layer on the passivated surface; and forming a metal contact on the n-type zinc oxide containing layer. Original
The method of claim 1, wherein the type I II -V semiconductor material is indium gallium arsenide (InGaAs). Original
The method of claim 1, wherein a channel region of the field effect transistor comprises indium gallium arsenide (InGaAs). Currently amended
The method of claim 1, wherein the sulfur passivation layer is formed by applying a thiourea containing solution. Original
The method of claim 1, wherein the aluminum containing layer comprises aluminum oxide formed by atomic layer deposition (ALD). Original
The method of claim 1, wherein the n-type zinc oxide containing layer is formed by atomic layer deposition. Original
The method of claim 1, wherein the metal contact is composed of a composition selected from aluminum, titanium, and combinations thereof. Original
The method of claim 1, wherein a conduction band of the type I II-V semiconductor material is substantially aligned with a conduction band of the n-type zinc oxide containing layer. Original
A method of forming a semiconductor device comprising: providing a field effect transistor including a region composed of indium gallium arsenide (I nGaAs) doped to an n-type conductivity; forming at least one of sulfur passivation layer and an aluminum containing layer on an interface surface the region of the type I II -V semiconductor material to provide a passivated surface; forming an n-type zinc oxide containing layer on the passivated surface, wherein a conduction band of the I nGaAs is substantially aligned with a conduction band of the n-type zinc oxide containing layer; and forming a metal contact is formed on the n-type zinc oxide containing layer. Original
The method of claim 11, wherein a channel region of the field effect transistor comprises indium gallium arsenide (I nGaAs). Currently amended
The method of claim 11, wherein the sulfur passivation layer is formed by applying a thiourea containing solution. Original
The method of claim 11, wherein the aluminum containing layer comprises aluminum oxide formed by atomic layer deposition (ALD). Original
A semiconductor device comprising: an n-type conductivity region comprised of a type I II -V semiconductor material; and a contact to the n-type conductivity region, wherein the contact comprises an interface passivation layer atop the type I II -V semiconductor material, and an n-type zinc oxide layer, wherein a conduction band of the type I II -V semiconductor material is substantially aligned with a conduction band of the n-type zinc oxide containing layer. Original
The semiconductor device of claim 15, wherein the contact may further include a metal containing portion on the n-type zinc oxide containing layer. Original
The semiconductor device of claim 15, wherein the type III -V semiconductor material is indium gallium arsenide (InGaAs). Original
The semiconductor device of claim 15, wherein the interface passivation layer includes a sulfur passivation layer. Original
The semiconductor device of claim 15, wherein the interface passivation layer includes an aluminum oxide monolayer. Original
Layer stacks claimed or described, ordered top of device to substrate.
InGaAs MOSFET
Materials described outside the worked examples.
type III-V semiconductor material
sulfur passivation layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a side cross-sectional view of a metal oxide semiconductor field effect transistor device that includes at least one of a source region and a drain …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness | 1–4 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,559,669Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a side cross-sectional view of a metal oxide semiconductor field effect transistor device that includes at least one of a source region and a drain …
FIG. 2 is a side cross-sectional view of forming a surface passivation layer on an interface surface of at least one of the source region and the drain region, …
FIG. 3 is a side cross-sectional view of forming a metal fill and corresponding metal layer on the n-type zin c oxide layer that is depicted in
FIG. 4 is a side cross-sectional view of planarizing the structure depicted in
FIG. 5 is a plot of the contact resistivity of a contact to a source/drain region including a type I II -V semiconductor material and an n-type conductivity, …
FIG. 6 is a plot of a band alignment between an n-type zin c oxide layer and a type I II-V semiconductor material of indium gallium arsenide (InGaAs), in …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a semiconductor device comprising: providing a field effect transistor including a region composed of a type I II-V semiconductor material and an n-type conductivity; forming at least one of sulfur passivation layer and an aluminum containing layer on an interface surface of the at least one of the type I II -V semiconductor material to provide a passivated surface; forming an n-type zinc oxide containing layer on the passivated surface; and forming a metal contact on the n-type zinc oxide containing layer. Original
The method of claim 1, wherein the type I II -V semiconductor material is indium gallium arsenide (InGaAs). Original
The method of claim 1, wherein a channel region of the field effect transistor comprises indium gallium arsenide (InGaAs). Currently amended
The method of claim 1, wherein the sulfur passivation layer is formed by applying a thiourea containing solution. Original
The method of claim 1, wherein the aluminum containing layer comprises aluminum oxide formed by atomic layer deposition (ALD). Original
The method of claim 1, wherein the n-type zinc oxide containing layer is formed by atomic layer deposition. Original
The method of claim 1, wherein the metal contact is composed of a composition selected from aluminum, titanium, and combinations thereof. Original
The method of claim 1, wherein a conduction band of the type I II-V semiconductor material is substantially aligned with a conduction band of the n-type zinc oxide containing layer. Original
A method of forming a semiconductor device comprising: providing a field effect transistor including a region composed of indium gallium arsenide (I nGaAs) doped to an n-type conductivity; forming at least one of sulfur passivation layer and an aluminum containing layer on an interface surface the region of the type I II -V semiconductor material to provide a passivated surface; forming an n-type zinc oxide containing layer on the passivated surface, wherein a conduction band of the I nGaAs is substantially aligned with a conduction band of the n-type zinc oxide containing layer; and forming a metal contact is formed on the n-type zinc oxide containing layer. Original
The method of claim 11, wherein a channel region of the field effect transistor comprises indium gallium arsenide (I nGaAs). Currently amended
The method of claim 11, wherein the sulfur passivation layer is formed by applying a thiourea containing solution. Original
The method of claim 11, wherein the aluminum containing layer comprises aluminum oxide formed by atomic layer deposition (ALD). Original
A semiconductor device comprising: an n-type conductivity region comprised of a type I II -V semiconductor material; and a contact to the n-type conductivity region, wherein the contact comprises an interface passivation layer atop the type I II -V semiconductor material, and an n-type zinc oxide layer, wherein a conduction band of the type I II -V semiconductor material is substantially aligned with a conduction band of the n-type zinc oxide containing layer. Original
The semiconductor device of claim 15, wherein the contact may further include a metal containing portion on the n-type zinc oxide containing layer. Original
The semiconductor device of claim 15, wherein the type III -V semiconductor material is indium gallium arsenide (InGaAs). Original
The semiconductor device of claim 15, wherein the interface passivation layer includes a sulfur passivation layer. Original
The semiconductor device of claim 15, wherein the interface passivation layer includes an aluminum oxide monolayer. Original
Layer stacks claimed or described, ordered top of device to substrate.
InGaAs MOSFET
Materials described outside the worked examples.
type III-V semiconductor material
sulfur passivation layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a side cross-sectional view of a metal oxide semiconductor field effect transistor device that includes at least one of a source region and a drain …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness | 1–4 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,559,669Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a side cross-sectional view of a metal oxide semiconductor field effect transistor device that includes at least one of a source region and a drain …
FIG. 2 is a side cross-sectional view of forming a surface passivation layer on an interface surface of at least one of the source region and the drain region, …
FIG. 3 is a side cross-sectional view of forming a metal fill and corresponding metal layer on the n-type zin c oxide layer that is depicted in
FIG. 4 is a side cross-sectional view of planarizing the structure depicted in
FIG. 5 is a plot of the contact resistivity of a contact to a source/drain region including a type I II -V semiconductor material and an n-type conductivity, …
FIG. 6 is a plot of a band alignment between an n-type zin c oxide layer and a type I II-V semiconductor material of indium gallium arsenide (InGaAs), in …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a semiconductor device comprising: providing a field effect transistor including a region composed of a type I II-V semiconductor material and an n-type conductivity; forming at least one of sulfur passivation layer and an aluminum containing layer on an interface surface of the at least one of the type I II -V semiconductor material to provide a passivated surface; forming an n-type zinc oxide containing layer on the passivated surface; and forming a metal contact on the n-type zinc oxide containing layer. Original
The method of claim 1, wherein the type I II -V semiconductor material is indium gallium arsenide (InGaAs). Original
The method of claim 1, wherein a channel region of the field effect transistor comprises indium gallium arsenide (InGaAs). Currently amended
The method of claim 1, wherein the sulfur passivation layer is formed by applying a thiourea containing solution. Original
The method of claim 1, wherein the aluminum containing layer comprises aluminum oxide formed by atomic layer deposition (ALD). Original
The method of claim 1, wherein the n-type zinc oxide containing layer is formed by atomic layer deposition. Original
The method of claim 1, wherein the metal contact is composed of a composition selected from aluminum, titanium, and combinations thereof. Original
The method of claim 1, wherein a conduction band of the type I II-V semiconductor material is substantially aligned with a conduction band of the n-type zinc oxide containing layer. Original
A method of forming a semiconductor device comprising: providing a field effect transistor including a region composed of indium gallium arsenide (I nGaAs) doped to an n-type conductivity; forming at least one of sulfur passivation layer and an aluminum containing layer on an interface surface the region of the type I II -V semiconductor material to provide a passivated surface; forming an n-type zinc oxide containing layer on the passivated surface, wherein a conduction band of the I nGaAs is substantially aligned with a conduction band of the n-type zinc oxide containing layer; and forming a metal contact is formed on the n-type zinc oxide containing layer. Original
The method of claim 11, wherein a channel region of the field effect transistor comprises indium gallium arsenide (I nGaAs). Currently amended
The method of claim 11, wherein the sulfur passivation layer is formed by applying a thiourea containing solution. Original
The method of claim 11, wherein the aluminum containing layer comprises aluminum oxide formed by atomic layer deposition (ALD). Original
A semiconductor device comprising: an n-type conductivity region comprised of a type I II -V semiconductor material; and a contact to the n-type conductivity region, wherein the contact comprises an interface passivation layer atop the type I II -V semiconductor material, and an n-type zinc oxide layer, wherein a conduction band of the type I II -V semiconductor material is substantially aligned with a conduction band of the n-type zinc oxide containing layer. Original
The semiconductor device of claim 15, wherein the contact may further include a metal containing portion on the n-type zinc oxide containing layer. Original
The semiconductor device of claim 15, wherein the type III -V semiconductor material is indium gallium arsenide (InGaAs). Original
The semiconductor device of claim 15, wherein the interface passivation layer includes a sulfur passivation layer. Original
The semiconductor device of claim 15, wherein the interface passivation layer includes an aluminum oxide monolayer. Original
Layer stacks claimed or described, ordered top of device to substrate.
InGaAs MOSFET
Materials described outside the worked examples.
type III-V semiconductor material
sulfur passivation layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a side cross-sectional view of a metal oxide semiconductor field effect transistor device that includes at least one of a source region and a drain …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness | 1–4 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,559,669Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a side cross-sectional view of a metal oxide semiconductor field effect transistor device that includes at least one of a source region and a drain …
FIG. 2 is a side cross-sectional view of forming a surface passivation layer on an interface surface of at least one of the source region and the drain region, …
FIG. 3 is a side cross-sectional view of forming a metal fill and corresponding metal layer on the n-type zin c oxide layer that is depicted in
FIG. 4 is a side cross-sectional view of planarizing the structure depicted in
FIG. 5 is a plot of the contact resistivity of a contact to a source/drain region including a type I II -V semiconductor material and an n-type conductivity, …
FIG. 6 is a plot of a band alignment between an n-type zin c oxide layer and a type I II-V semiconductor material of indium gallium arsenide (InGaAs), in …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a semiconductor device comprising: providing a field effect transistor including a region composed of a type I II-V semiconductor material and an n-type conductivity; forming at least one of sulfur passivation layer and an aluminum containing layer on an interface surface of the at least one of the type I II -V semiconductor material to provide a passivated surface; forming an n-type zinc oxide containing layer on the passivated surface; and forming a metal contact on the n-type zinc oxide containing layer. Original
The method of claim 1, wherein the type I II -V semiconductor material is indium gallium arsenide (InGaAs). Original
The method of claim 1, wherein a channel region of the field effect transistor comprises indium gallium arsenide (InGaAs). Currently amended
The method of claim 1, wherein the sulfur passivation layer is formed by applying a thiourea containing solution. Original
The method of claim 1, wherein the aluminum containing layer comprises aluminum oxide formed by atomic layer deposition (ALD). Original
The method of claim 1, wherein the n-type zinc oxide containing layer is formed by atomic layer deposition. Original
The method of claim 1, wherein the metal contact is composed of a composition selected from aluminum, titanium, and combinations thereof. Original
The method of claim 1, wherein a conduction band of the type I II-V semiconductor material is substantially aligned with a conduction band of the n-type zinc oxide containing layer. Original
A method of forming a semiconductor device comprising: providing a field effect transistor including a region composed of indium gallium arsenide (I nGaAs) doped to an n-type conductivity; forming at least one of sulfur passivation layer and an aluminum containing layer on an interface surface the region of the type I II -V semiconductor material to provide a passivated surface; forming an n-type zinc oxide containing layer on the passivated surface, wherein a conduction band of the I nGaAs is substantially aligned with a conduction band of the n-type zinc oxide containing layer; and forming a metal contact is formed on the n-type zinc oxide containing layer. Original
The method of claim 11, wherein a channel region of the field effect transistor comprises indium gallium arsenide (I nGaAs). Currently amended
The method of claim 11, wherein the sulfur passivation layer is formed by applying a thiourea containing solution. Original
The method of claim 11, wherein the aluminum containing layer comprises aluminum oxide formed by atomic layer deposition (ALD). Original
A semiconductor device comprising: an n-type conductivity region comprised of a type I II -V semiconductor material; and a contact to the n-type conductivity region, wherein the contact comprises an interface passivation layer atop the type I II -V semiconductor material, and an n-type zinc oxide layer, wherein a conduction band of the type I II -V semiconductor material is substantially aligned with a conduction band of the n-type zinc oxide containing layer. Original
The semiconductor device of claim 15, wherein the contact may further include a metal containing portion on the n-type zinc oxide containing layer. Original
The semiconductor device of claim 15, wherein the type III -V semiconductor material is indium gallium arsenide (InGaAs). Original
The semiconductor device of claim 15, wherein the interface passivation layer includes a sulfur passivation layer. Original
The semiconductor device of claim 15, wherein the interface passivation layer includes an aluminum oxide monolayer. Original
Layer stacks claimed or described, ordered top of device to substrate.
InGaAs MOSFET
Materials described outside the worked examples.
type III-V semiconductor material
sulfur passivation layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a side cross-sectional view of a metal oxide semiconductor field effect transistor device that includes at least one of a source region and a drain …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness | 1–4 nm |
Related documents with shared materials, methods, properties, or citations.
III-V semiconductor device with ZnO-based contact
aluminum containing layer (aluminum oxide)
Al₂O₃
n-type zinc oxide containing layer
ZnO
indium gallium arsenide
InGaAs
thiourea containing solution
metal contact
indium aluminum arsenic
InAlAs
indium phosphide
InP
high-k gate dielectric
FIG. 6 is a plot of a band alignment between an n-type zin c oxide layer and a type I II-V semiconductor material of indium gallium arsenide (InGaAs), in …
| — |
Temperature | 20–25 °C | — |
Temperature | 60–95 °C | — |
Thickness | 0.1–5 nm | — |
Temperature | 25–900 °C | — |
Thickness | ≤ 5 nm | — |
III-V semiconductor device with ZnO-based contact
aluminum containing layer (aluminum oxide)
Al₂O₃
n-type zinc oxide containing layer
ZnO
indium gallium arsenide
InGaAs
thiourea containing solution
metal contact
indium aluminum arsenic
InAlAs
indium phosphide
InP
high-k gate dielectric
FIG. 6 is a plot of a band alignment between an n-type zin c oxide layer and a type I II-V semiconductor material of indium gallium arsenide (InGaAs), in …
| — |
Temperature | 20–25 °C | — |
Temperature | 60–95 °C | — |
Thickness | 0.1–5 nm | — |
Temperature | 25–900 °C | — |
Thickness | ≤ 5 nm | — |
III-V semiconductor device with ZnO-based contact
aluminum containing layer (aluminum oxide)
Al₂O₃
n-type zinc oxide containing layer
ZnO
indium gallium arsenide
InGaAs
thiourea containing solution
metal contact
indium aluminum arsenic
InAlAs
indium phosphide
InP
high-k gate dielectric
FIG. 6 is a plot of a band alignment between an n-type zin c oxide layer and a type I II-V semiconductor material of indium gallium arsenide (InGaAs), in …
| — |
Temperature | 20–25 °C | — |
Temperature | 60–95 °C | — |
Thickness | 0.1–5 nm | — |
Temperature | 25–900 °C | — |
Thickness | ≤ 5 nm | — |
III-V semiconductor device with ZnO-based contact
aluminum containing layer (aluminum oxide)
Al₂O₃
n-type zinc oxide containing layer
ZnO
indium gallium arsenide
InGaAs
thiourea containing solution
metal contact
indium aluminum arsenic
InAlAs
indium phosphide
InP
high-k gate dielectric
FIG. 6 is a plot of a band alignment between an n-type zin c oxide layer and a type I II-V semiconductor material of indium gallium arsenide (InGaAs), in …
| — |
Temperature | 20–25 °C | — |
Temperature | 60–95 °C | — |
Thickness | 0.1–5 nm | — |
Temperature | 25–900 °C | — |
Thickness | ≤ 5 nm | — |