ENHANCEMENT-MODE/DEPLETION-MODE FIELD-EFFECT TRANSISTOR GAN TECHNOLOGY

Jose Jimenez

Patent

Atlas literature

Patent

US 10,446,544

ENHANCEMENT-MODE/DEPLETION-MODE FIELD-EFFECT TRANSISTOR GAN TECHNOLOGY

Jose Jimenez

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

3 independent · 22 dependent

1
Independentthreshold voltage shift layer semiconductor material (higher bandgap)channel layer semiconductor material (lower bandgap)integrated circuit die with E-mode and D-mode field-effect devices
An integrated circuit die comprising: " a substrate; " a ﬁrst device stack disposed upon the substrate; and " a second device stack spaced from the ﬁrst device stack and disposed upon the substrate, the second device stack comprising: " a ﬁrst portion of a channel layer; and " a threshold voltage shift layer disposed between the ﬁrst portion of the channel layer portion and the substrate, wherein the threshold voltage shift layer is conﬁgured to set a ﬁrst threshold voltage that is a minimum device control voltage required to create a conducting path within the ﬁrst portion of the channel layer, wherein the threshold voltage shift layer is made of a ﬁrst semiconductor material having a ﬁrst bandgap that is higher than a second bandgap of a second semiconductor material making up the channel layer. Currently amended
1. 2
  Dependent← claim 1integrated circuit die with E-mode and D-mode field-effect devices
  The integrated circuit die of claim 1 wherein the ﬁrst device stack comprises an enhancement-mode (E-mode) ﬁeld-eﬀect device and the second stack device comprises a depletion-mode (D-mode) ﬁeld-eﬀect device. Original
2. 3
  Dependent← claim 1integrated circuit die with E-mode and D-mode field-effect devices
  The integrated circuit die of claim 1 wherein the ﬁrst device stack comprises a D- mode ﬁeld-eﬀect device and the second stack device comprises an E-mode ﬁeld-eﬀect device. Original
3. 4
  Dependent← claim 1integrated circuit die with E-mode and D-mode field-effect devices
  The integrated circuit die of claim 1 wherein the ﬁrst threshold voltage is determined by a predetermined thickness of the threshold voltage shift layer. Original
4. 7
  Dependent← claim 1integrated circuit die with E-mode and D-mode field-effect devices
  The integrated circuit die of claim 1 wherein the ﬁrst threshold voltage is determined by a predetermined dopant density within the threshold voltage shift layer. Original
5. 10
  Dependent← claim 1integrated circuit die with E-mode and D-mode field-effect devices
  The integrated circuit die of claim 1 wherein the ﬁrst threshold voltage is determined by both a predetermined thickness of the threshold voltage shift layer and a predetermined dopant density of the threshold voltage shift layer. Original
6. 11
  Dependent← claim 1GaNintegrated circuit die with E-mode and D-mode field-effect devices
  The integrated circuit die of claim 1 wherein the ﬁrst device stack and the second device stack are both gallium nitride based. Original
7. 13
  Dependent← claim 1integrated circuit die with E-mode and D-mode field-effect devices
  The integrated circuit die of claim 1 wherein the second device stack has a second threshold voltage that is opposite in polarity from the ﬁrst threshold voltage of the ﬁrst device stack. Original
12
Independent
. Canceled
14
Independentthreshold voltage shift layer semiconductor material (higher bandgap)channel layer semiconductor material (lower bandgap)fabricated integrated circuit die (method claim)
A method of fabricating an integrated circuit die comprising: " providing a substrate; " disposing a buﬀer layer over the substrate; " disposing a threshold voltage shift layer over the buﬀer layer to a predetermined thickness; " masking the threshold voltage shift layer with an etch mask to deﬁne a ﬁrst device stack location; " etching through the threshold voltage shift layer not masked by the etch mask to create an exposed portion of the buﬀer layer; " removing the etch mask to expose a non-etched portion of the threshold voltage shift layer; " disposing a channel layer over the exposed portion of the buﬀer layer and the non-etched portion of the threshold voltage shift layer, wherein the threshold voltage shift layer is conﬁgured to set a ﬁrst threshold voltage that is a minimum device control voltage required to create a conducting path within a portion of the channel layer residing over the non-etched portion of the threshold voltage shift layer. Original
1. 15
  Dependent← claim 14fabricated integrated circuit die (method claim)
  The method of fabricating the integrated circuit die of claim 14 further comprising: " disposing a barrier layer over the channel layer; " forming an isolation region adjacent to the ﬁrst device stack location to deﬁne a second device stack location spaced from the ﬁrst device stack location; " disposing a ﬁrst gate over the barrier layer at the ﬁrst device stack location; and " disposing a second gate over the barrier layer at the second device stack location. Original
2. 20
  Dependent← claim 14fabricated integrated circuit die (method claim)
  The method of fabricating the integrated circuit die of claim 14 wherein the ﬁrst threshold voltage is determined by a predetermined thickness of the threshold voltage shift layer. Original
3. 22
  Dependent← claim 14fabricated integrated circuit die (method claim)
  The method of fabricating the integrated circuit die of claim 14 wherein the ﬁrst threshold voltage is determined by a predetermined dopant density within the threshold voltage shift layer. Original
4. 24
  Dependent← claim 14threshold voltage shift layer semiconductor material (higher bandgap)channel layer semiconductor material (lower bandgap)fabricated integrated circuit die (method claim)
  The method of fabricating the integrated circuit die of claim 14 wherein the threshold voltage shift layer is made of a ﬁrst semiconductor material having a ﬁrst bandgap that is higher than a second bandgap of a second semiconductor material making up the channel layer. Original
5. 25
  Dependent← claim 14GaNfabricated integrated circuit die (method claim)
  The method of fabricating the integrated circuit of claim 14 wherein the buﬀer layer is made of gallium nitride. Original

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

integrated circuit die with E-mode and D-mode field-effect devices

barrier_layerbarrier layer

channel layer semiconductor material (lower bandgap)channel layer

threshold voltage shift layer semiconductor material (higher bandgap)threshold voltage shift layer

GaNbuffer layer

substratesubstrate

fabricated integrated circuit die (method claim)

Materials

Materials described outside the worked examples.

threshold voltage shift layer semiconductor material (higher bandgap)

Threshold Voltage Shift Layer

channel layer semiconductor material (lower bandgap)

Channel Material

Process steps

Additional fabrication and treatment steps described in the patent.

Layer Deposition And Etch

Step 1

Process details

steps:providing a substrate, disposing a buffer layer over the substrate, disposing a threshold voltage shift layer over the buffer layer to a predetermined thickness, masking the threshold voltage shift layer with an etch mask to define a first device stack location, etching through the threshold voltage shift layer not masked by the etch mask to create an exposed portion of the buffer layer, removing the etch mask to expose a non-etched portion of the threshold voltage shift layer, disposing a channel layer over the exposed portion of the buffer layer and the non-etched portion of the threshold voltage shift layer

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
threshold voltage shift (delta Vt) range from Figure 3	-1–1.25	threshold voltage shift layer semiconductor material (higher bandgap)
Voltage

Why these are connected

Related documents with shared materials, methods, properties, or citations.

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