A direct drive D-mode half-bridge power module comprising a high-side switch and a low-side switch con-nected in series, wherein the high-side switch is a D-mode normally-on GaN transistor switch (Q₁) in series with an E-mode normally-off Si MOSFET switch (M₁) and the low-side switch is a D-mode normally-on GaN transistor switch (Q₂), wherein gates of the D-mode normally-on GaN transistor switches Q₁ and Q₂ are directly driven, and the gate of E-mode normally-off Si MOSFET M₁ is directly driven by a control signal, wherein M₁ acts as a protection FET to hold the high-side switch in an off-state during start-up and during a fault condition.

A power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein: the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q₁) is con-nected in series with a normally-off Si MOSFET switch (M₁), the source of Q₁ being connected to the drain of M1; the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q₂); wherein gates of the D-mode normally-on GaN transistor switches Q₁ or Q₂ are directly driven, and the gate of the E-mode normally-off Si MOSFET M₁ is directly driven by a control circuit, wherein M₁ acts as a protection FET to hold the high-side switch in an off-state during start-up and during a fault condition; and the control circuit is configured to determine an opera-tional mode of M₁ responsive to an undervoltage lock-out (UVLO) signal and a voltage sense signal indicative of an overcurrent event, the control circuit operating so that: M₁ is OFF during start-up until UVLO is off; M₁ is ON for normal operation; M₁ is turned-off during a fault condition if UVLO is turned-on; and if overcurrent protection (OCP) is triggered, M₁ is ON and Q₁ and Q₂ are turned-off.

A power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q₁) is con-nected in series with a normally-off Si MOSFET switch (M₁), the source of Q₁ being connected to the drain of M1; the low side switch is a normally-on switch, comprising a second normally-on GaN transitory switch (Q₂); and Q₁ has a source, a drain and a gate, wherein the drain of Q₁ is connected to the high voltage DC bus and the source of Q₁ is connected to a drain of M1, and the gate of Q₁ is connected to a first gate drive terminal for directly driving the gate of Q1; the source of M₁ is connected to the switching node, a gate of M₁ is connected to an enable (control) terminal for directly driving the gate of the M1; a high-side ground terminal is connected to the source of M1; and a voltage sense B₂ terminal is connected to a common point between the source of Q₁ and the drain of M1; and Q₂ has a source, a drain and a gate, the drain of Q₂ is connected to the switching node and the source of Q₂ is connected to the low voltage DC bus, and the gate of Q₂ is connected to a second gate drive terminal for directly driving the gate of Q2; and a low-side ground terminal is connected to the source of Q2.

A power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein: the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q₁) is con-nected in series with a normally-off Si MOSFET switch (M₁), the source of Q₁ being connected to the drain of M1; and the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q₂); and a half-bridge driver circuit comprising: a high-side driver for directly driving a gate of Q1; a low-side driver for directly driving a gate of Q2; wherein the high-side driver and the low-side driver are driven by PWM input signals INH and INL respec-tively; and a control circuit for driving M1, wherein the control circuit comprises a gate driver for providing an enable (control) signal for directly driving the gate of M₁ in response to a gate input signal PGOOD, the control circuit having a voltage sense input Vsen from a voltage sense terminal connected to a node between the source of Q₁ and the drain of M1, circuitry for receiving an undervoltage lock-out (UVLO) signal, and determining a power status and operational mode for M1, circuitry for comparing the voltage sense input Vsen to a reference overcurrent protection (OCP) limit volt-age VOCP_limit, wherein said enable signal provides that M₁ is OFF during start-up until UVLO is off; M₁ is ON for normal operation; M₁ is turned-off during a fault condition if UVLO is turned-on; and if OCP is triggered, M₁ is ON and Q₁ and Q₂ are turned-off.

A direct drive D-mode half-bridge power module comprising a high-side switch and a low-side switch con-nected in series, wherein the high-side switch is a D-mode normally-on GaN transistor switch (Q₁) in series with an E-mode normally-off Si MOSFET switch (M₁) and the low-side switch is a D-mode normally-on GaN transistor switch (Q₂), wherein gates of the D-mode normally-on GaN transistor switches Q₁ and Q₂ are directly driven, and the gate of E-mode normally-off Si MOSFET M₁ is directly driven by a control signal, wherein M₁ acts as a protection FET to hold the high-side switch in an off-state during start-up and during a fault condition.

A power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein: the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q₁) is con-nected in series with a normally-off Si MOSFET switch (M₁), the source of Q₁ being connected to the drain of M1; the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q₂); wherein gates of the D-mode normally-on GaN transistor switches Q₁ or Q₂ are directly driven, and the gate of the E-mode normally-off Si MOSFET M₁ is directly driven by a control circuit, wherein M₁ acts as a protection FET to hold the high-side switch in an off-state during start-up and during a fault condition; and the control circuit is configured to determine an opera-tional mode of M₁ responsive to an undervoltage lock-out (UVLO) signal and a voltage sense signal indicative of an overcurrent event, the control circuit operating so that: M₁ is OFF during start-up until UVLO is off; M₁ is ON for normal operation; M₁ is turned-off during a fault condition if UVLO is turned-on; and if overcurrent protection (OCP) is triggered, M₁ is ON and Q₁ and Q₂ are turned-off.

A power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q₁) is con-nected in series with a normally-off Si MOSFET switch (M₁), the source of Q₁ being connected to the drain of M1; the low side switch is a normally-on switch, comprising a second normally-on GaN transitory switch (Q₂); and Q₁ has a source, a drain and a gate, wherein the drain of Q₁ is connected to the high voltage DC bus and the source of Q₁ is connected to a drain of M1, and the gate of Q₁ is connected to a first gate drive terminal for directly driving the gate of Q1; the source of M₁ is connected to the switching node, a gate of M₁ is connected to an enable (control) terminal for directly driving the gate of the M1; a high-side ground terminal is connected to the source of M1; and a voltage sense B₂ terminal is connected to a common point between the source of Q₁ and the drain of M1; and Q₂ has a source, a drain and a gate, the drain of Q₂ is connected to the switching node and the source of Q₂ is connected to the low voltage DC bus, and the gate of Q₂ is connected to a second gate drive terminal for directly driving the gate of Q2; and a low-side ground terminal is connected to the source of Q2.

A power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein: the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q₁) is con-nected in series with a normally-off Si MOSFET switch (M₁), the source of Q₁ being connected to the drain of M1; and the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q₂); and a half-bridge driver circuit comprising: a high-side driver for directly driving a gate of Q1; a low-side driver for directly driving a gate of Q2; wherein the high-side driver and the low-side driver are driven by PWM input signals INH and INL respec-tively; and a control circuit for driving M1, wherein the control circuit comprises a gate driver for providing an enable (control) signal for directly driving the gate of M₁ in response to a gate input signal PGOOD, the control circuit having a voltage sense input Vsen from a voltage sense terminal connected to a node between the source of Q₁ and the drain of M1, circuitry for receiving an undervoltage lock-out (UVLO) signal, and determining a power status and operational mode for M1, circuitry for comparing the voltage sense input Vsen to a reference overcurrent protection (OCP) limit volt-age VOCP_limit, wherein said enable signal provides that M₁ is OFF during start-up until UVLO is off; M₁ is ON for normal operation; M₁ is turned-off during a fault condition if UVLO is turned-on; and if OCP is triggered, M₁ is ON and Q₁ and Q₂ are turned-off.

A direct drive D-mode half-bridge power module comprising a high-side switch and a low-side switch con-nected in series, wherein the high-side switch is a D-mode normally-on GaN transistor switch (Q₁) in series with an E-mode normally-off Si MOSFET switch (M₁) and the low-side switch is a D-mode normally-on GaN transistor switch (Q₂), wherein gates of the D-mode normally-on GaN transistor switches Q₁ and Q₂ are directly driven, and the gate of E-mode normally-off Si MOSFET M₁ is directly driven by a control signal, wherein M₁ acts as a protection FET to hold the high-side switch in an off-state during start-up and during a fault condition.

A power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein: the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q₁) is con-nected in series with a normally-off Si MOSFET switch (M₁), the source of Q₁ being connected to the drain of M1; the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q₂); wherein gates of the D-mode normally-on GaN transistor switches Q₁ or Q₂ are directly driven, and the gate of the E-mode normally-off Si MOSFET M₁ is directly driven by a control circuit, wherein M₁ acts as a protection FET to hold the high-side switch in an off-state during start-up and during a fault condition; and the control circuit is configured to determine an opera-tional mode of M₁ responsive to an undervoltage lock-out (UVLO) signal and a voltage sense signal indicative of an overcurrent event, the control circuit operating so that: M₁ is OFF during start-up until UVLO is off; M₁ is ON for normal operation; M₁ is turned-off during a fault condition if UVLO is turned-on; and if overcurrent protection (OCP) is triggered, M₁ is ON and Q₁ and Q₂ are turned-off.

A power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q₁) is con-nected in series with a normally-off Si MOSFET switch (M₁), the source of Q₁ being connected to the drain of M1; the low side switch is a normally-on switch, comprising a second normally-on GaN transitory switch (Q₂); and Q₁ has a source, a drain and a gate, wherein the drain of Q₁ is connected to the high voltage DC bus and the source of Q₁ is connected to a drain of M1, and the gate of Q₁ is connected to a first gate drive terminal for directly driving the gate of Q1; the source of M₁ is connected to the switching node, a gate of M₁ is connected to an enable (control) terminal for directly driving the gate of the M1; a high-side ground terminal is connected to the source of M1; and a voltage sense B₂ terminal is connected to a common point between the source of Q₁ and the drain of M1; and Q₂ has a source, a drain and a gate, the drain of Q₂ is connected to the switching node and the source of Q₂ is connected to the low voltage DC bus, and the gate of Q₂ is connected to a second gate drive terminal for directly driving the gate of Q2; and a low-side ground terminal is connected to the source of Q2.

A power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein: the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q₁) is con-nected in series with a normally-off Si MOSFET switch (M₁), the source of Q₁ being connected to the drain of M1; and the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q₂); and a half-bridge driver circuit comprising: a high-side driver for directly driving a gate of Q1; a low-side driver for directly driving a gate of Q2; wherein the high-side driver and the low-side driver are driven by PWM input signals INH and INL respec-tively; and a control circuit for driving M1, wherein the control circuit comprises a gate driver for providing an enable (control) signal for directly driving the gate of M₁ in response to a gate input signal PGOOD, the control circuit having a voltage sense input Vsen from a voltage sense terminal connected to a node between the source of Q₁ and the drain of M1, circuitry for receiving an undervoltage lock-out (UVLO) signal, and determining a power status and operational mode for M1, circuitry for comparing the voltage sense input Vsen to a reference overcurrent protection (OCP) limit volt-age VOCP_limit, wherein said enable signal provides that M₁ is OFF during start-up until UVLO is off; M₁ is ON for normal operation; M₁ is turned-off during a fault condition if UVLO is turned-on; and if OCP is triggered, M₁ is ON and Q₁ and Q₂ are turned-off.

A direct drive D-mode half-bridge power module comprising a high-side switch and a low-side switch con-nected in series, wherein the high-side switch is a D-mode normally-on GaN transistor switch (Q₁) in series with an E-mode normally-off Si MOSFET switch (M₁) and the low-side switch is a D-mode normally-on GaN transistor switch (Q₂), wherein gates of the D-mode normally-on GaN transistor switches Q₁ and Q₂ are directly driven, and the gate of E-mode normally-off Si MOSFET M₁ is directly driven by a control signal, wherein M₁ acts as a protection FET to hold the high-side switch in an off-state during start-up and during a fault condition.

A power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein: the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q₁) is con-nected in series with a normally-off Si MOSFET switch (M₁), the source of Q₁ being connected to the drain of M1; the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q₂); wherein gates of the D-mode normally-on GaN transistor switches Q₁ or Q₂ are directly driven, and the gate of the E-mode normally-off Si MOSFET M₁ is directly driven by a control circuit, wherein M₁ acts as a protection FET to hold the high-side switch in an off-state during start-up and during a fault condition; and the control circuit is configured to determine an opera-tional mode of M₁ responsive to an undervoltage lock-out (UVLO) signal and a voltage sense signal indicative of an overcurrent event, the control circuit operating so that: M₁ is OFF during start-up until UVLO is off; M₁ is ON for normal operation; M₁ is turned-off during a fault condition if UVLO is turned-on; and if overcurrent protection (OCP) is triggered, M₁ is ON and Q₁ and Q₂ are turned-off.

A power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q₁) is con-nected in series with a normally-off Si MOSFET switch (M₁), the source of Q₁ being connected to the drain of M1; the low side switch is a normally-on switch, comprising a second normally-on GaN transitory switch (Q₂); and Q₁ has a source, a drain and a gate, wherein the drain of Q₁ is connected to the high voltage DC bus and the source of Q₁ is connected to a drain of M1, and the gate of Q₁ is connected to a first gate drive terminal for directly driving the gate of Q1; the source of M₁ is connected to the switching node, a gate of M₁ is connected to an enable (control) terminal for directly driving the gate of the M1; a high-side ground terminal is connected to the source of M1; and a voltage sense B₂ terminal is connected to a common point between the source of Q₁ and the drain of M1; and Q₂ has a source, a drain and a gate, the drain of Q₂ is connected to the switching node and the source of Q₂ is connected to the low voltage DC bus, and the gate of Q₂ is connected to a second gate drive terminal for directly driving the gate of Q2; and a low-side ground terminal is connected to the source of Q2.

A power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein: the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q₁) is con-nected in series with a normally-off Si MOSFET switch (M₁), the source of Q₁ being connected to the drain of M1; and the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q₂); and a half-bridge driver circuit comprising: a high-side driver for directly driving a gate of Q1; a low-side driver for directly driving a gate of Q2; wherein the high-side driver and the low-side driver are driven by PWM input signals INH and INL respec-tively; and a control circuit for driving M1, wherein the control circuit comprises a gate driver for providing an enable (control) signal for directly driving the gate of M₁ in response to a gate input signal PGOOD, the control circuit having a voltage sense input Vsen from a voltage sense terminal connected to a node between the source of Q₁ and the drain of M1, circuitry for receiving an undervoltage lock-out (UVLO) signal, and determining a power status and operational mode for M1, circuitry for comparing the voltage sense input Vsen to a reference overcurrent protection (OCP) limit volt-age VOCP_limit, wherein said enable signal provides that M₁ is OFF during start-up until UVLO is off; M₁ is ON for normal operation; M₁ is turned-off during a fault condition if UVLO is turned-on; and if OCP is triggered, M₁ is ON and Q₁ and Q₂ are turned-off.