Patent
A LOW GATE-LEAKAGE STRUCTURE AND METHOD FOR GALLIUM NITRIDE ENHANCEMENT MODE TRANSISTOR
Alexander Kalnitsky
Copyright © 2026 Matter42. All rights reserved.
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Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (A I GaN) layer disposed on the GaN layer; and a gate stack disposed on the A l GaN layer, wherein the gate stack includes: a pair of layers forming a diode, wherein the pair of layers includes: a Gr oup III -V compound n-type doped layer; and a Gr oup III -V compound p-type doped layer adjacent the Gr oup III-V compound n-type doped layer; a nd a metal layer formed over the pair of la v ers and a first dielectric layer interposing the pair of layers and the metal la yer; wherein the Group III -V compound n-type doped layer, the Gr oup III-V compound p-type doped layer, and the metal layer have substantially co-planar sidewal ls. currently amended
The semiconductor structure of claim 1, wherein the gate stack further includes a second dielectric layer underlying the metal layer and underl yin g the pair of la yers,, laye r.
The semiconductor structure of claim 1, further comprising another pair of Grou p III -V compound doped layers.
The semiconductor structure of claim 1, wherein the Grou p III -V compound n-type doped layer includes a n-type GaN layer and the Gr ou p I II -V compound p-type doped layer includes a p-type GaN layer. 2 SVG 13049699.05-05-2014.HUUBEM₁KPXXIFW3.CLM23868109.2.295.142.2225.230.svg 0.293 6.433 Chemistry Black and white
The semiconductor structure of claim 1, wherein each of the Gr ou p I II -V compound p-type doped layer and the Group III -V compound n-type doped layer has a thickness ranging between about 1 nanometer and about 100 nanometers.
The semiconductor structure of claim 1, wherein the GaN layer is undoped or unintentionally doped.
canceled
An enhancement-mode transistor comprising: a first Gr oup III -V compound layer on a substrate; a second Group I II -V compound layer directly on the first Group I II -V compound layer and different from the first Group I II -V compound layer in composition; and a gate stack on the second Grou p III -V compound layer, the gate stack including; a pair of a n-type doped Group I II -V compound layer and a fir st p-type doped Group I II -V compound layer configured as a first diode, a second p-t yp e doped Group I II -V compound la ye r disposed under the n-t ype doped Group I II -V compound layer, wherein the n-type doped Group I II -V compound layer directly interfaces the second p-type doped Group I II -V compound layer and wherein the second p-type doped Group I II -V compound layer is configured as a second diode with the second Group I II -V compound la yer; and 3 SVG 13049699.05-05-2014.HUUBEM₁KPXXIFW3.CLM23868110.2.294.145.2225.232.svg 0.29 6.437 Chemistry Black and white a metal la ye r disposed on the first p-type doped Group III -V compound layer, wherein no additional Group III -V compound layer interposes the metal layer and the first p-type doped Group III -V compound layer; and wherein the Ill-V eempound n-type doped Group III -V compound layer and the 11-V eempeund first p-type doped Group III -V compound layer have substantially co-planar sidewalls.
The enhancement-mode transistor of claim 11, wherein the substrate includes one of a sapphire substrate, a silicon substrate, and a silicon carbide substrate; the first Grou p III -V compound layer includes a gallium nitride (GaN) layer; and the second Gr oup III -V compound layer includes an aluminum gallium nitride (A l GaN) layer.
The enhancement-mode transistor of claim 11, further comprising an aluminum nitride (A l N) layer interposed between the first and second Group III-V compound layers.
The enhancement-mode transistor of claim 11, further comprising a source and drain feature interposed by the gate stack, wherein the source and drain feature includes a metal selected from the group consisting of titanium, aluminum, nickel, and gold. 19-23
The enhancement-mode transistor of claim [[1 3]] 12, wherein the metal layer has an Ohmic contact with the pair of the n-type doped Group III-V compound layer and the first p-type doped Gr oup III -V compound layer by implementing a thermal annealing process.
canceled
canceled
canceled
canceled
canceled
A semiconductor structure comprising: a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (A l GaN) layer disposed on the GaN layer; a barrier layer disposed on the GaN layer; and a gate stack disposed on the barrier layer, wherein the gate stack includes: a Gr ou p I II -V compound n-type doped layer; a Gr oup III -V compound p-type doped layer adjacent the Gr oup III -V compound n-type doped layer; a dielectric la ye r disposed on the Group III -V compound p-type doped la yer; and a metal layer formed over the Gr oup III -V compound p-type doped layer and the Grou p I II -V compound n-type doped layer.
The semiconductor structure of claim 24, wherein the Group I II -V compound p-type doped layer and the A l GaN layer form a first diode; and wherein the Group III-V compound p-type doped layer and the Group I II -V compound n-type doped layer form a second diode.
Layer stacks claimed or described, ordered top of device to substrate.
GaN enhancement-mode transistor (gate stack with p-n diode isolation)
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
aluminum gallium nitride (AlGaN) layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness Range | 0.5–10 micron | GaN |
Thickness Range | 5–50 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (A I GaN) layer disposed on the GaN layer; and a gate stack disposed on the A l GaN layer, wherein the gate stack includes: a pair of layers forming a diode, wherein the pair of layers includes: a Gr oup III -V compound n-type doped layer; and a Gr oup III -V compound p-type doped layer adjacent the Gr oup III-V compound n-type doped layer; a nd a metal layer formed over the pair of la v ers and a first dielectric layer interposing the pair of layers and the metal la yer; wherein the Group III -V compound n-type doped layer, the Gr oup III-V compound p-type doped layer, and the metal layer have substantially co-planar sidewal ls. currently amended
The semiconductor structure of claim 1, wherein the gate stack further includes a second dielectric layer underlying the metal layer and underl yin g the pair of la yers,, laye r.
The semiconductor structure of claim 1, further comprising another pair of Grou p III -V compound doped layers.
The semiconductor structure of claim 1, wherein the Grou p III -V compound n-type doped layer includes a n-type GaN layer and the Gr ou p I II -V compound p-type doped layer includes a p-type GaN layer. 2 SVG 13049699.05-05-2014.HUUBEM₁KPXXIFW3.CLM23868109.2.295.142.2225.230.svg 0.293 6.433 Chemistry Black and white
The semiconductor structure of claim 1, wherein each of the Gr ou p I II -V compound p-type doped layer and the Group III -V compound n-type doped layer has a thickness ranging between about 1 nanometer and about 100 nanometers.
The semiconductor structure of claim 1, wherein the GaN layer is undoped or unintentionally doped.
canceled
An enhancement-mode transistor comprising: a first Gr oup III -V compound layer on a substrate; a second Group I II -V compound layer directly on the first Group I II -V compound layer and different from the first Group I II -V compound layer in composition; and a gate stack on the second Grou p III -V compound layer, the gate stack including; a pair of a n-type doped Group I II -V compound layer and a fir st p-type doped Group I II -V compound layer configured as a first diode, a second p-t yp e doped Group I II -V compound la ye r disposed under the n-t ype doped Group I II -V compound layer, wherein the n-type doped Group I II -V compound layer directly interfaces the second p-type doped Group I II -V compound layer and wherein the second p-type doped Group I II -V compound layer is configured as a second diode with the second Group I II -V compound la yer; and 3 SVG 13049699.05-05-2014.HUUBEM₁KPXXIFW3.CLM23868110.2.294.145.2225.232.svg 0.29 6.437 Chemistry Black and white a metal la ye r disposed on the first p-type doped Group III -V compound layer, wherein no additional Group III -V compound layer interposes the metal layer and the first p-type doped Group III -V compound layer; and wherein the Ill-V eempound n-type doped Group III -V compound layer and the 11-V eempeund first p-type doped Group III -V compound layer have substantially co-planar sidewalls.
The enhancement-mode transistor of claim 11, wherein the substrate includes one of a sapphire substrate, a silicon substrate, and a silicon carbide substrate; the first Grou p III -V compound layer includes a gallium nitride (GaN) layer; and the second Gr oup III -V compound layer includes an aluminum gallium nitride (A l GaN) layer.
The enhancement-mode transistor of claim 11, further comprising an aluminum nitride (A l N) layer interposed between the first and second Group III-V compound layers.
The enhancement-mode transistor of claim 11, further comprising a source and drain feature interposed by the gate stack, wherein the source and drain feature includes a metal selected from the group consisting of titanium, aluminum, nickel, and gold. 19-23
The enhancement-mode transistor of claim [[1 3]] 12, wherein the metal layer has an Ohmic contact with the pair of the n-type doped Group III-V compound layer and the first p-type doped Gr oup III -V compound layer by implementing a thermal annealing process.
canceled
canceled
canceled
canceled
canceled
A semiconductor structure comprising: a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (A l GaN) layer disposed on the GaN layer; a barrier layer disposed on the GaN layer; and a gate stack disposed on the barrier layer, wherein the gate stack includes: a Gr ou p I II -V compound n-type doped layer; a Gr oup III -V compound p-type doped layer adjacent the Gr oup III -V compound n-type doped layer; a dielectric la ye r disposed on the Group III -V compound p-type doped la yer; and a metal layer formed over the Gr oup III -V compound p-type doped layer and the Grou p I II -V compound n-type doped layer.
The semiconductor structure of claim 24, wherein the Group I II -V compound p-type doped layer and the A l GaN layer form a first diode; and wherein the Group III-V compound p-type doped layer and the Group I II -V compound n-type doped layer form a second diode.
Layer stacks claimed or described, ordered top of device to substrate.
GaN enhancement-mode transistor (gate stack with p-n diode isolation)
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
aluminum gallium nitride (AlGaN) layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness Range | 0.5–10 micron | GaN |
Thickness Range | 5–50 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (A I GaN) layer disposed on the GaN layer; and a gate stack disposed on the A l GaN layer, wherein the gate stack includes: a pair of layers forming a diode, wherein the pair of layers includes: a Gr oup III -V compound n-type doped layer; and a Gr oup III -V compound p-type doped layer adjacent the Gr oup III-V compound n-type doped layer; a nd a metal layer formed over the pair of la v ers and a first dielectric layer interposing the pair of layers and the metal la yer; wherein the Group III -V compound n-type doped layer, the Gr oup III-V compound p-type doped layer, and the metal layer have substantially co-planar sidewal ls. currently amended
The semiconductor structure of claim 1, wherein the gate stack further includes a second dielectric layer underlying the metal layer and underl yin g the pair of la yers,, laye r.
The semiconductor structure of claim 1, further comprising another pair of Grou p III -V compound doped layers.
The semiconductor structure of claim 1, wherein the Grou p III -V compound n-type doped layer includes a n-type GaN layer and the Gr ou p I II -V compound p-type doped layer includes a p-type GaN layer. 2 SVG 13049699.05-05-2014.HUUBEM₁KPXXIFW3.CLM23868109.2.295.142.2225.230.svg 0.293 6.433 Chemistry Black and white
The semiconductor structure of claim 1, wherein each of the Gr ou p I II -V compound p-type doped layer and the Group III -V compound n-type doped layer has a thickness ranging between about 1 nanometer and about 100 nanometers.
The semiconductor structure of claim 1, wherein the GaN layer is undoped or unintentionally doped.
canceled
An enhancement-mode transistor comprising: a first Gr oup III -V compound layer on a substrate; a second Group I II -V compound layer directly on the first Group I II -V compound layer and different from the first Group I II -V compound layer in composition; and a gate stack on the second Grou p III -V compound layer, the gate stack including; a pair of a n-type doped Group I II -V compound layer and a fir st p-type doped Group I II -V compound layer configured as a first diode, a second p-t yp e doped Group I II -V compound la ye r disposed under the n-t ype doped Group I II -V compound layer, wherein the n-type doped Group I II -V compound layer directly interfaces the second p-type doped Group I II -V compound layer and wherein the second p-type doped Group I II -V compound layer is configured as a second diode with the second Group I II -V compound la yer; and 3 SVG 13049699.05-05-2014.HUUBEM₁KPXXIFW3.CLM23868110.2.294.145.2225.232.svg 0.29 6.437 Chemistry Black and white a metal la ye r disposed on the first p-type doped Group III -V compound layer, wherein no additional Group III -V compound layer interposes the metal layer and the first p-type doped Group III -V compound layer; and wherein the Ill-V eempound n-type doped Group III -V compound layer and the 11-V eempeund first p-type doped Group III -V compound layer have substantially co-planar sidewalls.
The enhancement-mode transistor of claim 11, wherein the substrate includes one of a sapphire substrate, a silicon substrate, and a silicon carbide substrate; the first Grou p III -V compound layer includes a gallium nitride (GaN) layer; and the second Gr oup III -V compound layer includes an aluminum gallium nitride (A l GaN) layer.
The enhancement-mode transistor of claim 11, further comprising an aluminum nitride (A l N) layer interposed between the first and second Group III-V compound layers.
The enhancement-mode transistor of claim 11, further comprising a source and drain feature interposed by the gate stack, wherein the source and drain feature includes a metal selected from the group consisting of titanium, aluminum, nickel, and gold. 19-23
The enhancement-mode transistor of claim [[1 3]] 12, wherein the metal layer has an Ohmic contact with the pair of the n-type doped Group III-V compound layer and the first p-type doped Gr oup III -V compound layer by implementing a thermal annealing process.
canceled
canceled
canceled
canceled
canceled
A semiconductor structure comprising: a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (A l GaN) layer disposed on the GaN layer; a barrier layer disposed on the GaN layer; and a gate stack disposed on the barrier layer, wherein the gate stack includes: a Gr ou p I II -V compound n-type doped layer; a Gr oup III -V compound p-type doped layer adjacent the Gr oup III -V compound n-type doped layer; a dielectric la ye r disposed on the Group III -V compound p-type doped la yer; and a metal layer formed over the Gr oup III -V compound p-type doped layer and the Grou p I II -V compound n-type doped layer.
The semiconductor structure of claim 24, wherein the Group I II -V compound p-type doped layer and the A l GaN layer form a first diode; and wherein the Group III-V compound p-type doped layer and the Group I II -V compound n-type doped layer form a second diode.
Layer stacks claimed or described, ordered top of device to substrate.
GaN enhancement-mode transistor (gate stack with p-n diode isolation)
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
aluminum gallium nitride (AlGaN) layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness Range | 0.5–10 micron | GaN |
Thickness Range | 5–50 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (A I GaN) layer disposed on the GaN layer; and a gate stack disposed on the A l GaN layer, wherein the gate stack includes: a pair of layers forming a diode, wherein the pair of layers includes: a Gr oup III -V compound n-type doped layer; and a Gr oup III -V compound p-type doped layer adjacent the Gr oup III-V compound n-type doped layer; a nd a metal layer formed over the pair of la v ers and a first dielectric layer interposing the pair of layers and the metal la yer; wherein the Group III -V compound n-type doped layer, the Gr oup III-V compound p-type doped layer, and the metal layer have substantially co-planar sidewal ls. currently amended
The semiconductor structure of claim 1, wherein the gate stack further includes a second dielectric layer underlying the metal layer and underl yin g the pair of la yers,, laye r.
The semiconductor structure of claim 1, further comprising another pair of Grou p III -V compound doped layers.
The semiconductor structure of claim 1, wherein the Grou p III -V compound n-type doped layer includes a n-type GaN layer and the Gr ou p I II -V compound p-type doped layer includes a p-type GaN layer. 2 SVG 13049699.05-05-2014.HUUBEM₁KPXXIFW3.CLM23868109.2.295.142.2225.230.svg 0.293 6.433 Chemistry Black and white
The semiconductor structure of claim 1, wherein each of the Gr ou p I II -V compound p-type doped layer and the Group III -V compound n-type doped layer has a thickness ranging between about 1 nanometer and about 100 nanometers.
The semiconductor structure of claim 1, wherein the GaN layer is undoped or unintentionally doped.
canceled
An enhancement-mode transistor comprising: a first Gr oup III -V compound layer on a substrate; a second Group I II -V compound layer directly on the first Group I II -V compound layer and different from the first Group I II -V compound layer in composition; and a gate stack on the second Grou p III -V compound layer, the gate stack including; a pair of a n-type doped Group I II -V compound layer and a fir st p-type doped Group I II -V compound layer configured as a first diode, a second p-t yp e doped Group I II -V compound la ye r disposed under the n-t ype doped Group I II -V compound layer, wherein the n-type doped Group I II -V compound layer directly interfaces the second p-type doped Group I II -V compound layer and wherein the second p-type doped Group I II -V compound layer is configured as a second diode with the second Group I II -V compound la yer; and 3 SVG 13049699.05-05-2014.HUUBEM₁KPXXIFW3.CLM23868110.2.294.145.2225.232.svg 0.29 6.437 Chemistry Black and white a metal la ye r disposed on the first p-type doped Group III -V compound layer, wherein no additional Group III -V compound layer interposes the metal layer and the first p-type doped Group III -V compound layer; and wherein the Ill-V eempound n-type doped Group III -V compound layer and the 11-V eempeund first p-type doped Group III -V compound layer have substantially co-planar sidewalls.
The enhancement-mode transistor of claim 11, wherein the substrate includes one of a sapphire substrate, a silicon substrate, and a silicon carbide substrate; the first Grou p III -V compound layer includes a gallium nitride (GaN) layer; and the second Gr oup III -V compound layer includes an aluminum gallium nitride (A l GaN) layer.
The enhancement-mode transistor of claim 11, further comprising an aluminum nitride (A l N) layer interposed between the first and second Group III-V compound layers.
The enhancement-mode transistor of claim 11, further comprising a source and drain feature interposed by the gate stack, wherein the source and drain feature includes a metal selected from the group consisting of titanium, aluminum, nickel, and gold. 19-23
The enhancement-mode transistor of claim [[1 3]] 12, wherein the metal layer has an Ohmic contact with the pair of the n-type doped Group III-V compound layer and the first p-type doped Gr oup III -V compound layer by implementing a thermal annealing process.
canceled
canceled
canceled
canceled
canceled
A semiconductor structure comprising: a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (A l GaN) layer disposed on the GaN layer; a barrier layer disposed on the GaN layer; and a gate stack disposed on the barrier layer, wherein the gate stack includes: a Gr ou p I II -V compound n-type doped layer; a Gr oup III -V compound p-type doped layer adjacent the Gr oup III -V compound n-type doped layer; a dielectric la ye r disposed on the Group III -V compound p-type doped la yer; and a metal layer formed over the Gr oup III -V compound p-type doped layer and the Grou p I II -V compound n-type doped layer.
The semiconductor structure of claim 24, wherein the Group I II -V compound p-type doped layer and the A l GaN layer form a first diode; and wherein the Group III-V compound p-type doped layer and the Group I II -V compound n-type doped layer form a second diode.
Layer stacks claimed or described, ordered top of device to substrate.
GaN enhancement-mode transistor (gate stack with p-n diode isolation)
Materials described outside the worked examples.
gallium nitride (GaN) layer
GaN
aluminum gallium nitride (AlGaN) layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness Range | 0.5–10 micron | GaN |
Thickness Range | 5–50 nm |
Related documents with shared materials, methods, properties, or citations.
Enhancement-mode transistor with dual-diode gate stack
Semiconductor structure with barrier layer and gate stack (claim 24)
Group III-V compound n-type doped layer (n-GaN)
GaN:n
Group III-V compound p-type doped layer (p-GaN)
GaN:p
metal layer (gate electrode)
dielectric layer (insulating material layer)
first Group III-V compound layer (buffer layer)
second Group III-V compound layer (barrier layer)
n-type doped Group III-V compound layer
first p-type doped Group III-V compound layer
sapphire substrate
silicon substrate
Si
silicon carbide substrate
SiC
aluminum nitride (AlN) layer
AlN
source and drain metal (Ti, Al, Ni, Au)
Thickness Range | 1–100 nm | GaN:n |
Thickness Range | 1–100 nm | GaN:p |
Thickness | 0.5–10 µm | — |
Thickness | 3–100 nm | — |
Enhancement-mode transistor with dual-diode gate stack
Semiconductor structure with barrier layer and gate stack (claim 24)
Group III-V compound n-type doped layer (n-GaN)
GaN:n
Group III-V compound p-type doped layer (p-GaN)
GaN:p
metal layer (gate electrode)
dielectric layer (insulating material layer)
first Group III-V compound layer (buffer layer)
second Group III-V compound layer (barrier layer)
n-type doped Group III-V compound layer
first p-type doped Group III-V compound layer
sapphire substrate
silicon substrate
Si
silicon carbide substrate
SiC
aluminum nitride (AlN) layer
AlN
source and drain metal (Ti, Al, Ni, Au)
Thickness Range | 1–100 nm | GaN:n |
Thickness Range | 1–100 nm | GaN:p |
Thickness | 0.5–10 µm | — |
Thickness | 3–100 nm | — |
Enhancement-mode transistor with dual-diode gate stack
Semiconductor structure with barrier layer and gate stack (claim 24)
Group III-V compound n-type doped layer (n-GaN)
GaN:n
Group III-V compound p-type doped layer (p-GaN)
GaN:p
metal layer (gate electrode)
dielectric layer (insulating material layer)
first Group III-V compound layer (buffer layer)
second Group III-V compound layer (barrier layer)
n-type doped Group III-V compound layer
first p-type doped Group III-V compound layer
sapphire substrate
silicon substrate
Si
silicon carbide substrate
SiC
aluminum nitride (AlN) layer
AlN
source and drain metal (Ti, Al, Ni, Au)
Thickness Range | 1–100 nm | GaN:n |
Thickness Range | 1–100 nm | GaN:p |
Thickness | 0.5–10 µm | — |
Thickness | 3–100 nm | — |
Enhancement-mode transistor with dual-diode gate stack
Semiconductor structure with barrier layer and gate stack (claim 24)
Group III-V compound n-type doped layer (n-GaN)
GaN:n
Group III-V compound p-type doped layer (p-GaN)
GaN:p
metal layer (gate electrode)
dielectric layer (insulating material layer)
first Group III-V compound layer (buffer layer)
second Group III-V compound layer (barrier layer)
n-type doped Group III-V compound layer
first p-type doped Group III-V compound layer
sapphire substrate
silicon substrate
Si
silicon carbide substrate
SiC
aluminum nitride (AlN) layer
AlN
source and drain metal (Ti, Al, Ni, Au)
Thickness Range | 1–100 nm | GaN:n |
Thickness Range | 1–100 nm | GaN:p |
Thickness | 0.5–10 µm | — |
Thickness | 3–100 nm | — |