Patent
Atlas literature
Patent
US 12,501,604 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram for illustrating a negative transcon- ductance device according to one embodiment of the present disclosure.
FIG. 2 is a diagram and a circuit diagram for illustrating 20 a multi-valued memory device according to one embodi- ment of the present disclosure. (a) in
FIG. 3.
FIG. 4 is a diagram analyzing a WSe₂ surface charge transfer doping mechanism via density functional theory (DFT) calculation of WSe₂ DLHJ of one embodiment of …
FIG. 5 shows (a) a schematic diagram of a KPFM measurement method according to the present disclosure, 40 (b) transistor characteristics of n-i WSe₂ junction, …
FIG. 6 shows (a) a schematic diagram and a circuit configuration of a quaternary latch composed of a triple 50 NDR circuit that may be implemented via …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A negative transconductance device comprising: a monolithic WSe₂ semiconductor thin film forming a continuous channel layer; a first chemically doped layer formed in a first area of the WSe₂ semiconductor thin film, the first doped region configured to supply electrons to the first area; a second chemically doped layer formed in a second area of the WSe₂ semiconductor thin film, the second doped region configured to supply holes to the second area, wherein the second area is spaced apart from the first area along a lateral direction of the WSe₂ semiconduc-tor thin film; 60 a third area of the WSe₂ semiconductor thin film disposed between the first and second areas and remaining substantially intrinsic or undoped; a first electrode electrically connected to the first area of the WSe₂ semiconductor thin film; 65 a second electrode electrically connected to the second area of the WSe₂ semiconductor thin film; and B₂ a third electrode configured to apply a gate voltage simultaneously to the first area, the second area, and the third area to induce ambipolar carrier transport and generate negative transconductance behavior.
The negative transconductance device of claim 1, wherein the first chemically doped layer comprises CH₃ radicals as n-type dopants, and the second chemically doped layer comprises Au₂Cl₆ as p-type dopants.
The negative transconductance device of claim 1, wherein a poly (methyl methacrylate) (PMMA) coating layer is disposed on the third area of the WSe₂ semiconductor thin film to suppress unintentional doping and stabilize the intrinsic electrical properties of the third area.
The negative transconductance device of claim 1, wherein the device further comprises: a semiconductor substrate; and an insulating film disposed on a surface of the semiconductor substrate, wherein the WSe₂ semiconductor thin film is supported by the insulating film, and wherein the semiconductor substrate functions as a global back gate for applying the gate voltage to the first, second, and third areas of the WSe₂ semiconductor thin film.
A multi-valued memory device comprising: a monolithic WSe₂ semiconductor thin film forming a continuous channel layer; a first chemically doped layer disposed in a first area of the WSe₂ semiconductor thin film and configured to supply electrons to the first area; a second chemically doped layer disposed in a second area of the WSe₂ semiconductor thin film and config-ured to supply holes to the second area, wherein the second area is laterally spaced apart from the first area; a third area of the WSe₂ semiconductor thin film disposed between the first and second areas and having an intrinsic or undoped carrier profile; a first electrode electrically connected to the first area of the WSe₂ semiconductor thin film; a second electrode electrically connected to the second area of the WSe₂ semiconductor thin film; and a third electrode configured to apply a gate voltage to the first, second, and third areas of the WSe₂ semiconduc-tor thin film, wherein the device is configured to exhibit multiple stable current levels at the second electrode in response to different gate voltages applied to the third electrode, such that each current level represents a distinct logic state.
The multi-valued memory device of claim 6, wherein the first chemically doped layer includes CH₃ radicals as n-type dopants, and the second chemically doped layer includes Au₂Cl₆ as p-type dopants.
The multi-valued memory device of claim 6, wherein a poly (methyl methacrylate) (PMMA) coating layer is disposed on the third area of the WSe₂ semi13 14 conductor thin film to suppress unintentional doping and stabilize the intrinsic electrical properties of the third region.
The multi-valued memory device of claim 6, wherein the device further comprises: 5 a semiconductor substrate; and an insulating film disposed on a surface of the semiconductor substrate, wherein the WSe₂ semiconductor thin film is supported by the insulating film, and wherein the semiconductor substrate functions as a global back gate for applying the gate voltage to the first, second, and third areas of the WSe₂ semiconductor thin film. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
negative transconductance device (n-i-p double lateral homojunction)
multi-valued memory device (n-i-p double lateral homojunction)
Materials described outside the worked examples.
WSe₂ semiconductor thin film
WSe₂
first chemically doped layer (n-type)
Measurements and analyses referenced in the patent, with their drawing references.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Cited non-patent literature · 1
Patent
Atlas literature
Patent
US 12,501,604 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram for illustrating a negative transcon- ductance device according to one embodiment of the present disclosure.
FIG. 2 is a diagram and a circuit diagram for illustrating 20 a multi-valued memory device according to one embodi- ment of the present disclosure. (a) in
FIG. 3.
FIG. 4 is a diagram analyzing a WSe₂ surface charge transfer doping mechanism via density functional theory (DFT) calculation of WSe₂ DLHJ of one embodiment of …
FIG. 5 shows (a) a schematic diagram of a KPFM measurement method according to the present disclosure, 40 (b) transistor characteristics of n-i WSe₂ junction, …
FIG. 6 shows (a) a schematic diagram and a circuit configuration of a quaternary latch composed of a triple 50 NDR circuit that may be implemented via …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A negative transconductance device comprising: a monolithic WSe₂ semiconductor thin film forming a continuous channel layer; a first chemically doped layer formed in a first area of the WSe₂ semiconductor thin film, the first doped region configured to supply electrons to the first area; a second chemically doped layer formed in a second area of the WSe₂ semiconductor thin film, the second doped region configured to supply holes to the second area, wherein the second area is spaced apart from the first area along a lateral direction of the WSe₂ semiconduc-tor thin film; 60 a third area of the WSe₂ semiconductor thin film disposed between the first and second areas and remaining substantially intrinsic or undoped; a first electrode electrically connected to the first area of the WSe₂ semiconductor thin film; 65 a second electrode electrically connected to the second area of the WSe₂ semiconductor thin film; and B₂ a third electrode configured to apply a gate voltage simultaneously to the first area, the second area, and the third area to induce ambipolar carrier transport and generate negative transconductance behavior.
The negative transconductance device of claim 1, wherein the first chemically doped layer comprises CH₃ radicals as n-type dopants, and the second chemically doped layer comprises Au₂Cl₆ as p-type dopants.
The negative transconductance device of claim 1, wherein a poly (methyl methacrylate) (PMMA) coating layer is disposed on the third area of the WSe₂ semiconductor thin film to suppress unintentional doping and stabilize the intrinsic electrical properties of the third area.
The negative transconductance device of claim 1, wherein the device further comprises: a semiconductor substrate; and an insulating film disposed on a surface of the semiconductor substrate, wherein the WSe₂ semiconductor thin film is supported by the insulating film, and wherein the semiconductor substrate functions as a global back gate for applying the gate voltage to the first, second, and third areas of the WSe₂ semiconductor thin film.
A multi-valued memory device comprising: a monolithic WSe₂ semiconductor thin film forming a continuous channel layer; a first chemically doped layer disposed in a first area of the WSe₂ semiconductor thin film and configured to supply electrons to the first area; a second chemically doped layer disposed in a second area of the WSe₂ semiconductor thin film and config-ured to supply holes to the second area, wherein the second area is laterally spaced apart from the first area; a third area of the WSe₂ semiconductor thin film disposed between the first and second areas and having an intrinsic or undoped carrier profile; a first electrode electrically connected to the first area of the WSe₂ semiconductor thin film; a second electrode electrically connected to the second area of the WSe₂ semiconductor thin film; and a third electrode configured to apply a gate voltage to the first, second, and third areas of the WSe₂ semiconduc-tor thin film, wherein the device is configured to exhibit multiple stable current levels at the second electrode in response to different gate voltages applied to the third electrode, such that each current level represents a distinct logic state.
The multi-valued memory device of claim 6, wherein the first chemically doped layer includes CH₃ radicals as n-type dopants, and the second chemically doped layer includes Au₂Cl₆ as p-type dopants.
The multi-valued memory device of claim 6, wherein a poly (methyl methacrylate) (PMMA) coating layer is disposed on the third area of the WSe₂ semi13 14 conductor thin film to suppress unintentional doping and stabilize the intrinsic electrical properties of the third region.
The multi-valued memory device of claim 6, wherein the device further comprises: 5 a semiconductor substrate; and an insulating film disposed on a surface of the semiconductor substrate, wherein the WSe₂ semiconductor thin film is supported by the insulating film, and wherein the semiconductor substrate functions as a global back gate for applying the gate voltage to the first, second, and third areas of the WSe₂ semiconductor thin film. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
negative transconductance device (n-i-p double lateral homojunction)
multi-valued memory device (n-i-p double lateral homojunction)
Materials described outside the worked examples.
WSe₂ semiconductor thin film
WSe₂
first chemically doped layer (n-type)
Measurements and analyses referenced in the patent, with their drawing references.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Cited non-patent literature · 1
Patent
Atlas literature
Patent
US 12,501,604 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram for illustrating a negative transcon- ductance device according to one embodiment of the present disclosure.
FIG. 2 is a diagram and a circuit diagram for illustrating 20 a multi-valued memory device according to one embodi- ment of the present disclosure. (a) in
FIG. 3.
FIG. 4 is a diagram analyzing a WSe₂ surface charge transfer doping mechanism via density functional theory (DFT) calculation of WSe₂ DLHJ of one embodiment of …
FIG. 5 shows (a) a schematic diagram of a KPFM measurement method according to the present disclosure, 40 (b) transistor characteristics of n-i WSe₂ junction, …
FIG. 6 shows (a) a schematic diagram and a circuit configuration of a quaternary latch composed of a triple 50 NDR circuit that may be implemented via …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A negative transconductance device comprising: a monolithic WSe₂ semiconductor thin film forming a continuous channel layer; a first chemically doped layer formed in a first area of the WSe₂ semiconductor thin film, the first doped region configured to supply electrons to the first area; a second chemically doped layer formed in a second area of the WSe₂ semiconductor thin film, the second doped region configured to supply holes to the second area, wherein the second area is spaced apart from the first area along a lateral direction of the WSe₂ semiconduc-tor thin film; 60 a third area of the WSe₂ semiconductor thin film disposed between the first and second areas and remaining substantially intrinsic or undoped; a first electrode electrically connected to the first area of the WSe₂ semiconductor thin film; 65 a second electrode electrically connected to the second area of the WSe₂ semiconductor thin film; and B₂ a third electrode configured to apply a gate voltage simultaneously to the first area, the second area, and the third area to induce ambipolar carrier transport and generate negative transconductance behavior.
The negative transconductance device of claim 1, wherein the first chemically doped layer comprises CH₃ radicals as n-type dopants, and the second chemically doped layer comprises Au₂Cl₆ as p-type dopants.
The negative transconductance device of claim 1, wherein a poly (methyl methacrylate) (PMMA) coating layer is disposed on the third area of the WSe₂ semiconductor thin film to suppress unintentional doping and stabilize the intrinsic electrical properties of the third area.
The negative transconductance device of claim 1, wherein the device further comprises: a semiconductor substrate; and an insulating film disposed on a surface of the semiconductor substrate, wherein the WSe₂ semiconductor thin film is supported by the insulating film, and wherein the semiconductor substrate functions as a global back gate for applying the gate voltage to the first, second, and third areas of the WSe₂ semiconductor thin film.
A multi-valued memory device comprising: a monolithic WSe₂ semiconductor thin film forming a continuous channel layer; a first chemically doped layer disposed in a first area of the WSe₂ semiconductor thin film and configured to supply electrons to the first area; a second chemically doped layer disposed in a second area of the WSe₂ semiconductor thin film and config-ured to supply holes to the second area, wherein the second area is laterally spaced apart from the first area; a third area of the WSe₂ semiconductor thin film disposed between the first and second areas and having an intrinsic or undoped carrier profile; a first electrode electrically connected to the first area of the WSe₂ semiconductor thin film; a second electrode electrically connected to the second area of the WSe₂ semiconductor thin film; and a third electrode configured to apply a gate voltage to the first, second, and third areas of the WSe₂ semiconduc-tor thin film, wherein the device is configured to exhibit multiple stable current levels at the second electrode in response to different gate voltages applied to the third electrode, such that each current level represents a distinct logic state.
The multi-valued memory device of claim 6, wherein the first chemically doped layer includes CH₃ radicals as n-type dopants, and the second chemically doped layer includes Au₂Cl₆ as p-type dopants.
The multi-valued memory device of claim 6, wherein a poly (methyl methacrylate) (PMMA) coating layer is disposed on the third area of the WSe₂ semi13 14 conductor thin film to suppress unintentional doping and stabilize the intrinsic electrical properties of the third region.
The multi-valued memory device of claim 6, wherein the device further comprises: 5 a semiconductor substrate; and an insulating film disposed on a surface of the semiconductor substrate, wherein the WSe₂ semiconductor thin film is supported by the insulating film, and wherein the semiconductor substrate functions as a global back gate for applying the gate voltage to the first, second, and third areas of the WSe₂ semiconductor thin film. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
negative transconductance device (n-i-p double lateral homojunction)
multi-valued memory device (n-i-p double lateral homojunction)
Materials described outside the worked examples.
WSe₂ semiconductor thin film
WSe₂
first chemically doped layer (n-type)
Measurements and analyses referenced in the patent, with their drawing references.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Cited non-patent literature · 1
Patent
Atlas literature
Patent
US 12,501,604 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram for illustrating a negative transcon- ductance device according to one embodiment of the present disclosure.
FIG. 2 is a diagram and a circuit diagram for illustrating 20 a multi-valued memory device according to one embodi- ment of the present disclosure. (a) in
FIG. 3.
FIG. 4 is a diagram analyzing a WSe₂ surface charge transfer doping mechanism via density functional theory (DFT) calculation of WSe₂ DLHJ of one embodiment of …
FIG. 5 shows (a) a schematic diagram of a KPFM measurement method according to the present disclosure, 40 (b) transistor characteristics of n-i WSe₂ junction, …
FIG. 6 shows (a) a schematic diagram and a circuit configuration of a quaternary latch composed of a triple 50 NDR circuit that may be implemented via …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A negative transconductance device comprising: a monolithic WSe₂ semiconductor thin film forming a continuous channel layer; a first chemically doped layer formed in a first area of the WSe₂ semiconductor thin film, the first doped region configured to supply electrons to the first area; a second chemically doped layer formed in a second area of the WSe₂ semiconductor thin film, the second doped region configured to supply holes to the second area, wherein the second area is spaced apart from the first area along a lateral direction of the WSe₂ semiconduc-tor thin film; 60 a third area of the WSe₂ semiconductor thin film disposed between the first and second areas and remaining substantially intrinsic or undoped; a first electrode electrically connected to the first area of the WSe₂ semiconductor thin film; 65 a second electrode electrically connected to the second area of the WSe₂ semiconductor thin film; and B₂ a third electrode configured to apply a gate voltage simultaneously to the first area, the second area, and the third area to induce ambipolar carrier transport and generate negative transconductance behavior.
The negative transconductance device of claim 1, wherein the first chemically doped layer comprises CH₃ radicals as n-type dopants, and the second chemically doped layer comprises Au₂Cl₆ as p-type dopants.
The negative transconductance device of claim 1, wherein a poly (methyl methacrylate) (PMMA) coating layer is disposed on the third area of the WSe₂ semiconductor thin film to suppress unintentional doping and stabilize the intrinsic electrical properties of the third area.
The negative transconductance device of claim 1, wherein the device further comprises: a semiconductor substrate; and an insulating film disposed on a surface of the semiconductor substrate, wherein the WSe₂ semiconductor thin film is supported by the insulating film, and wherein the semiconductor substrate functions as a global back gate for applying the gate voltage to the first, second, and third areas of the WSe₂ semiconductor thin film.
A multi-valued memory device comprising: a monolithic WSe₂ semiconductor thin film forming a continuous channel layer; a first chemically doped layer disposed in a first area of the WSe₂ semiconductor thin film and configured to supply electrons to the first area; a second chemically doped layer disposed in a second area of the WSe₂ semiconductor thin film and config-ured to supply holes to the second area, wherein the second area is laterally spaced apart from the first area; a third area of the WSe₂ semiconductor thin film disposed between the first and second areas and having an intrinsic or undoped carrier profile; a first electrode electrically connected to the first area of the WSe₂ semiconductor thin film; a second electrode electrically connected to the second area of the WSe₂ semiconductor thin film; and a third electrode configured to apply a gate voltage to the first, second, and third areas of the WSe₂ semiconduc-tor thin film, wherein the device is configured to exhibit multiple stable current levels at the second electrode in response to different gate voltages applied to the third electrode, such that each current level represents a distinct logic state.
The multi-valued memory device of claim 6, wherein the first chemically doped layer includes CH₃ radicals as n-type dopants, and the second chemically doped layer includes Au₂Cl₆ as p-type dopants.
The multi-valued memory device of claim 6, wherein a poly (methyl methacrylate) (PMMA) coating layer is disposed on the third area of the WSe₂ semi13 14 conductor thin film to suppress unintentional doping and stabilize the intrinsic electrical properties of the third region.
The multi-valued memory device of claim 6, wherein the device further comprises: 5 a semiconductor substrate; and an insulating film disposed on a surface of the semiconductor substrate, wherein the WSe₂ semiconductor thin film is supported by the insulating film, and wherein the semiconductor substrate functions as a global back gate for applying the gate voltage to the first, second, and third areas of the WSe₂ semiconductor thin film. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
negative transconductance device (n-i-p double lateral homojunction)
multi-valued memory device (n-i-p double lateral homojunction)
Materials described outside the worked examples.
WSe₂ semiconductor thin film
WSe₂
first chemically doped layer (n-type)
Measurements and analyses referenced in the patent, with their drawing references.
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Cited non-patent literature · 1
second chemically doped layer (p-type)
CH₃ radicals
CH₃
Au₂Cl₆
poly(methyl methacrylate) (PMMA)
FIG. 5 shows (a) a schematic diagram of a KPFM measurement method according to the present disclosure, 40 (b) transistor characteristics of n-i WSe₂ junction, …
second chemically doped layer (p-type)
CH₃ radicals
CH₃
Au₂Cl₆
poly(methyl methacrylate) (PMMA)
FIG. 5 shows (a) a schematic diagram of a KPFM measurement method according to the present disclosure, 40 (b) transistor characteristics of n-i WSe₂ junction, …
second chemically doped layer (p-type)
CH₃ radicals
CH₃
Au₂Cl₆
poly(methyl methacrylate) (PMMA)
FIG. 5 shows (a) a schematic diagram of a KPFM measurement method according to the present disclosure, 40 (b) transistor characteristics of n-i WSe₂ junction, …
second chemically doped layer (p-type)
CH₃ radicals
CH₃
Au₂Cl₆
poly(methyl methacrylate) (PMMA)
FIG. 5 shows (a) a schematic diagram of a KPFM measurement method according to the present disclosure, 40 (b) transistor characteristics of n-i WSe₂ junction, …
