Patent
US 10,283,358LATERAL GAN PN JUNCTION DIODE ENABLED BY SIDEWALL REGROWTH
Rongming Chu
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,283,358Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 2 shows an scanning electron micrograph (SEM) of an embodiment of a device at one processing step.
Figure 3 shows an SEM of an embodiment of a device at one processing step. [0011] Figure 4a-c show SEMs of a embodiments of a device at a particular processing step.
Figure 5 is a diagram of an embodiment disclosed herein.
Figure 6 is a diagram of an embodiment of a vertical diode.
Figure 7 is a diagram of a plan view of an embodiment of a vertical diode.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a lateral PN junction, the method comprising: conformally growing p-GaN material on a n-GaN vertical surface extending vertically from an n-GaN horizontal surface on an n-GaN drift layer to form a first PN junction, wherein the n-GaN horizontal surface extends horizontally from the n-GaN vertical surface and the n-GaN horizontal surface has a layer of dielectric material formed on the n-GaN horizontal surface that extends from the p-GaN surface.
The method of claim 1, wherein the n-GaN vertical surface is a non-polar plane of GaN.
The method of claim 1, wherein the n-GaN horizontal surface contacts the layer of dielectric material, and the n-GaN horizontal surface comprises a c-plane of GaN.
The method of claim 1, wherein the layer of dielectric material is formed by anisotropic deposition of dielectric material on the n-GaN horizontal surface resulting in a thicker layer of dielectric present on the n-GaN horizontal surface than a layer of dielectric present on the n-GaN vertical surface, followed by isotropic removal of a portion of the dielectric material resulting in the layer of dielectric formed on the n-GaN horizontal surface remaining.
The method of claim 1, wherein the n-GaN vertical surface is substantially free of dielectric material after the isotropic removal of dielectric material.
The method of claim 1, wherein the n- G aN vertical surface is a first sidewall of a trench formed in an n- G aN drift layer and the n- G aN horizontal surface forms the bottom of the trench.
A method of fabricating a lateral PN junction, the method comprising: isotropically depositing a first layer of dielectric material on a n- G aN drift layer; patterning and etching the n- G aN drift layer to form a trench through the first layer of dielectric material and into the n- G aN drift layer, wherein the trench comprises a bottom surface and a first sidewall; anisotropically depositing a second layer of dielectric material on the bottom surface of the trench and on the first layer of dielectric material; isotropically etching the trench resulting in n- G aN drift layer having remaining first layer and second layer of dielectric material on an upper horizontal surface of the n- G aN drift layer and remaining second layer of dielectric material on the bottom surface of the trench and the first sidewall having exposed n- G aN material; conformally regrowing p- G aN material on the exposed n- G aN material of the first sidewall.
A semiconductor comprising a lateral PN junction, the semiconductor comprising: an n- G aN horizontal surface; an n- G aN vertical surface extending vertically from the n- G aN horizontal surface; a dielectric layer deposited on the n- G aN horizontal surface and contacting the n- GaN vertical surface; and a p- G aN layer extending horizontally from the n- G aN vertical surface to form a first PN junction therewith.
The semiconductor of claim 11, wherein the n- G aN vertical surface is a non-polar plane of G aN.
The semiconductor of claim 11, wherein the n- G aN horizontal surface comprises a c-plane of G aN.
The semiconductor of claim 11, further comprising: a second n- G aN vertical surface extending vertically from the n- G aN horizontal surface and facing the n- G aN vertical surface; a second p- G aN layer extending horizontally from the second n- G aN vertical surface toward the n- G aN vertical surface, the second p- G aN layer and the second n- G aN vertical surface forming a second PN junction.
Layer stacks claimed or described, ordered top of device to substrate.
lateral PN junction diode (trench-based)
lateral PN junction semiconductor structure
Materials described outside the worked examples.
n-GaN
GaN
dielectric material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2 shows an scanning electron micrograph (SEM) of an embodiment of a device at one processing step.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Duration | ≤ 30 minutes | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,283,358Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 2 shows an scanning electron micrograph (SEM) of an embodiment of a device at one processing step.
Figure 3 shows an SEM of an embodiment of a device at one processing step. [0011] Figure 4a-c show SEMs of a embodiments of a device at a particular processing step.
Figure 5 is a diagram of an embodiment disclosed herein.
Figure 6 is a diagram of an embodiment of a vertical diode.
Figure 7 is a diagram of a plan view of an embodiment of a vertical diode.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a lateral PN junction, the method comprising: conformally growing p-GaN material on a n-GaN vertical surface extending vertically from an n-GaN horizontal surface on an n-GaN drift layer to form a first PN junction, wherein the n-GaN horizontal surface extends horizontally from the n-GaN vertical surface and the n-GaN horizontal surface has a layer of dielectric material formed on the n-GaN horizontal surface that extends from the p-GaN surface.
The method of claim 1, wherein the n-GaN vertical surface is a non-polar plane of GaN.
The method of claim 1, wherein the n-GaN horizontal surface contacts the layer of dielectric material, and the n-GaN horizontal surface comprises a c-plane of GaN.
The method of claim 1, wherein the layer of dielectric material is formed by anisotropic deposition of dielectric material on the n-GaN horizontal surface resulting in a thicker layer of dielectric present on the n-GaN horizontal surface than a layer of dielectric present on the n-GaN vertical surface, followed by isotropic removal of a portion of the dielectric material resulting in the layer of dielectric formed on the n-GaN horizontal surface remaining.
The method of claim 1, wherein the n-GaN vertical surface is substantially free of dielectric material after the isotropic removal of dielectric material.
The method of claim 1, wherein the n- G aN vertical surface is a first sidewall of a trench formed in an n- G aN drift layer and the n- G aN horizontal surface forms the bottom of the trench.
A method of fabricating a lateral PN junction, the method comprising: isotropically depositing a first layer of dielectric material on a n- G aN drift layer; patterning and etching the n- G aN drift layer to form a trench through the first layer of dielectric material and into the n- G aN drift layer, wherein the trench comprises a bottom surface and a first sidewall; anisotropically depositing a second layer of dielectric material on the bottom surface of the trench and on the first layer of dielectric material; isotropically etching the trench resulting in n- G aN drift layer having remaining first layer and second layer of dielectric material on an upper horizontal surface of the n- G aN drift layer and remaining second layer of dielectric material on the bottom surface of the trench and the first sidewall having exposed n- G aN material; conformally regrowing p- G aN material on the exposed n- G aN material of the first sidewall.
A semiconductor comprising a lateral PN junction, the semiconductor comprising: an n- G aN horizontal surface; an n- G aN vertical surface extending vertically from the n- G aN horizontal surface; a dielectric layer deposited on the n- G aN horizontal surface and contacting the n- GaN vertical surface; and a p- G aN layer extending horizontally from the n- G aN vertical surface to form a first PN junction therewith.
The semiconductor of claim 11, wherein the n- G aN vertical surface is a non-polar plane of G aN.
The semiconductor of claim 11, wherein the n- G aN horizontal surface comprises a c-plane of G aN.
The semiconductor of claim 11, further comprising: a second n- G aN vertical surface extending vertically from the n- G aN horizontal surface and facing the n- G aN vertical surface; a second p- G aN layer extending horizontally from the second n- G aN vertical surface toward the n- G aN vertical surface, the second p- G aN layer and the second n- G aN vertical surface forming a second PN junction.
Layer stacks claimed or described, ordered top of device to substrate.
lateral PN junction diode (trench-based)
lateral PN junction semiconductor structure
Materials described outside the worked examples.
n-GaN
GaN
dielectric material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2 shows an scanning electron micrograph (SEM) of an embodiment of a device at one processing step.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Duration | ≤ 30 minutes | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,283,358Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 2 shows an scanning electron micrograph (SEM) of an embodiment of a device at one processing step.
Figure 3 shows an SEM of an embodiment of a device at one processing step. [0011] Figure 4a-c show SEMs of a embodiments of a device at a particular processing step.
Figure 5 is a diagram of an embodiment disclosed herein.
Figure 6 is a diagram of an embodiment of a vertical diode.
Figure 7 is a diagram of a plan view of an embodiment of a vertical diode.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a lateral PN junction, the method comprising: conformally growing p-GaN material on a n-GaN vertical surface extending vertically from an n-GaN horizontal surface on an n-GaN drift layer to form a first PN junction, wherein the n-GaN horizontal surface extends horizontally from the n-GaN vertical surface and the n-GaN horizontal surface has a layer of dielectric material formed on the n-GaN horizontal surface that extends from the p-GaN surface.
The method of claim 1, wherein the n-GaN vertical surface is a non-polar plane of GaN.
The method of claim 1, wherein the n-GaN horizontal surface contacts the layer of dielectric material, and the n-GaN horizontal surface comprises a c-plane of GaN.
The method of claim 1, wherein the layer of dielectric material is formed by anisotropic deposition of dielectric material on the n-GaN horizontal surface resulting in a thicker layer of dielectric present on the n-GaN horizontal surface than a layer of dielectric present on the n-GaN vertical surface, followed by isotropic removal of a portion of the dielectric material resulting in the layer of dielectric formed on the n-GaN horizontal surface remaining.
The method of claim 1, wherein the n-GaN vertical surface is substantially free of dielectric material after the isotropic removal of dielectric material.
The method of claim 1, wherein the n- G aN vertical surface is a first sidewall of a trench formed in an n- G aN drift layer and the n- G aN horizontal surface forms the bottom of the trench.
A method of fabricating a lateral PN junction, the method comprising: isotropically depositing a first layer of dielectric material on a n- G aN drift layer; patterning and etching the n- G aN drift layer to form a trench through the first layer of dielectric material and into the n- G aN drift layer, wherein the trench comprises a bottom surface and a first sidewall; anisotropically depositing a second layer of dielectric material on the bottom surface of the trench and on the first layer of dielectric material; isotropically etching the trench resulting in n- G aN drift layer having remaining first layer and second layer of dielectric material on an upper horizontal surface of the n- G aN drift layer and remaining second layer of dielectric material on the bottom surface of the trench and the first sidewall having exposed n- G aN material; conformally regrowing p- G aN material on the exposed n- G aN material of the first sidewall.
A semiconductor comprising a lateral PN junction, the semiconductor comprising: an n- G aN horizontal surface; an n- G aN vertical surface extending vertically from the n- G aN horizontal surface; a dielectric layer deposited on the n- G aN horizontal surface and contacting the n- GaN vertical surface; and a p- G aN layer extending horizontally from the n- G aN vertical surface to form a first PN junction therewith.
The semiconductor of claim 11, wherein the n- G aN vertical surface is a non-polar plane of G aN.
The semiconductor of claim 11, wherein the n- G aN horizontal surface comprises a c-plane of G aN.
The semiconductor of claim 11, further comprising: a second n- G aN vertical surface extending vertically from the n- G aN horizontal surface and facing the n- G aN vertical surface; a second p- G aN layer extending horizontally from the second n- G aN vertical surface toward the n- G aN vertical surface, the second p- G aN layer and the second n- G aN vertical surface forming a second PN junction.
Layer stacks claimed or described, ordered top of device to substrate.
lateral PN junction diode (trench-based)
lateral PN junction semiconductor structure
Materials described outside the worked examples.
n-GaN
GaN
dielectric material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2 shows an scanning electron micrograph (SEM) of an embodiment of a device at one processing step.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Duration | ≤ 30 minutes | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,283,358Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 2 shows an scanning electron micrograph (SEM) of an embodiment of a device at one processing step.
Figure 3 shows an SEM of an embodiment of a device at one processing step. [0011] Figure 4a-c show SEMs of a embodiments of a device at a particular processing step.
Figure 5 is a diagram of an embodiment disclosed herein.
Figure 6 is a diagram of an embodiment of a vertical diode.
Figure 7 is a diagram of a plan view of an embodiment of a vertical diode.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a lateral PN junction, the method comprising: conformally growing p-GaN material on a n-GaN vertical surface extending vertically from an n-GaN horizontal surface on an n-GaN drift layer to form a first PN junction, wherein the n-GaN horizontal surface extends horizontally from the n-GaN vertical surface and the n-GaN horizontal surface has a layer of dielectric material formed on the n-GaN horizontal surface that extends from the p-GaN surface.
The method of claim 1, wherein the n-GaN vertical surface is a non-polar plane of GaN.
The method of claim 1, wherein the n-GaN horizontal surface contacts the layer of dielectric material, and the n-GaN horizontal surface comprises a c-plane of GaN.
The method of claim 1, wherein the layer of dielectric material is formed by anisotropic deposition of dielectric material on the n-GaN horizontal surface resulting in a thicker layer of dielectric present on the n-GaN horizontal surface than a layer of dielectric present on the n-GaN vertical surface, followed by isotropic removal of a portion of the dielectric material resulting in the layer of dielectric formed on the n-GaN horizontal surface remaining.
The method of claim 1, wherein the n-GaN vertical surface is substantially free of dielectric material after the isotropic removal of dielectric material.
The method of claim 1, wherein the n- G aN vertical surface is a first sidewall of a trench formed in an n- G aN drift layer and the n- G aN horizontal surface forms the bottom of the trench.
A method of fabricating a lateral PN junction, the method comprising: isotropically depositing a first layer of dielectric material on a n- G aN drift layer; patterning and etching the n- G aN drift layer to form a trench through the first layer of dielectric material and into the n- G aN drift layer, wherein the trench comprises a bottom surface and a first sidewall; anisotropically depositing a second layer of dielectric material on the bottom surface of the trench and on the first layer of dielectric material; isotropically etching the trench resulting in n- G aN drift layer having remaining first layer and second layer of dielectric material on an upper horizontal surface of the n- G aN drift layer and remaining second layer of dielectric material on the bottom surface of the trench and the first sidewall having exposed n- G aN material; conformally regrowing p- G aN material on the exposed n- G aN material of the first sidewall.
A semiconductor comprising a lateral PN junction, the semiconductor comprising: an n- G aN horizontal surface; an n- G aN vertical surface extending vertically from the n- G aN horizontal surface; a dielectric layer deposited on the n- G aN horizontal surface and contacting the n- GaN vertical surface; and a p- G aN layer extending horizontally from the n- G aN vertical surface to form a first PN junction therewith.
The semiconductor of claim 11, wherein the n- G aN vertical surface is a non-polar plane of G aN.
The semiconductor of claim 11, wherein the n- G aN horizontal surface comprises a c-plane of G aN.
The semiconductor of claim 11, further comprising: a second n- G aN vertical surface extending vertically from the n- G aN horizontal surface and facing the n- G aN vertical surface; a second p- G aN layer extending horizontally from the second n- G aN vertical surface toward the n- G aN vertical surface, the second p- G aN layer and the second n- G aN vertical surface forming a second PN junction.
Layer stacks claimed or described, ordered top of device to substrate.
lateral PN junction diode (trench-based)
lateral PN junction semiconductor structure
Materials described outside the worked examples.
n-GaN
GaN
dielectric material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 2 shows an scanning electron micrograph (SEM) of an embodiment of a device at one processing step.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Duration | ≤ 30 minutes | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
SiO₂
SiN
Figure 3 shows an SEM of an embodiment of a device at one processing step. [0011] Figure 4a-c show SEMs of a embodiments of a device at a particular processing step.
| ≤ 20 minutes |
| — |
Duration | ≤ 10 minutes | — |
Duration | ≤ 5 minutes | — |
SiO₂
SiN
Figure 3 shows an SEM of an embodiment of a device at one processing step. [0011] Figure 4a-c show SEMs of a embodiments of a device at a particular processing step.
| ≤ 20 minutes |
| — |
Duration | ≤ 10 minutes | — |
Duration | ≤ 5 minutes | — |
SiO₂
SiN
Figure 3 shows an SEM of an embodiment of a device at one processing step. [0011] Figure 4a-c show SEMs of a embodiments of a device at a particular processing step.
| ≤ 20 minutes |
| — |
Duration | ≤ 10 minutes | — |
Duration | ≤ 5 minutes | — |
SiO₂
SiN
Figure 3 shows an SEM of an embodiment of a device at one processing step. [0011] Figure 4a-c show SEMs of a embodiments of a device at a particular processing step.
| ≤ 20 minutes |
| — |
Duration | ≤ 10 minutes | — |
Duration | ≤ 5 minutes | — |