Patent
US 11,198,901METHOD FOR FORMING NANO-GAPS IN GRAPHENE
George Andrew Davidson BRIGGS
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,198,901Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method of claim 27 wherein the graphene is in the form of a ribbon comprising a notch. Previously presented
The method as claimed in claim 1 wherein the notch comprises a crack therein. Previously presented
The method as claimed in claim 1 wherein the ribbon comprises an asymmetrical ribbon. Previously presented
The method of claim 1, wherein the notch comprises a V- shaped notch. Previously presented
The method as claimed in claim 27 wherein said graphene is single layer graphene (SLG). Previously presented
Canceled
Canceled
The method as claimed in claim 27 wherein the width of the nano-gap is determined by analyzing an I-V measurement. Previously presented
The method as claimed in claim 27 wherein changes in a conductance are used to determine the onset of gap formation. Previously presented
The method as claimed in claim 27 wherein the width of the nano-gap is 0.1 to 5 nm. Previously presented
The method as claimed in claim 27 wherein the graphene is CVD-grown graphene. Previously presented
Canceled
The method as claimed in claim 27 wherein, prior to application of the voltage, the graphene is shaped lithographically. Previously presented
- 20. Canceled
Canceled
The method as claimed in claim 27 wherein the width of the nano-gap is 0.5 to 2.5 nm. Previously presented
The method as claimed in claim 27 wherein the width of the nano-gap is 1 to 2 nm. Previously presented
A method for preparing a na no -gap array on graphene, said method comprising: (i) depositing [[a]] graphene onto a substrate; (ii) shaping the graphene such that it has a plurality of narrow points; and (iii) controlling the position of na no -gap formation in the graphene by feed-back- controlled electroburning which comprises applying a voltage across each narrow point, wherein a region across which the voltage is applied comprises a width which is the narrowest in that region, wherein the step of applying a voltage comprises: (a) increasing the voltage while recording the current or resistance; (b) decreasing the voltage when said current drops or said resistance increases; and repeating steps (a) and (b) until a na no -gap has formed; wherein the na no -gap forms via a crack developing across the graphene thus forming an array of na no -gaps, each of which extends across the entire width of the graphene. Currently amended
The method of claim 27, wherein said substrate is a silicon substrate which is patterned with electrical contacts. Previously presented
The method of claim 27, wherein controlling the position of the na no -gap formation aligns a na no -gap with a lithographically defined structure. Previously presented
The method of claim 27, wherein the plurality of narrow points comprises a plurality of V-shaped notches. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
graphene nano-gap electrode array
graphene nano-gap on silicon substrate with electrical contacts
Materials described outside the worked examples.
graphene
C
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
low-bias resistance at gap formation (threshold range) | 100–1000 | C |
Thickness | 0.1–5 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,198,901Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method of claim 27 wherein the graphene is in the form of a ribbon comprising a notch. Previously presented
The method as claimed in claim 1 wherein the notch comprises a crack therein. Previously presented
The method as claimed in claim 1 wherein the ribbon comprises an asymmetrical ribbon. Previously presented
The method of claim 1, wherein the notch comprises a V- shaped notch. Previously presented
The method as claimed in claim 27 wherein said graphene is single layer graphene (SLG). Previously presented
Canceled
Canceled
The method as claimed in claim 27 wherein the width of the nano-gap is determined by analyzing an I-V measurement. Previously presented
The method as claimed in claim 27 wherein changes in a conductance are used to determine the onset of gap formation. Previously presented
The method as claimed in claim 27 wherein the width of the nano-gap is 0.1 to 5 nm. Previously presented
The method as claimed in claim 27 wherein the graphene is CVD-grown graphene. Previously presented
Canceled
The method as claimed in claim 27 wherein, prior to application of the voltage, the graphene is shaped lithographically. Previously presented
- 20. Canceled
Canceled
The method as claimed in claim 27 wherein the width of the nano-gap is 0.5 to 2.5 nm. Previously presented
The method as claimed in claim 27 wherein the width of the nano-gap is 1 to 2 nm. Previously presented
A method for preparing a na no -gap array on graphene, said method comprising: (i) depositing [[a]] graphene onto a substrate; (ii) shaping the graphene such that it has a plurality of narrow points; and (iii) controlling the position of na no -gap formation in the graphene by feed-back- controlled electroburning which comprises applying a voltage across each narrow point, wherein a region across which the voltage is applied comprises a width which is the narrowest in that region, wherein the step of applying a voltage comprises: (a) increasing the voltage while recording the current or resistance; (b) decreasing the voltage when said current drops or said resistance increases; and repeating steps (a) and (b) until a na no -gap has formed; wherein the na no -gap forms via a crack developing across the graphene thus forming an array of na no -gaps, each of which extends across the entire width of the graphene. Currently amended
The method of claim 27, wherein said substrate is a silicon substrate which is patterned with electrical contacts. Previously presented
The method of claim 27, wherein controlling the position of the na no -gap formation aligns a na no -gap with a lithographically defined structure. Previously presented
The method of claim 27, wherein the plurality of narrow points comprises a plurality of V-shaped notches. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
graphene nano-gap electrode array
graphene nano-gap on silicon substrate with electrical contacts
Materials described outside the worked examples.
graphene
C
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
low-bias resistance at gap formation (threshold range) | 100–1000 | C |
Thickness | 0.1–5 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,198,901Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method of claim 27 wherein the graphene is in the form of a ribbon comprising a notch. Previously presented
The method as claimed in claim 1 wherein the notch comprises a crack therein. Previously presented
The method as claimed in claim 1 wherein the ribbon comprises an asymmetrical ribbon. Previously presented
The method of claim 1, wherein the notch comprises a V- shaped notch. Previously presented
The method as claimed in claim 27 wherein said graphene is single layer graphene (SLG). Previously presented
Canceled
Canceled
The method as claimed in claim 27 wherein the width of the nano-gap is determined by analyzing an I-V measurement. Previously presented
The method as claimed in claim 27 wherein changes in a conductance are used to determine the onset of gap formation. Previously presented
The method as claimed in claim 27 wherein the width of the nano-gap is 0.1 to 5 nm. Previously presented
The method as claimed in claim 27 wherein the graphene is CVD-grown graphene. Previously presented
Canceled
The method as claimed in claim 27 wherein, prior to application of the voltage, the graphene is shaped lithographically. Previously presented
- 20. Canceled
Canceled
The method as claimed in claim 27 wherein the width of the nano-gap is 0.5 to 2.5 nm. Previously presented
The method as claimed in claim 27 wherein the width of the nano-gap is 1 to 2 nm. Previously presented
A method for preparing a na no -gap array on graphene, said method comprising: (i) depositing [[a]] graphene onto a substrate; (ii) shaping the graphene such that it has a plurality of narrow points; and (iii) controlling the position of na no -gap formation in the graphene by feed-back- controlled electroburning which comprises applying a voltage across each narrow point, wherein a region across which the voltage is applied comprises a width which is the narrowest in that region, wherein the step of applying a voltage comprises: (a) increasing the voltage while recording the current or resistance; (b) decreasing the voltage when said current drops or said resistance increases; and repeating steps (a) and (b) until a na no -gap has formed; wherein the na no -gap forms via a crack developing across the graphene thus forming an array of na no -gaps, each of which extends across the entire width of the graphene. Currently amended
The method of claim 27, wherein said substrate is a silicon substrate which is patterned with electrical contacts. Previously presented
The method of claim 27, wherein controlling the position of the na no -gap formation aligns a na no -gap with a lithographically defined structure. Previously presented
The method of claim 27, wherein the plurality of narrow points comprises a plurality of V-shaped notches. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
graphene nano-gap electrode array
graphene nano-gap on silicon substrate with electrical contacts
Materials described outside the worked examples.
graphene
C
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
low-bias resistance at gap formation (threshold range) | 100–1000 | C |
Thickness | 0.1–5 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,198,901Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method of claim 27 wherein the graphene is in the form of a ribbon comprising a notch. Previously presented
The method as claimed in claim 1 wherein the notch comprises a crack therein. Previously presented
The method as claimed in claim 1 wherein the ribbon comprises an asymmetrical ribbon. Previously presented
The method of claim 1, wherein the notch comprises a V- shaped notch. Previously presented
The method as claimed in claim 27 wherein said graphene is single layer graphene (SLG). Previously presented
Canceled
Canceled
The method as claimed in claim 27 wherein the width of the nano-gap is determined by analyzing an I-V measurement. Previously presented
The method as claimed in claim 27 wherein changes in a conductance are used to determine the onset of gap formation. Previously presented
The method as claimed in claim 27 wherein the width of the nano-gap is 0.1 to 5 nm. Previously presented
The method as claimed in claim 27 wherein the graphene is CVD-grown graphene. Previously presented
Canceled
The method as claimed in claim 27 wherein, prior to application of the voltage, the graphene is shaped lithographically. Previously presented
- 20. Canceled
Canceled
The method as claimed in claim 27 wherein the width of the nano-gap is 0.5 to 2.5 nm. Previously presented
The method as claimed in claim 27 wherein the width of the nano-gap is 1 to 2 nm. Previously presented
A method for preparing a na no -gap array on graphene, said method comprising: (i) depositing [[a]] graphene onto a substrate; (ii) shaping the graphene such that it has a plurality of narrow points; and (iii) controlling the position of na no -gap formation in the graphene by feed-back- controlled electroburning which comprises applying a voltage across each narrow point, wherein a region across which the voltage is applied comprises a width which is the narrowest in that region, wherein the step of applying a voltage comprises: (a) increasing the voltage while recording the current or resistance; (b) decreasing the voltage when said current drops or said resistance increases; and repeating steps (a) and (b) until a na no -gap has formed; wherein the na no -gap forms via a crack developing across the graphene thus forming an array of na no -gaps, each of which extends across the entire width of the graphene. Currently amended
The method of claim 27, wherein said substrate is a silicon substrate which is patterned with electrical contacts. Previously presented
The method of claim 27, wherein controlling the position of the na no -gap formation aligns a na no -gap with a lithographically defined structure. Previously presented
The method of claim 27, wherein the plurality of narrow points comprises a plurality of V-shaped notches. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
graphene nano-gap electrode array
graphene nano-gap on silicon substrate with electrical contacts
Materials described outside the worked examples.
graphene
C
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
low-bias resistance at gap formation (threshold range) | 100–1000 | C |
Thickness | 0.1–5 nm |
Related documents with shared materials, methods, properties, or citations.
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Thickness | 0.5–2.5 nm | — |
Thickness | 1–2 nm | — |
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Thickness | 0.5–2.5 nm | — |
Thickness | 1–2 nm | — |
| — |
Thickness | 0.5–2.5 nm | — |
Thickness | 1–2 nm | — |
| — |
Thickness | 0.5–2.5 nm | — |
Thickness | 1–2 nm | — |