Patent
US 12,431,874 B2INTEGRATED GaN-BASED LOGIC LEVEL TRANSLATOR
Ravi Ananth, Edward Lee, Michael Chapman
Efficient Power Conversion Corporation, El Segundo, CA (US)·Sep. 30, 2025·US
Copyright © 2026 Matter42. All rights reserved.
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US 12,431,874 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a conventional logic-level shifter circuit; 45
FIG. 2 is a conventional differential latch-based logic- level shifter;
FIG. 3 is a conventional common-gate based logic-level shifter;
FIG. 4 is a prior art voltage divider level-shifter circuit 50 design;
FIG. 5 shows the resistive network-based logic-level shifter circuit of the present invention with a single-ended input;
FIG. 6 shows the resistive network-based logic-level 55 shifter circuit of the present invention with a differential input; and
FIG. 7 shows the resistive network-based logic level shifter circuit of the present invention with a differential input and with series input resistors to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated GaN based logic-level shifter, compris-ing: a GaN differential comparator having first and second inputs and corresponding positive and negative out-puts; and a resistive network comprising a plurality of resistors, the resistive network including: a first voltage divider for receiving an input signal and outputting a level shifted and scaled input signal, the first voltage divider comprising a first resistor, a scale resistor, and an offset resistor disposed in series between a voltage supply and a lower voltage; and a second voltage divider for generating a trip voltage, the second voltage divider including a resistive hys-teresis circuit; wherein the level shifted and scaled input signal from the first voltage divider is connected to the first input of the GaN differential comparator, and the trip voltage from the second voltage divider is connected to the second input of the GaN differential comparator, such that the positive and negative outputs of the GaN differential comparator comprise complementary bipolar level shifted signals corresponding to the input signal; and wherein the values of the first resistor and the offset resistor are set such that the level shifted and scaled input signal to the first input of the comparator hovers around an optimal bias point of the comparator.
The integrated GaN based logic-level shifter according to claim 1, wherein the input signal is connected between the scale resistor and the offset resistor, and the first input of the GaN differential comparator is connected between the first resistor and the scale resistor.
The integrated GaN based logic-level shifted according to claim 1, wherein the second voltage divider generates a trip voltage which hovers around the optimal bias point of the comparator.
The integrated GaN based logic-level shifter according to claim 1, wherein the GaN differential comparator is configured to control the hysteresis circuit by outputting a signal to a gate of a FET connected across the hysteresis circuit. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
integrated GaN based logic-level shifter
No layer stack recorded.
GaN differential comparator
No layer stack recorded.
Materials described outside the worked examples.
GaN
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,431,874 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a conventional logic-level shifter circuit; 45
FIG. 2 is a conventional differential latch-based logic- level shifter;
FIG. 3 is a conventional common-gate based logic-level shifter;
FIG. 4 is a prior art voltage divider level-shifter circuit 50 design;
FIG. 5 shows the resistive network-based logic-level shifter circuit of the present invention with a single-ended input;
FIG. 6 shows the resistive network-based logic-level 55 shifter circuit of the present invention with a differential input; and
FIG. 7 shows the resistive network-based logic level shifter circuit of the present invention with a differential input and with series input resistors to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated GaN based logic-level shifter, compris-ing: a GaN differential comparator having first and second inputs and corresponding positive and negative out-puts; and a resistive network comprising a plurality of resistors, the resistive network including: a first voltage divider for receiving an input signal and outputting a level shifted and scaled input signal, the first voltage divider comprising a first resistor, a scale resistor, and an offset resistor disposed in series between a voltage supply and a lower voltage; and a second voltage divider for generating a trip voltage, the second voltage divider including a resistive hys-teresis circuit; wherein the level shifted and scaled input signal from the first voltage divider is connected to the first input of the GaN differential comparator, and the trip voltage from the second voltage divider is connected to the second input of the GaN differential comparator, such that the positive and negative outputs of the GaN differential comparator comprise complementary bipolar level shifted signals corresponding to the input signal; and wherein the values of the first resistor and the offset resistor are set such that the level shifted and scaled input signal to the first input of the comparator hovers around an optimal bias point of the comparator.
The integrated GaN based logic-level shifter according to claim 1, wherein the input signal is connected between the scale resistor and the offset resistor, and the first input of the GaN differential comparator is connected between the first resistor and the scale resistor.
The integrated GaN based logic-level shifted according to claim 1, wherein the second voltage divider generates a trip voltage which hovers around the optimal bias point of the comparator.
The integrated GaN based logic-level shifter according to claim 1, wherein the GaN differential comparator is configured to control the hysteresis circuit by outputting a signal to a gate of a FET connected across the hysteresis circuit. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
integrated GaN based logic-level shifter
No layer stack recorded.
GaN differential comparator
No layer stack recorded.
Materials described outside the worked examples.
GaN
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,431,874 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a conventional logic-level shifter circuit; 45
FIG. 2 is a conventional differential latch-based logic- level shifter;
FIG. 3 is a conventional common-gate based logic-level shifter;
FIG. 4 is a prior art voltage divider level-shifter circuit 50 design;
FIG. 5 shows the resistive network-based logic-level shifter circuit of the present invention with a single-ended input;
FIG. 6 shows the resistive network-based logic-level 55 shifter circuit of the present invention with a differential input; and
FIG. 7 shows the resistive network-based logic level shifter circuit of the present invention with a differential input and with series input resistors to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated GaN based logic-level shifter, compris-ing: a GaN differential comparator having first and second inputs and corresponding positive and negative out-puts; and a resistive network comprising a plurality of resistors, the resistive network including: a first voltage divider for receiving an input signal and outputting a level shifted and scaled input signal, the first voltage divider comprising a first resistor, a scale resistor, and an offset resistor disposed in series between a voltage supply and a lower voltage; and a second voltage divider for generating a trip voltage, the second voltage divider including a resistive hys-teresis circuit; wherein the level shifted and scaled input signal from the first voltage divider is connected to the first input of the GaN differential comparator, and the trip voltage from the second voltage divider is connected to the second input of the GaN differential comparator, such that the positive and negative outputs of the GaN differential comparator comprise complementary bipolar level shifted signals corresponding to the input signal; and wherein the values of the first resistor and the offset resistor are set such that the level shifted and scaled input signal to the first input of the comparator hovers around an optimal bias point of the comparator.
The integrated GaN based logic-level shifter according to claim 1, wherein the input signal is connected between the scale resistor and the offset resistor, and the first input of the GaN differential comparator is connected between the first resistor and the scale resistor.
The integrated GaN based logic-level shifted according to claim 1, wherein the second voltage divider generates a trip voltage which hovers around the optimal bias point of the comparator.
The integrated GaN based logic-level shifter according to claim 1, wherein the GaN differential comparator is configured to control the hysteresis circuit by outputting a signal to a gate of a FET connected across the hysteresis circuit. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
integrated GaN based logic-level shifter
No layer stack recorded.
GaN differential comparator
No layer stack recorded.
Materials described outside the worked examples.
GaN
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,431,874 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a conventional logic-level shifter circuit; 45
FIG. 2 is a conventional differential latch-based logic- level shifter;
FIG. 3 is a conventional common-gate based logic-level shifter;
FIG. 4 is a prior art voltage divider level-shifter circuit 50 design;
FIG. 5 shows the resistive network-based logic-level shifter circuit of the present invention with a single-ended input;
FIG. 6 shows the resistive network-based logic-level 55 shifter circuit of the present invention with a differential input; and
FIG. 7 shows the resistive network-based logic level shifter circuit of the present invention with a differential input and with series input resistors to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated GaN based logic-level shifter, compris-ing: a GaN differential comparator having first and second inputs and corresponding positive and negative out-puts; and a resistive network comprising a plurality of resistors, the resistive network including: a first voltage divider for receiving an input signal and outputting a level shifted and scaled input signal, the first voltage divider comprising a first resistor, a scale resistor, and an offset resistor disposed in series between a voltage supply and a lower voltage; and a second voltage divider for generating a trip voltage, the second voltage divider including a resistive hys-teresis circuit; wherein the level shifted and scaled input signal from the first voltage divider is connected to the first input of the GaN differential comparator, and the trip voltage from the second voltage divider is connected to the second input of the GaN differential comparator, such that the positive and negative outputs of the GaN differential comparator comprise complementary bipolar level shifted signals corresponding to the input signal; and wherein the values of the first resistor and the offset resistor are set such that the level shifted and scaled input signal to the first input of the comparator hovers around an optimal bias point of the comparator.
The integrated GaN based logic-level shifter according to claim 1, wherein the input signal is connected between the scale resistor and the offset resistor, and the first input of the GaN differential comparator is connected between the first resistor and the scale resistor.
The integrated GaN based logic-level shifted according to claim 1, wherein the second voltage divider generates a trip voltage which hovers around the optimal bias point of the comparator.
The integrated GaN based logic-level shifter according to claim 1, wherein the GaN differential comparator is configured to control the hysteresis circuit by outputting a signal to a gate of a FET connected across the hysteresis circuit. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
integrated GaN based logic-level shifter
No layer stack recorded.
GaN differential comparator
No layer stack recorded.
Materials described outside the worked examples.
GaN
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Cited non-patent literature · 1
Cited non-patent literature · 1
Cited non-patent literature · 1
Cited non-patent literature · 1