Patent
US 9,171,907GRAPHENE TRANSISTOR
Walt A. de Heer
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,171,907Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 C, the resulting crystal 11 0 is subjected to an annealing process (e.g., by heating it to a temperature of between 1000 ° C and 2000 ° C in a partial …
FIGS. 2A-2D are schematic diagrams demonstrating a flat embodiment. [0017]
FIGS. 3A-3E are schematic diagrams demonstrating a passivated layer embodiment. Attorney Docket No. G009.P 061U₁ 3 Customer No. 2
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor, comprising: (a) a silicon carbide crystal having a silicon terminated face; (b) a semiconducting-type graphene layer bonded to the silicon terminated face; (c) a first semimetallic-type graphene layer contiguous with a first portion of the semiconducting-type graphene layer; (d) a second semimetallic-type graphene layer contiguous with a second portion of the semiconducting-type graphene l ayer that is spaced apart from the first portion; (e) an insulator layer disposed on a portion of the semiconducting-type graphene layer; and (f) a gate conductive layer disposed on the insulator layer and spaced apart from the semiconducting-type graphene layer.
The transistor of Claim 1, wherein the semiconducting-type graphene layer comprises a layer 0-type graphene.
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer comprises a layer 1-type graphene.
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer is formed adjacent to a non-silicon terminated face of the silicon carbide crystal.
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer is formed on a layer 0- type graphene layer. withdrawn
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer comprises passivated graphene. withdrawn
The transistor of Claim 1, wherein the gate conductive layer comprises a metal.
The transistor of Claim 1, further comprising: (a) a metal source contact affixed to the first semimetallic-type graphene layer; and (b) a metal drain contact affixed to the second semimetallic-type graphene layer.
A method of making a transistor, comprising the steps of: (a) forming a semiconducting-type graphene layer on a silicon terminated face of a silicon carbide crystal; Application No. 14/345,093 Amendment dated 07/02/2015 Reply to Office Action dated 03/02/2015 Page 4 of 8 (b) forming at least one semimetallic-type graphene layer adjacent to the silicon carbide crystal so that the semimetallic-type graphene layer is contiguous with the semiconducting-type graphene layer; (c) applying an insulator layer on a portion of the semiconducting layer; and (d) applying a conductor layer to the insulator layer.
The method of Claim 11, wherein the step of forming a semiconducting-type graphene layer comprises evaporating silicon from the silicon carbide crystal.
The method of Claim 11, further comprising the step of forming a raised portion on the silicon carbide crystal so that the raised portion has a silicon terminated face and at least one sidewall extending transversely therefrom so that the sidewall is not silicon terminated, wherein the semimetallic-type graphene is disposed on the sidewall.
The method of Claim 11, wherein the step of forming at least one semimetallic-type graphene layer comprises forming a plurality of graphene layers on the silicon carbide crystal and wherein the step of forming a semiconducting-type graphene layer comprises removing a region of the plurality of graphene layers so as to expose an exposed silicon terminated face portion and then forming the semiconducting-type graphene layer on the exposed silicon terminated face portion. withdrawn
The method of Claim 11, wherein the step of forming a semimetallic-type graphene layer comprises the steps of: (a) evaporating silicon from a selected surface of the silicon carbide crystal thereby forming a graphene layer; and (b) passivating a portion of the selected surface of the silicon carbide crystal, thereby breaking chemical bonds between the p ortion of the selected surface and the Application No. 14/345,093 Amendment dated 07/02/2015 Reply to Office Action dated 03/02/2015 Page 5 of 8 silicon carbide crystal so that the selected surface becomes semimetallic-type graphene. withdrawn
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
A silicon carbide crystal is masked and etched (e.g., oxygen plasma etching) to form a raised portion with opposing sidewalls. The crystal is then annealed (1000–2000 °C, partial vacuum) causing silicon evaporation to form a layer 0-type graphene (buffer layer) on the silicon-terminated face and layer 1-type graphene on the non-silicon-terminated sidewalls. A dielectric insulator and metal gate layer are deposited on the layer 0-type graphene, and source/drain metal contacts are deposited on the layer 1-type graphene sidewall regions.
5 materials2 process steps
At least two graphene layers (layer 0-type bonded to SiC and layer 1-type on top) are grown on the silicon-terminated face of a SiC crystal via a first anneal with silicon evaporation. A region is etched (e.g., oxygen plasma) to expose the SiC surface. A second anneal grows a new layer 0-type graphene on the exposed portion, acting as the semiconductor channel. A gate structure is deposited on the new layer 0-type graphene and source/drain contacts on the remaining layer 1-type graphene.
5 materials2 process steps
A graphene buffer layer is grown on the silicon-terminated face of a SiC crystal. The SiC surface is then passivated in a hydrogen gas environment (1 atm H2, ~550 °C, ~75 min), breaking SiC-graphene bonds and converting the layer 0-type graphene to quasi-free-standing semimetallic layer 0*-type (passivated graphene). An opening is etched to expose SiC, and a second anneal grows a new layer 0-type semiconducting graphene on the exposed SiC. A gate structure is deposited on the new layer 0-type graphene and source/drain contacts on the layer 0*-type graphene. The layer 0*-type graphene can be converted back to layer 0-type by heating in a hydrogen-poor environment (e.g., ~900 °C, partial vacuum).
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor on SiC
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
band gap of layer 0-type graphene bonded to silicon-terminated SiC face | 0.3–0.5 eV | C |
Temperature | 1000–2000 °C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,171,907Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 C, the resulting crystal 11 0 is subjected to an annealing process (e.g., by heating it to a temperature of between 1000 ° C and 2000 ° C in a partial …
FIGS. 2A-2D are schematic diagrams demonstrating a flat embodiment. [0017]
FIGS. 3A-3E are schematic diagrams demonstrating a passivated layer embodiment. Attorney Docket No. G009.P 061U₁ 3 Customer No. 2
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor, comprising: (a) a silicon carbide crystal having a silicon terminated face; (b) a semiconducting-type graphene layer bonded to the silicon terminated face; (c) a first semimetallic-type graphene layer contiguous with a first portion of the semiconducting-type graphene layer; (d) a second semimetallic-type graphene layer contiguous with a second portion of the semiconducting-type graphene l ayer that is spaced apart from the first portion; (e) an insulator layer disposed on a portion of the semiconducting-type graphene layer; and (f) a gate conductive layer disposed on the insulator layer and spaced apart from the semiconducting-type graphene layer.
The transistor of Claim 1, wherein the semiconducting-type graphene layer comprises a layer 0-type graphene.
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer comprises a layer 1-type graphene.
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer is formed adjacent to a non-silicon terminated face of the silicon carbide crystal.
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer is formed on a layer 0- type graphene layer. withdrawn
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer comprises passivated graphene. withdrawn
The transistor of Claim 1, wherein the gate conductive layer comprises a metal.
The transistor of Claim 1, further comprising: (a) a metal source contact affixed to the first semimetallic-type graphene layer; and (b) a metal drain contact affixed to the second semimetallic-type graphene layer.
A method of making a transistor, comprising the steps of: (a) forming a semiconducting-type graphene layer on a silicon terminated face of a silicon carbide crystal; Application No. 14/345,093 Amendment dated 07/02/2015 Reply to Office Action dated 03/02/2015 Page 4 of 8 (b) forming at least one semimetallic-type graphene layer adjacent to the silicon carbide crystal so that the semimetallic-type graphene layer is contiguous with the semiconducting-type graphene layer; (c) applying an insulator layer on a portion of the semiconducting layer; and (d) applying a conductor layer to the insulator layer.
The method of Claim 11, wherein the step of forming a semiconducting-type graphene layer comprises evaporating silicon from the silicon carbide crystal.
The method of Claim 11, further comprising the step of forming a raised portion on the silicon carbide crystal so that the raised portion has a silicon terminated face and at least one sidewall extending transversely therefrom so that the sidewall is not silicon terminated, wherein the semimetallic-type graphene is disposed on the sidewall.
The method of Claim 11, wherein the step of forming at least one semimetallic-type graphene layer comprises forming a plurality of graphene layers on the silicon carbide crystal and wherein the step of forming a semiconducting-type graphene layer comprises removing a region of the plurality of graphene layers so as to expose an exposed silicon terminated face portion and then forming the semiconducting-type graphene layer on the exposed silicon terminated face portion. withdrawn
The method of Claim 11, wherein the step of forming a semimetallic-type graphene layer comprises the steps of: (a) evaporating silicon from a selected surface of the silicon carbide crystal thereby forming a graphene layer; and (b) passivating a portion of the selected surface of the silicon carbide crystal, thereby breaking chemical bonds between the p ortion of the selected surface and the Application No. 14/345,093 Amendment dated 07/02/2015 Reply to Office Action dated 03/02/2015 Page 5 of 8 silicon carbide crystal so that the selected surface becomes semimetallic-type graphene. withdrawn
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
A silicon carbide crystal is masked and etched (e.g., oxygen plasma etching) to form a raised portion with opposing sidewalls. The crystal is then annealed (1000–2000 °C, partial vacuum) causing silicon evaporation to form a layer 0-type graphene (buffer layer) on the silicon-terminated face and layer 1-type graphene on the non-silicon-terminated sidewalls. A dielectric insulator and metal gate layer are deposited on the layer 0-type graphene, and source/drain metal contacts are deposited on the layer 1-type graphene sidewall regions.
5 materials2 process steps
At least two graphene layers (layer 0-type bonded to SiC and layer 1-type on top) are grown on the silicon-terminated face of a SiC crystal via a first anneal with silicon evaporation. A region is etched (e.g., oxygen plasma) to expose the SiC surface. A second anneal grows a new layer 0-type graphene on the exposed portion, acting as the semiconductor channel. A gate structure is deposited on the new layer 0-type graphene and source/drain contacts on the remaining layer 1-type graphene.
5 materials2 process steps
A graphene buffer layer is grown on the silicon-terminated face of a SiC crystal. The SiC surface is then passivated in a hydrogen gas environment (1 atm H2, ~550 °C, ~75 min), breaking SiC-graphene bonds and converting the layer 0-type graphene to quasi-free-standing semimetallic layer 0*-type (passivated graphene). An opening is etched to expose SiC, and a second anneal grows a new layer 0-type semiconducting graphene on the exposed SiC. A gate structure is deposited on the new layer 0-type graphene and source/drain contacts on the layer 0*-type graphene. The layer 0*-type graphene can be converted back to layer 0-type by heating in a hydrogen-poor environment (e.g., ~900 °C, partial vacuum).
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor on SiC
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
band gap of layer 0-type graphene bonded to silicon-terminated SiC face | 0.3–0.5 eV | C |
Temperature | 1000–2000 °C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,171,907Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 C, the resulting crystal 11 0 is subjected to an annealing process (e.g., by heating it to a temperature of between 1000 ° C and 2000 ° C in a partial …
FIGS. 2A-2D are schematic diagrams demonstrating a flat embodiment. [0017]
FIGS. 3A-3E are schematic diagrams demonstrating a passivated layer embodiment. Attorney Docket No. G009.P 061U₁ 3 Customer No. 2
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor, comprising: (a) a silicon carbide crystal having a silicon terminated face; (b) a semiconducting-type graphene layer bonded to the silicon terminated face; (c) a first semimetallic-type graphene layer contiguous with a first portion of the semiconducting-type graphene layer; (d) a second semimetallic-type graphene layer contiguous with a second portion of the semiconducting-type graphene l ayer that is spaced apart from the first portion; (e) an insulator layer disposed on a portion of the semiconducting-type graphene layer; and (f) a gate conductive layer disposed on the insulator layer and spaced apart from the semiconducting-type graphene layer.
The transistor of Claim 1, wherein the semiconducting-type graphene layer comprises a layer 0-type graphene.
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer comprises a layer 1-type graphene.
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer is formed adjacent to a non-silicon terminated face of the silicon carbide crystal.
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer is formed on a layer 0- type graphene layer. withdrawn
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer comprises passivated graphene. withdrawn
The transistor of Claim 1, wherein the gate conductive layer comprises a metal.
The transistor of Claim 1, further comprising: (a) a metal source contact affixed to the first semimetallic-type graphene layer; and (b) a metal drain contact affixed to the second semimetallic-type graphene layer.
A method of making a transistor, comprising the steps of: (a) forming a semiconducting-type graphene layer on a silicon terminated face of a silicon carbide crystal; Application No. 14/345,093 Amendment dated 07/02/2015 Reply to Office Action dated 03/02/2015 Page 4 of 8 (b) forming at least one semimetallic-type graphene layer adjacent to the silicon carbide crystal so that the semimetallic-type graphene layer is contiguous with the semiconducting-type graphene layer; (c) applying an insulator layer on a portion of the semiconducting layer; and (d) applying a conductor layer to the insulator layer.
The method of Claim 11, wherein the step of forming a semiconducting-type graphene layer comprises evaporating silicon from the silicon carbide crystal.
The method of Claim 11, further comprising the step of forming a raised portion on the silicon carbide crystal so that the raised portion has a silicon terminated face and at least one sidewall extending transversely therefrom so that the sidewall is not silicon terminated, wherein the semimetallic-type graphene is disposed on the sidewall.
The method of Claim 11, wherein the step of forming at least one semimetallic-type graphene layer comprises forming a plurality of graphene layers on the silicon carbide crystal and wherein the step of forming a semiconducting-type graphene layer comprises removing a region of the plurality of graphene layers so as to expose an exposed silicon terminated face portion and then forming the semiconducting-type graphene layer on the exposed silicon terminated face portion. withdrawn
The method of Claim 11, wherein the step of forming a semimetallic-type graphene layer comprises the steps of: (a) evaporating silicon from a selected surface of the silicon carbide crystal thereby forming a graphene layer; and (b) passivating a portion of the selected surface of the silicon carbide crystal, thereby breaking chemical bonds between the p ortion of the selected surface and the Application No. 14/345,093 Amendment dated 07/02/2015 Reply to Office Action dated 03/02/2015 Page 5 of 8 silicon carbide crystal so that the selected surface becomes semimetallic-type graphene. withdrawn
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
A silicon carbide crystal is masked and etched (e.g., oxygen plasma etching) to form a raised portion with opposing sidewalls. The crystal is then annealed (1000–2000 °C, partial vacuum) causing silicon evaporation to form a layer 0-type graphene (buffer layer) on the silicon-terminated face and layer 1-type graphene on the non-silicon-terminated sidewalls. A dielectric insulator and metal gate layer are deposited on the layer 0-type graphene, and source/drain metal contacts are deposited on the layer 1-type graphene sidewall regions.
5 materials2 process steps
At least two graphene layers (layer 0-type bonded to SiC and layer 1-type on top) are grown on the silicon-terminated face of a SiC crystal via a first anneal with silicon evaporation. A region is etched (e.g., oxygen plasma) to expose the SiC surface. A second anneal grows a new layer 0-type graphene on the exposed portion, acting as the semiconductor channel. A gate structure is deposited on the new layer 0-type graphene and source/drain contacts on the remaining layer 1-type graphene.
5 materials2 process steps
A graphene buffer layer is grown on the silicon-terminated face of a SiC crystal. The SiC surface is then passivated in a hydrogen gas environment (1 atm H2, ~550 °C, ~75 min), breaking SiC-graphene bonds and converting the layer 0-type graphene to quasi-free-standing semimetallic layer 0*-type (passivated graphene). An opening is etched to expose SiC, and a second anneal grows a new layer 0-type semiconducting graphene on the exposed SiC. A gate structure is deposited on the new layer 0-type graphene and source/drain contacts on the layer 0*-type graphene. The layer 0*-type graphene can be converted back to layer 0-type by heating in a hydrogen-poor environment (e.g., ~900 °C, partial vacuum).
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor on SiC
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
band gap of layer 0-type graphene bonded to silicon-terminated SiC face | 0.3–0.5 eV | C |
Temperature | 1000–2000 °C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,171,907Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 C, the resulting crystal 11 0 is subjected to an annealing process (e.g., by heating it to a temperature of between 1000 ° C and 2000 ° C in a partial …
FIGS. 2A-2D are schematic diagrams demonstrating a flat embodiment. [0017]
FIGS. 3A-3E are schematic diagrams demonstrating a passivated layer embodiment. Attorney Docket No. G009.P 061U₁ 3 Customer No. 2
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor, comprising: (a) a silicon carbide crystal having a silicon terminated face; (b) a semiconducting-type graphene layer bonded to the silicon terminated face; (c) a first semimetallic-type graphene layer contiguous with a first portion of the semiconducting-type graphene layer; (d) a second semimetallic-type graphene layer contiguous with a second portion of the semiconducting-type graphene l ayer that is spaced apart from the first portion; (e) an insulator layer disposed on a portion of the semiconducting-type graphene layer; and (f) a gate conductive layer disposed on the insulator layer and spaced apart from the semiconducting-type graphene layer.
The transistor of Claim 1, wherein the semiconducting-type graphene layer comprises a layer 0-type graphene.
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer comprises a layer 1-type graphene.
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer is formed adjacent to a non-silicon terminated face of the silicon carbide crystal.
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer is formed on a layer 0- type graphene layer. withdrawn
The transistor of Claim 1, wherein at least one of the first semimetallic-type graphene layer and the second semimetallic-type graphene layer comprises passivated graphene. withdrawn
The transistor of Claim 1, wherein the gate conductive layer comprises a metal.
The transistor of Claim 1, further comprising: (a) a metal source contact affixed to the first semimetallic-type graphene layer; and (b) a metal drain contact affixed to the second semimetallic-type graphene layer.
A method of making a transistor, comprising the steps of: (a) forming a semiconducting-type graphene layer on a silicon terminated face of a silicon carbide crystal; Application No. 14/345,093 Amendment dated 07/02/2015 Reply to Office Action dated 03/02/2015 Page 4 of 8 (b) forming at least one semimetallic-type graphene layer adjacent to the silicon carbide crystal so that the semimetallic-type graphene layer is contiguous with the semiconducting-type graphene layer; (c) applying an insulator layer on a portion of the semiconducting layer; and (d) applying a conductor layer to the insulator layer.
The method of Claim 11, wherein the step of forming a semiconducting-type graphene layer comprises evaporating silicon from the silicon carbide crystal.
The method of Claim 11, further comprising the step of forming a raised portion on the silicon carbide crystal so that the raised portion has a silicon terminated face and at least one sidewall extending transversely therefrom so that the sidewall is not silicon terminated, wherein the semimetallic-type graphene is disposed on the sidewall.
The method of Claim 11, wherein the step of forming at least one semimetallic-type graphene layer comprises forming a plurality of graphene layers on the silicon carbide crystal and wherein the step of forming a semiconducting-type graphene layer comprises removing a region of the plurality of graphene layers so as to expose an exposed silicon terminated face portion and then forming the semiconducting-type graphene layer on the exposed silicon terminated face portion. withdrawn
The method of Claim 11, wherein the step of forming a semimetallic-type graphene layer comprises the steps of: (a) evaporating silicon from a selected surface of the silicon carbide crystal thereby forming a graphene layer; and (b) passivating a portion of the selected surface of the silicon carbide crystal, thereby breaking chemical bonds between the p ortion of the selected surface and the Application No. 14/345,093 Amendment dated 07/02/2015 Reply to Office Action dated 03/02/2015 Page 5 of 8 silicon carbide crystal so that the selected surface becomes semimetallic-type graphene. withdrawn
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials1 process step
A silicon carbide crystal is masked and etched (e.g., oxygen plasma etching) to form a raised portion with opposing sidewalls. The crystal is then annealed (1000–2000 °C, partial vacuum) causing silicon evaporation to form a layer 0-type graphene (buffer layer) on the silicon-terminated face and layer 1-type graphene on the non-silicon-terminated sidewalls. A dielectric insulator and metal gate layer are deposited on the layer 0-type graphene, and source/drain metal contacts are deposited on the layer 1-type graphene sidewall regions.
5 materials2 process steps
At least two graphene layers (layer 0-type bonded to SiC and layer 1-type on top) are grown on the silicon-terminated face of a SiC crystal via a first anneal with silicon evaporation. A region is etched (e.g., oxygen plasma) to expose the SiC surface. A second anneal grows a new layer 0-type graphene on the exposed portion, acting as the semiconductor channel. A gate structure is deposited on the new layer 0-type graphene and source/drain contacts on the remaining layer 1-type graphene.
5 materials2 process steps
A graphene buffer layer is grown on the silicon-terminated face of a SiC crystal. The SiC surface is then passivated in a hydrogen gas environment (1 atm H2, ~550 °C, ~75 min), breaking SiC-graphene bonds and converting the layer 0-type graphene to quasi-free-standing semimetallic layer 0*-type (passivated graphene). An opening is etched to expose SiC, and a second anneal grows a new layer 0-type semiconducting graphene on the exposed SiC. A gate structure is deposited on the new layer 0-type graphene and source/drain contacts on the layer 0*-type graphene. The layer 0*-type graphene can be converted back to layer 0-type by heating in a hydrogen-poor environment (e.g., ~900 °C, partial vacuum).
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor on SiC
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
band gap of layer 0-type graphene bonded to silicon-terminated SiC face | 0.3–0.5 eV | C |
Temperature | 1000–2000 °C |
Related documents with shared materials, methods, properties, or citations.
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