Patent
US 8,703,623WAFER BONDING TECHNIQUE IN NITRIDE SEMICONDUCTORS
Jinwook Chung, Han Wang, Tomas Palacios
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,703,623Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1C.
FIG. 2 is a scanning electron micrograph of a successfully processed bonding between a GaN 10 and Si carrier 14 wafers in accordance with the invention (False …
FIG. 3A. The A I GaN/GaN transistor structure 22 includes a GaN buffer layer 30 and an A l GaN layer 28 grown on the GaN buffer layer 30. To have access to the …
FIG. 4A illustrates HEMT 36 having a Si substrate 38 and a HSQ interlayer 40 formed on the substrate 38. An A l GaN layer 42 is formed on the HSQ interlayer …
FIG. 5G. The silicon dioxide layers 74 and 84 can be the HSQ interlayers described herein.
FIG. 6B shows a cross- section schematic view 164 of fabricated Si MOSFETs 160 and GaN HEMTs 162 and a plan-view 166 SEM image of the fabricated transistors …
FIG. 7 are graphs illustrating the performance of nitride-based devices; and FIGs. 8A- 8B are schematic diagrams illustrating two embodiments of power devices …
FIG. 8A. While the HSQ layer 120 will reduce the charge compensation effect of the p-type substrate 118 on the GaN channel 122, this layer 120 of H SQ can also …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor arrangement comprising. 2 one or more substrate structures; 3 one or more ni tride-based mate ri al structures for fabricating nitride-based devices 4 fabricated in dependently from said one or more substrate structures, 5 one or more intermediary layers having in sulating materials being directly 6 interposed between said one or more substrate structures and said one or more nitride- 7 based material structures, said one or more intermediary layers supporting the lattice 8 mismatch and thermal expansion coefficients between said one or more ni tride-based 9 material structures, and said one or more substrate structures. 1 2 The semiconductor arrangement of claim 1, where in said one 2 or more substrate structures comprise Si (100), Si (111), SiC, diamond, A 120 3, A l N, or 3 sapphire. 1
The semiconductor arrangement of claim 1, wherein said one or more 2 nitride-based material structures comprise A lxInyGazN. 1
The semiconductor arrangement of claim 1, where in said one 2 or more substrate structures have been locally removed to expose a buried structure 3 where devices are fabricated 820867 1 2 Attorney Docket No MIT 13414 U S App lic ation Se ri al No 12/475,740 1 5 The semiconductor arrangement of claim 1, wherein said one or more 2 intermediary layers comprise HSQ. 1
The semiconductor arrangement of claim 1, wherein said one or more 2 in termediary layers comprise si li con dioxide 1 7 The semiconductor arrangement of claim 1, wherein said one 2 or more substrate structures are doped p type 1
The semiconductor arrangement of claim 1, wherein said semiconductor 2 arrangement comprises a N-face GaN transistor structure. 1 9 (Orig in al) The semiconductor arrangement of claim 4, where in said semiconductor 2 arrangement comprises a GaN-based power device structure 1
The semiconductor arrangement of claim 1, wherein said one 2 or more ni tride-based material structures comprise A lxInyGaz N/GaN transistor structures. 1
A method of fabricating a ni tride-base device compris ing: 2 providing one or more substrate structures, 820867 1 3 SVG 12475740.10-16-2013.HMUX₄KUWPXXIFW3.CLM10336567.1.1512.154.2167.240.svg 0.287 2.183 Chemistry Black and white 3 provid in g one or more nitride-based material structures fabricated in dependently 4 from said one or more substrate structures, and 5 6 directly positioning one or more intermediary layers hav ing in sulating materials 7 between said one or more substrate structures and said one or more nitride-based material 8 structures, said one or more in termediary layers supporting the lattice mismatch and 9 thermal expansion coefficients between said one or more ni tride-based material structures 10 and said one or more substrate structures 1
The method of claim 12, where in said one or more substrate 2 structures comprise Si (100), Si (111), SiC, A 120 3, A l N, diamond or sapphire 2955
The method of claim 12, where in said one or more nitride-based material 2 structures comprise A lxInyGazN 1 15 The method of claim 12, wherein said one or more substrate 2 structures have been locally removed to expose a bur i ed structure where devices are SVG 12475740.10-16-2013.HMUX₄KUWPXXIFW3.CLM10336567.17.275.2169.630.2220.svg 0.17 1.183 Chemistry Black and white 1 16 The method of claim 12, where in said one or more intermediary layers 2 comprise HSQ. 1 17 (Orig in al) The method of claim 12, wherein said one or more intermediary layers 2 comprise s ili con dioxide 820867 1 4 SVG 12475740.10-16-2013.HMUX₄KUWPXXIFW3.CLM10336568.1.1507.155.2165.240.svg 0.283 2.193 Graph Black and white 1 18. The method of cla im 12, where in said one or more substrate 2 structures are doped p-type 1
The method of claim 12, where in said one or more nitride-based material 2 structures comprise A lxInyGaz N/GaN transistor structures 1
(Orig in al) The method of claim 15, wherein said device comprises a N-face GaN 2 transistor.
The method of claim 15, wherein said device comprises a GaN-based 2 power device. 1
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor arrangement with nitride-based material on substrate via insulating intermediary layer
N-face GaN transistor
Materials described outside the worked examples.
substrate (Si(100), Si(111), SiC, diamond, Al₂O3, AlN, sapphire)
nitride-based material structure
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a scanning electron micrograph of a successfully processed bonding between a GaN 10 and Si carrier 14 wafers in accordance with the invention (False …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Lattice Mismatch | 17 % | GaNsubstrate (Si(100), Si(111), SiC, diamond, Al₂O3, AlN, sapphire) |
Related documents with shared materials, methods, properties, or citations.
ENHANCEMENT MODE GALLIUM NITRIDE BASED TRANSISTOR DEVICE HAVING A P TYPE METAL OXIDE LAYER COMPRISING PLURALITY OF EXTENSION PARTS EXTENDING INTO THE EPITAXIAL STACKED LAYER
GATE STRUCTURES TO ENABLE LOWER SUBTHRESHOLD SLOPE IN GALLIUM NITRIDE-BASED TRANSISTORS
Patent
Atlas literature
Patent
US 8,703,623Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1C.
FIG. 2 is a scanning electron micrograph of a successfully processed bonding between a GaN 10 and Si carrier 14 wafers in accordance with the invention (False …
FIG. 3A. The A I GaN/GaN transistor structure 22 includes a GaN buffer layer 30 and an A l GaN layer 28 grown on the GaN buffer layer 30. To have access to the …
FIG. 4A illustrates HEMT 36 having a Si substrate 38 and a HSQ interlayer 40 formed on the substrate 38. An A l GaN layer 42 is formed on the HSQ interlayer …
FIG. 5G. The silicon dioxide layers 74 and 84 can be the HSQ interlayers described herein.
FIG. 6B shows a cross- section schematic view 164 of fabricated Si MOSFETs 160 and GaN HEMTs 162 and a plan-view 166 SEM image of the fabricated transistors …
FIG. 7 are graphs illustrating the performance of nitride-based devices; and FIGs. 8A- 8B are schematic diagrams illustrating two embodiments of power devices …
FIG. 8A. While the HSQ layer 120 will reduce the charge compensation effect of the p-type substrate 118 on the GaN channel 122, this layer 120 of H SQ can also …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor arrangement comprising. 2 one or more substrate structures; 3 one or more ni tride-based mate ri al structures for fabricating nitride-based devices 4 fabricated in dependently from said one or more substrate structures, 5 one or more intermediary layers having in sulating materials being directly 6 interposed between said one or more substrate structures and said one or more nitride- 7 based material structures, said one or more intermediary layers supporting the lattice 8 mismatch and thermal expansion coefficients between said one or more ni tride-based 9 material structures, and said one or more substrate structures. 1 2 The semiconductor arrangement of claim 1, where in said one 2 or more substrate structures comprise Si (100), Si (111), SiC, diamond, A 120 3, A l N, or 3 sapphire. 1
The semiconductor arrangement of claim 1, wherein said one or more 2 nitride-based material structures comprise A lxInyGazN. 1
The semiconductor arrangement of claim 1, where in said one 2 or more substrate structures have been locally removed to expose a buried structure 3 where devices are fabricated 820867 1 2 Attorney Docket No MIT 13414 U S App lic ation Se ri al No 12/475,740 1 5 The semiconductor arrangement of claim 1, wherein said one or more 2 intermediary layers comprise HSQ. 1
The semiconductor arrangement of claim 1, wherein said one or more 2 in termediary layers comprise si li con dioxide 1 7 The semiconductor arrangement of claim 1, wherein said one 2 or more substrate structures are doped p type 1
The semiconductor arrangement of claim 1, wherein said semiconductor 2 arrangement comprises a N-face GaN transistor structure. 1 9 (Orig in al) The semiconductor arrangement of claim 4, where in said semiconductor 2 arrangement comprises a GaN-based power device structure 1
The semiconductor arrangement of claim 1, wherein said one 2 or more ni tride-based material structures comprise A lxInyGaz N/GaN transistor structures. 1
A method of fabricating a ni tride-base device compris ing: 2 providing one or more substrate structures, 820867 1 3 SVG 12475740.10-16-2013.HMUX₄KUWPXXIFW3.CLM10336567.1.1512.154.2167.240.svg 0.287 2.183 Chemistry Black and white 3 provid in g one or more nitride-based material structures fabricated in dependently 4 from said one or more substrate structures, and 5 6 directly positioning one or more intermediary layers hav ing in sulating materials 7 between said one or more substrate structures and said one or more nitride-based material 8 structures, said one or more in termediary layers supporting the lattice mismatch and 9 thermal expansion coefficients between said one or more ni tride-based material structures 10 and said one or more substrate structures 1
The method of claim 12, where in said one or more substrate 2 structures comprise Si (100), Si (111), SiC, A 120 3, A l N, diamond or sapphire 2955
The method of claim 12, where in said one or more nitride-based material 2 structures comprise A lxInyGazN 1 15 The method of claim 12, wherein said one or more substrate 2 structures have been locally removed to expose a bur i ed structure where devices are SVG 12475740.10-16-2013.HMUX₄KUWPXXIFW3.CLM10336567.17.275.2169.630.2220.svg 0.17 1.183 Chemistry Black and white 1 16 The method of claim 12, where in said one or more intermediary layers 2 comprise HSQ. 1 17 (Orig in al) The method of claim 12, wherein said one or more intermediary layers 2 comprise s ili con dioxide 820867 1 4 SVG 12475740.10-16-2013.HMUX₄KUWPXXIFW3.CLM10336568.1.1507.155.2165.240.svg 0.283 2.193 Graph Black and white 1 18. The method of cla im 12, where in said one or more substrate 2 structures are doped p-type 1
The method of claim 12, where in said one or more nitride-based material 2 structures comprise A lxInyGaz N/GaN transistor structures 1
(Orig in al) The method of claim 15, wherein said device comprises a N-face GaN 2 transistor.
The method of claim 15, wherein said device comprises a GaN-based 2 power device. 1
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor arrangement with nitride-based material on substrate via insulating intermediary layer
N-face GaN transistor
Materials described outside the worked examples.
substrate (Si(100), Si(111), SiC, diamond, Al₂O3, AlN, sapphire)
nitride-based material structure
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a scanning electron micrograph of a successfully processed bonding between a GaN 10 and Si carrier 14 wafers in accordance with the invention (False …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Lattice Mismatch | 17 % | GaNsubstrate (Si(100), Si(111), SiC, diamond, Al₂O3, AlN, sapphire) |
Related documents with shared materials, methods, properties, or citations.
ENHANCEMENT MODE GALLIUM NITRIDE BASED TRANSISTOR DEVICE HAVING A P TYPE METAL OXIDE LAYER COMPRISING PLURALITY OF EXTENSION PARTS EXTENDING INTO THE EPITAXIAL STACKED LAYER
GATE STRUCTURES TO ENABLE LOWER SUBTHRESHOLD SLOPE IN GALLIUM NITRIDE-BASED TRANSISTORS
Patent
Atlas literature
Patent
US 8,703,623Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1C.
FIG. 2 is a scanning electron micrograph of a successfully processed bonding between a GaN 10 and Si carrier 14 wafers in accordance with the invention (False …
FIG. 3A. The A I GaN/GaN transistor structure 22 includes a GaN buffer layer 30 and an A l GaN layer 28 grown on the GaN buffer layer 30. To have access to the …
FIG. 4A illustrates HEMT 36 having a Si substrate 38 and a HSQ interlayer 40 formed on the substrate 38. An A l GaN layer 42 is formed on the HSQ interlayer …
FIG. 5G. The silicon dioxide layers 74 and 84 can be the HSQ interlayers described herein.
FIG. 6B shows a cross- section schematic view 164 of fabricated Si MOSFETs 160 and GaN HEMTs 162 and a plan-view 166 SEM image of the fabricated transistors …
FIG. 7 are graphs illustrating the performance of nitride-based devices; and FIGs. 8A- 8B are schematic diagrams illustrating two embodiments of power devices …
FIG. 8A. While the HSQ layer 120 will reduce the charge compensation effect of the p-type substrate 118 on the GaN channel 122, this layer 120 of H SQ can also …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor arrangement comprising. 2 one or more substrate structures; 3 one or more ni tride-based mate ri al structures for fabricating nitride-based devices 4 fabricated in dependently from said one or more substrate structures, 5 one or more intermediary layers having in sulating materials being directly 6 interposed between said one or more substrate structures and said one or more nitride- 7 based material structures, said one or more intermediary layers supporting the lattice 8 mismatch and thermal expansion coefficients between said one or more ni tride-based 9 material structures, and said one or more substrate structures. 1 2 The semiconductor arrangement of claim 1, where in said one 2 or more substrate structures comprise Si (100), Si (111), SiC, diamond, A 120 3, A l N, or 3 sapphire. 1
The semiconductor arrangement of claim 1, wherein said one or more 2 nitride-based material structures comprise A lxInyGazN. 1
The semiconductor arrangement of claim 1, where in said one 2 or more substrate structures have been locally removed to expose a buried structure 3 where devices are fabricated 820867 1 2 Attorney Docket No MIT 13414 U S App lic ation Se ri al No 12/475,740 1 5 The semiconductor arrangement of claim 1, wherein said one or more 2 intermediary layers comprise HSQ. 1
The semiconductor arrangement of claim 1, wherein said one or more 2 in termediary layers comprise si li con dioxide 1 7 The semiconductor arrangement of claim 1, wherein said one 2 or more substrate structures are doped p type 1
The semiconductor arrangement of claim 1, wherein said semiconductor 2 arrangement comprises a N-face GaN transistor structure. 1 9 (Orig in al) The semiconductor arrangement of claim 4, where in said semiconductor 2 arrangement comprises a GaN-based power device structure 1
The semiconductor arrangement of claim 1, wherein said one 2 or more ni tride-based material structures comprise A lxInyGaz N/GaN transistor structures. 1
A method of fabricating a ni tride-base device compris ing: 2 providing one or more substrate structures, 820867 1 3 SVG 12475740.10-16-2013.HMUX₄KUWPXXIFW3.CLM10336567.1.1512.154.2167.240.svg 0.287 2.183 Chemistry Black and white 3 provid in g one or more nitride-based material structures fabricated in dependently 4 from said one or more substrate structures, and 5 6 directly positioning one or more intermediary layers hav ing in sulating materials 7 between said one or more substrate structures and said one or more nitride-based material 8 structures, said one or more in termediary layers supporting the lattice mismatch and 9 thermal expansion coefficients between said one or more ni tride-based material structures 10 and said one or more substrate structures 1
The method of claim 12, where in said one or more substrate 2 structures comprise Si (100), Si (111), SiC, A 120 3, A l N, diamond or sapphire 2955
The method of claim 12, where in said one or more nitride-based material 2 structures comprise A lxInyGazN 1 15 The method of claim 12, wherein said one or more substrate 2 structures have been locally removed to expose a bur i ed structure where devices are SVG 12475740.10-16-2013.HMUX₄KUWPXXIFW3.CLM10336567.17.275.2169.630.2220.svg 0.17 1.183 Chemistry Black and white 1 16 The method of claim 12, where in said one or more intermediary layers 2 comprise HSQ. 1 17 (Orig in al) The method of claim 12, wherein said one or more intermediary layers 2 comprise s ili con dioxide 820867 1 4 SVG 12475740.10-16-2013.HMUX₄KUWPXXIFW3.CLM10336568.1.1507.155.2165.240.svg 0.283 2.193 Graph Black and white 1 18. The method of cla im 12, where in said one or more substrate 2 structures are doped p-type 1
The method of claim 12, where in said one or more nitride-based material 2 structures comprise A lxInyGaz N/GaN transistor structures 1
(Orig in al) The method of claim 15, wherein said device comprises a N-face GaN 2 transistor.
The method of claim 15, wherein said device comprises a GaN-based 2 power device. 1
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor arrangement with nitride-based material on substrate via insulating intermediary layer
N-face GaN transistor
Materials described outside the worked examples.
substrate (Si(100), Si(111), SiC, diamond, Al₂O3, AlN, sapphire)
nitride-based material structure
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a scanning electron micrograph of a successfully processed bonding between a GaN 10 and Si carrier 14 wafers in accordance with the invention (False …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Lattice Mismatch | 17 % | GaNsubstrate (Si(100), Si(111), SiC, diamond, Al₂O3, AlN, sapphire) |
Related documents with shared materials, methods, properties, or citations.
ENHANCEMENT MODE GALLIUM NITRIDE BASED TRANSISTOR DEVICE HAVING A P TYPE METAL OXIDE LAYER COMPRISING PLURALITY OF EXTENSION PARTS EXTENDING INTO THE EPITAXIAL STACKED LAYER
GATE STRUCTURES TO ENABLE LOWER SUBTHRESHOLD SLOPE IN GALLIUM NITRIDE-BASED TRANSISTORS
Patent
Atlas literature
Patent
US 8,703,623Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1C.
FIG. 2 is a scanning electron micrograph of a successfully processed bonding between a GaN 10 and Si carrier 14 wafers in accordance with the invention (False …
FIG. 3A. The A I GaN/GaN transistor structure 22 includes a GaN buffer layer 30 and an A l GaN layer 28 grown on the GaN buffer layer 30. To have access to the …
FIG. 4A illustrates HEMT 36 having a Si substrate 38 and a HSQ interlayer 40 formed on the substrate 38. An A l GaN layer 42 is formed on the HSQ interlayer …
FIG. 5G. The silicon dioxide layers 74 and 84 can be the HSQ interlayers described herein.
FIG. 6B shows a cross- section schematic view 164 of fabricated Si MOSFETs 160 and GaN HEMTs 162 and a plan-view 166 SEM image of the fabricated transistors …
FIG. 7 are graphs illustrating the performance of nitride-based devices; and FIGs. 8A- 8B are schematic diagrams illustrating two embodiments of power devices …
FIG. 8A. While the HSQ layer 120 will reduce the charge compensation effect of the p-type substrate 118 on the GaN channel 122, this layer 120 of H SQ can also …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor arrangement comprising. 2 one or more substrate structures; 3 one or more ni tride-based mate ri al structures for fabricating nitride-based devices 4 fabricated in dependently from said one or more substrate structures, 5 one or more intermediary layers having in sulating materials being directly 6 interposed between said one or more substrate structures and said one or more nitride- 7 based material structures, said one or more intermediary layers supporting the lattice 8 mismatch and thermal expansion coefficients between said one or more ni tride-based 9 material structures, and said one or more substrate structures. 1 2 The semiconductor arrangement of claim 1, where in said one 2 or more substrate structures comprise Si (100), Si (111), SiC, diamond, A 120 3, A l N, or 3 sapphire. 1
The semiconductor arrangement of claim 1, wherein said one or more 2 nitride-based material structures comprise A lxInyGazN. 1
The semiconductor arrangement of claim 1, where in said one 2 or more substrate structures have been locally removed to expose a buried structure 3 where devices are fabricated 820867 1 2 Attorney Docket No MIT 13414 U S App lic ation Se ri al No 12/475,740 1 5 The semiconductor arrangement of claim 1, wherein said one or more 2 intermediary layers comprise HSQ. 1
The semiconductor arrangement of claim 1, wherein said one or more 2 in termediary layers comprise si li con dioxide 1 7 The semiconductor arrangement of claim 1, wherein said one 2 or more substrate structures are doped p type 1
The semiconductor arrangement of claim 1, wherein said semiconductor 2 arrangement comprises a N-face GaN transistor structure. 1 9 (Orig in al) The semiconductor arrangement of claim 4, where in said semiconductor 2 arrangement comprises a GaN-based power device structure 1
The semiconductor arrangement of claim 1, wherein said one 2 or more ni tride-based material structures comprise A lxInyGaz N/GaN transistor structures. 1
A method of fabricating a ni tride-base device compris ing: 2 providing one or more substrate structures, 820867 1 3 SVG 12475740.10-16-2013.HMUX₄KUWPXXIFW3.CLM10336567.1.1512.154.2167.240.svg 0.287 2.183 Chemistry Black and white 3 provid in g one or more nitride-based material structures fabricated in dependently 4 from said one or more substrate structures, and 5 6 directly positioning one or more intermediary layers hav ing in sulating materials 7 between said one or more substrate structures and said one or more nitride-based material 8 structures, said one or more in termediary layers supporting the lattice mismatch and 9 thermal expansion coefficients between said one or more ni tride-based material structures 10 and said one or more substrate structures 1
The method of claim 12, where in said one or more substrate 2 structures comprise Si (100), Si (111), SiC, A 120 3, A l N, diamond or sapphire 2955
The method of claim 12, where in said one or more nitride-based material 2 structures comprise A lxInyGazN 1 15 The method of claim 12, wherein said one or more substrate 2 structures have been locally removed to expose a bur i ed structure where devices are SVG 12475740.10-16-2013.HMUX₄KUWPXXIFW3.CLM10336567.17.275.2169.630.2220.svg 0.17 1.183 Chemistry Black and white 1 16 The method of claim 12, where in said one or more intermediary layers 2 comprise HSQ. 1 17 (Orig in al) The method of claim 12, wherein said one or more intermediary layers 2 comprise s ili con dioxide 820867 1 4 SVG 12475740.10-16-2013.HMUX₄KUWPXXIFW3.CLM10336568.1.1507.155.2165.240.svg 0.283 2.193 Graph Black and white 1 18. The method of cla im 12, where in said one or more substrate 2 structures are doped p-type 1
The method of claim 12, where in said one or more nitride-based material 2 structures comprise A lxInyGaz N/GaN transistor structures 1
(Orig in al) The method of claim 15, wherein said device comprises a N-face GaN 2 transistor.
The method of claim 15, wherein said device comprises a GaN-based 2 power device. 1
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor arrangement with nitride-based material on substrate via insulating intermediary layer
N-face GaN transistor
Materials described outside the worked examples.
substrate (Si(100), Si(111), SiC, diamond, Al₂O3, AlN, sapphire)
nitride-based material structure
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a scanning electron micrograph of a successfully processed bonding between a GaN 10 and Si carrier 14 wafers in accordance with the invention (False …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Lattice Mismatch | 17 % | GaNsubstrate (Si(100), Si(111), SiC, diamond, Al₂O3, AlN, sapphire) |
Related documents with shared materials, methods, properties, or citations.
ENHANCEMENT MODE GALLIUM NITRIDE BASED TRANSISTOR DEVICE HAVING A P TYPE METAL OXIDE LAYER COMPRISING PLURALITY OF EXTENSION PARTS EXTENDING INTO THE EPITAXIAL STACKED LAYER
GATE STRUCTURES TO ENABLE LOWER SUBTHRESHOLD SLOPE IN GALLIUM NITRIDE-BASED TRANSISTORS
GaN-based power device
AlxInyGazN/GaN transistor structure
Ga-face GaN/AlxInyGazN transistor
N-face GaN/AlGaN HEMT
Ga-face AlGaN/GaN HEMT
AlxInyGazN
HSQ (hydrogen silsesquioxane)
silicon dioxide
SiO₂
GaN
HSQ (hydrogen silsesquioxane) intermediary/bonding layer
AlGaN
FIG. 3A. The A I GaN/GaN transistor structure 22 includes a GaN buffer layer 30 and an A l GaN layer 28 grown on the GaN buffer layer 30. To have access to the …
FIG. 6B shows a cross- section schematic view 164 of fabricated Si MOSFETs 160 and GaN HEMTs 162 and a plan-view 166 SEM image of the fabricated transistors …
FIG. 6B shows a cross- section schematic view 164 of fabricated Si MOSFETs 160 and GaN HEMTs 162 and a plan-view 166 SEM image of the fabricated transistors …
FIG. 7 are graphs illustrating the performance of nitride-based devices; and FIGs. 8A- 8B are schematic diagrams illustrating two embodiments of power devices …
Thermal Expansion Coefficient Mismatch | 55 % | GaNsubstrate (Si(100), Si(111), SiC, diamond, Al₂O3, AlN, sapphire) |
Dielectric Constant | 2.8 | HSQ (hydrogen silsesquioxane) intermediary/bonding layer |
Surface Roughness | ≤ 40 Å | HSQ (hydrogen silsesquioxane) intermediary/bonding layer |
Sheet Charge Density | 10000000000000 cm⁻² | nitride-based material structure |
Peak Electron Velocity | 25000000 cm/s | nitride-based material structure |
Breakdown Field Strength | 3 MV/cm | nitride-based material structure |
Thermal Conductivity | ≥ 1.5 W/cm·K | nitride-based material structure |
Fet Contact Resistance | ≤ 0.2 Ω·mm | GaN |
Fet Contact Resistance | 0.3–0.5 Ω·mm | AlGaN |
Voltage | ≥ 4 V | — |
GaN-based power device
AlxInyGazN/GaN transistor structure
Ga-face GaN/AlxInyGazN transistor
N-face GaN/AlGaN HEMT
Ga-face AlGaN/GaN HEMT
AlxInyGazN
HSQ (hydrogen silsesquioxane)
silicon dioxide
SiO₂
GaN
HSQ (hydrogen silsesquioxane) intermediary/bonding layer
AlGaN
FIG. 3A. The A I GaN/GaN transistor structure 22 includes a GaN buffer layer 30 and an A l GaN layer 28 grown on the GaN buffer layer 30. To have access to the …
FIG. 6B shows a cross- section schematic view 164 of fabricated Si MOSFETs 160 and GaN HEMTs 162 and a plan-view 166 SEM image of the fabricated transistors …
FIG. 6B shows a cross- section schematic view 164 of fabricated Si MOSFETs 160 and GaN HEMTs 162 and a plan-view 166 SEM image of the fabricated transistors …
FIG. 7 are graphs illustrating the performance of nitride-based devices; and FIGs. 8A- 8B are schematic diagrams illustrating two embodiments of power devices …
Thermal Expansion Coefficient Mismatch | 55 % | GaNsubstrate (Si(100), Si(111), SiC, diamond, Al₂O3, AlN, sapphire) |
Dielectric Constant | 2.8 | HSQ (hydrogen silsesquioxane) intermediary/bonding layer |
Surface Roughness | ≤ 40 Å | HSQ (hydrogen silsesquioxane) intermediary/bonding layer |
Sheet Charge Density | 10000000000000 cm⁻² | nitride-based material structure |
Peak Electron Velocity | 25000000 cm/s | nitride-based material structure |
Breakdown Field Strength | 3 MV/cm | nitride-based material structure |
Thermal Conductivity | ≥ 1.5 W/cm·K | nitride-based material structure |
Fet Contact Resistance | ≤ 0.2 Ω·mm | GaN |
Fet Contact Resistance | 0.3–0.5 Ω·mm | AlGaN |
Voltage | ≥ 4 V | — |
GaN-based power device
AlxInyGazN/GaN transistor structure
Ga-face GaN/AlxInyGazN transistor
N-face GaN/AlGaN HEMT
Ga-face AlGaN/GaN HEMT
AlxInyGazN
HSQ (hydrogen silsesquioxane)
silicon dioxide
SiO₂
GaN
HSQ (hydrogen silsesquioxane) intermediary/bonding layer
AlGaN
FIG. 3A. The A I GaN/GaN transistor structure 22 includes a GaN buffer layer 30 and an A l GaN layer 28 grown on the GaN buffer layer 30. To have access to the …
FIG. 6B shows a cross- section schematic view 164 of fabricated Si MOSFETs 160 and GaN HEMTs 162 and a plan-view 166 SEM image of the fabricated transistors …
FIG. 6B shows a cross- section schematic view 164 of fabricated Si MOSFETs 160 and GaN HEMTs 162 and a plan-view 166 SEM image of the fabricated transistors …
FIG. 7 are graphs illustrating the performance of nitride-based devices; and FIGs. 8A- 8B are schematic diagrams illustrating two embodiments of power devices …
Thermal Expansion Coefficient Mismatch | 55 % | GaNsubstrate (Si(100), Si(111), SiC, diamond, Al₂O3, AlN, sapphire) |
Dielectric Constant | 2.8 | HSQ (hydrogen silsesquioxane) intermediary/bonding layer |
Surface Roughness | ≤ 40 Å | HSQ (hydrogen silsesquioxane) intermediary/bonding layer |
Sheet Charge Density | 10000000000000 cm⁻² | nitride-based material structure |
Peak Electron Velocity | 25000000 cm/s | nitride-based material structure |
Breakdown Field Strength | 3 MV/cm | nitride-based material structure |
Thermal Conductivity | ≥ 1.5 W/cm·K | nitride-based material structure |
Fet Contact Resistance | ≤ 0.2 Ω·mm | GaN |
Fet Contact Resistance | 0.3–0.5 Ω·mm | AlGaN |
Voltage | ≥ 4 V | — |
GaN-based power device
AlxInyGazN/GaN transistor structure
Ga-face GaN/AlxInyGazN transistor
N-face GaN/AlGaN HEMT
Ga-face AlGaN/GaN HEMT
AlxInyGazN
HSQ (hydrogen silsesquioxane)
silicon dioxide
SiO₂
GaN
HSQ (hydrogen silsesquioxane) intermediary/bonding layer
AlGaN
FIG. 3A. The A I GaN/GaN transistor structure 22 includes a GaN buffer layer 30 and an A l GaN layer 28 grown on the GaN buffer layer 30. To have access to the …
FIG. 6B shows a cross- section schematic view 164 of fabricated Si MOSFETs 160 and GaN HEMTs 162 and a plan-view 166 SEM image of the fabricated transistors …
FIG. 6B shows a cross- section schematic view 164 of fabricated Si MOSFETs 160 and GaN HEMTs 162 and a plan-view 166 SEM image of the fabricated transistors …
FIG. 7 are graphs illustrating the performance of nitride-based devices; and FIGs. 8A- 8B are schematic diagrams illustrating two embodiments of power devices …
Thermal Expansion Coefficient Mismatch | 55 % | GaNsubstrate (Si(100), Si(111), SiC, diamond, Al₂O3, AlN, sapphire) |
Dielectric Constant | 2.8 | HSQ (hydrogen silsesquioxane) intermediary/bonding layer |
Surface Roughness | ≤ 40 Å | HSQ (hydrogen silsesquioxane) intermediary/bonding layer |
Sheet Charge Density | 10000000000000 cm⁻² | nitride-based material structure |
Peak Electron Velocity | 25000000 cm/s | nitride-based material structure |
Breakdown Field Strength | 3 MV/cm | nitride-based material structure |
Thermal Conductivity | ≥ 1.5 W/cm·K | nitride-based material structure |
Fet Contact Resistance | ≤ 0.2 Ω·mm | GaN |
Fet Contact Resistance | 0.3–0.5 Ω·mm | AlGaN |
Voltage | ≥ 4 V | — |