I. (C urrent ly A m ende d) A ch ip mu ltiprocessor, com prising; g p fi rst group of processor cores disposed on a die, whe r ein the g-first group o f processor c o res includes g raphene-containing computation elements;[[a ndfl a second gr oup o f processor cores disposed on the die, wherein the ty t sec pnd grou p of processor c o res includes a lower percentage of the graphene-co ntai ning com putation elements than the----g-p ir st group of processor cores; and a third group of pr tcessor cnres disposd o the die. herein the third group Qf proessor cores inclu des a lower prcentage of the gaphen-continng computati on elements _ han the second group of processor core s, !dl wherein. the first g roup of processor c o res a re hig h-speed processor c o res relative to the second eroup ofperoce sso r cores and the third gouof poessor coes. the first gro u p of processor c o res are configured to operate when a t least some p qotessor c of the second group of processor cores and the third g r oup of processor cores are c onfi gured to be gated j [and 1] r cy ra e g u p p c y n g -- p a ch processor core of the third g roup of processor coressarrang<ed_ to fcilithe thennal isolation o f e ach processor core of th fratjgrup of processor cores such that at least a processor core of the third g roup of processor cores is disposed in between every two ad ja cent cores of the f irs t gro up of processor cores, and to f acili t ate th erm al iso l ation of each processor core of th e second gr o up of processor cores such that at least another processor core of the th ird group of processor cores is disposed in between every two adjacent cores of the second group of processor cores, the facilitation of the thermal isolation of each processor core of the first group of processor cores and the second gro up of processor cores reduces an effect of le akage gyfrgid at is a ssoiated with the a nlieGCea~ta 1i}g ? tast leme'L"# d at leaston ro sor cor e ofthe sec ond ro frocesororesnd ales te procssetore fthethiraron f rocessor cores are dis o osed be t wee n eve t processorq h i g,m s t Up y t wo::.: adjacent cores of the first group of processor cores.

-5. Canceled

Canceled

6, (C urrently Amen ded) The chip mu lti p roc e ssor of claim [[2]1L wh e rein-p the f irst group of g processor cores are confi g ured to operate sequentially. Currently amended

(C urre ntly A mende d) Th e chip multipro ce ssor of claim [[6]] 1, wherein operation of an active processor core of-- the first group of p processor cores is t ransferre d to another processor core of the g-first gr o up o f processor cores p---based on an operati ng te m perature of the a c tive processor core. Currently amended

--- 9. Canceled

(C urrently Amended) T he chip mu ltip r ocess o r of c laim 1, wherein at least o ne processor core of t he onermer-gh-speed-first gro up of processor cores is disposed on an edge of the die. Currently amended

13, (Currently Amonded) TIh e chi p multip rocess or of cla im 1, wherein operation o f the group fprocessorcores and the thirgg pof p rocess o r cores is based on one of: a lower frequency clock than that of the r g-p i t_ ro of processor cores, and use of nnd tiple clock cycles of a clock associated with the fi rst uroup ofp rocessor c o res to per fo rm one operat ion.

The chip multip rocessor of cla im 1, whe rein the gr aphene- contai n ing c omp utat ion e l ements includ e one or more of gates and sequential elements, 15.2 5. Canceled

3 0. Canceled

I. (C urrent ly A m ende d) A ch ip mu ltiprocessor, com prising; g p fi rst group of processor cores disposed on a die, whe r ein the g-first group o f processor c o res includes g raphene-containing computation elements;[[a ndfl a second gr oup o f processor cores disposed on the die, wherein the ty t sec pnd grou p of processor c o res includes a lower percentage of the graphene-co ntai ning com putation elements than the----g-p ir st group of processor cores; and a third group of pr tcessor cnres disposd o the die. herein the third group Qf proessor cores inclu des a lower prcentage of the gaphen-continng computati on elements _ han the second group of processor core s, !dl wherein. the first g roup of processor c o res a re hig h-speed processor c o res relative to the second eroup ofperoce sso r cores and the third gouof poessor coes. the first gro u p of processor c o res are configured to operate when a t least some p qotessor c of the second group of processor cores and the third g r oup of processor cores are c onfi gured to be gated j [and 1] r cy ra e g u p p c y n g -- p a ch processor core of the third g roup of processor coressarrang<ed_ to fcilithe thennal isolation o f e ach processor core of th fratjgrup of processor cores such that at least a processor core of the third g roup of processor cores is disposed in between every two ad ja cent cores of the f irs t gro up of processor cores, and to f acili t ate th erm al iso l ation of each processor core of th e second gr o up of processor cores such that at least another processor core of the th ird group of processor cores is disposed in between every two adjacent cores of the second group of processor cores, the facilitation of the thermal isolation of each processor core of the first group of processor cores and the second gro up of processor cores reduces an effect of le akage gyfrgid at is a ssoiated with the a nlieGCea~ta 1i}g ? tast leme'L"# d at leaston ro sor cor e ofthe sec ond ro frocesororesnd ales te procssetore fthethiraron f rocessor cores are dis o osed be t wee n eve t processorq h i g,m s t Up y t wo::.: adjacent cores of the first group of processor cores.

-5. Canceled

Canceled

6, (C urrently Amen ded) The chip mu lti p roc e ssor of claim [[2]1L wh e rein-p the f irst group of g processor cores are confi g ured to operate sequentially. Currently amended

(C urre ntly A mende d) Th e chip multipro ce ssor of claim [[6]] 1, wherein operation of an active processor core of-- the first group of p processor cores is t ransferre d to another processor core of the g-first gr o up o f processor cores p---based on an operati ng te m perature of the a c tive processor core. Currently amended

--- 9. Canceled

(C urrently Amended) T he chip mu ltip r ocess o r of c laim 1, wherein at least o ne processor core of t he onermer-gh-speed-first gro up of processor cores is disposed on an edge of the die. Currently amended

13, (Currently Amonded) TIh e chi p multip rocess or of cla im 1, wherein operation o f the group fprocessorcores and the thirgg pof p rocess o r cores is based on one of: a lower frequency clock than that of the r g-p i t_ ro of processor cores, and use of nnd tiple clock cycles of a clock associated with the fi rst uroup ofp rocessor c o res to per fo rm one operat ion.

The chip multip rocessor of cla im 1, whe rein the gr aphene- contai n ing c omp utat ion e l ements includ e one or more of gates and sequential elements, 15.2 5. Canceled

3 0. Canceled

I. (C urrent ly A m ende d) A ch ip mu ltiprocessor, com prising; g p fi rst group of processor cores disposed on a die, whe r ein the g-first group o f processor c o res includes g raphene-containing computation elements;[[a ndfl a second gr oup o f processor cores disposed on the die, wherein the ty t sec pnd grou p of processor c o res includes a lower percentage of the graphene-co ntai ning com putation elements than the----g-p ir st group of processor cores; and a third group of pr tcessor cnres disposd o the die. herein the third group Qf proessor cores inclu des a lower prcentage of the gaphen-continng computati on elements _ han the second group of processor core s, !dl wherein. the first g roup of processor c o res a re hig h-speed processor c o res relative to the second eroup ofperoce sso r cores and the third gouof poessor coes. the first gro u p of processor c o res are configured to operate when a t least some p qotessor c of the second group of processor cores and the third g r oup of processor cores are c onfi gured to be gated j [and 1] r cy ra e g u p p c y n g -- p a ch processor core of the third g roup of processor coressarrang<ed_ to fcilithe thennal isolation o f e ach processor core of th fratjgrup of processor cores such that at least a processor core of the third g roup of processor cores is disposed in between every two ad ja cent cores of the f irs t gro up of processor cores, and to f acili t ate th erm al iso l ation of each processor core of th e second gr o up of processor cores such that at least another processor core of the th ird group of processor cores is disposed in between every two adjacent cores of the second group of processor cores, the facilitation of the thermal isolation of each processor core of the first group of processor cores and the second gro up of processor cores reduces an effect of le akage gyfrgid at is a ssoiated with the a nlieGCea~ta 1i}g ? tast leme'L"# d at leaston ro sor cor e ofthe sec ond ro frocesororesnd ales te procssetore fthethiraron f rocessor cores are dis o osed be t wee n eve t processorq h i g,m s t Up y t wo::.: adjacent cores of the first group of processor cores.

-5. Canceled

Canceled

6, (C urrently Amen ded) The chip mu lti p roc e ssor of claim [[2]1L wh e rein-p the f irst group of g processor cores are confi g ured to operate sequentially. Currently amended

(C urre ntly A mende d) Th e chip multipro ce ssor of claim [[6]] 1, wherein operation of an active processor core of-- the first group of p processor cores is t ransferre d to another processor core of the g-first gr o up o f processor cores p---based on an operati ng te m perature of the a c tive processor core. Currently amended

--- 9. Canceled

(C urrently Amended) T he chip mu ltip r ocess o r of c laim 1, wherein at least o ne processor core of t he onermer-gh-speed-first gro up of processor cores is disposed on an edge of the die. Currently amended

13, (Currently Amonded) TIh e chi p multip rocess or of cla im 1, wherein operation o f the group fprocessorcores and the thirgg pof p rocess o r cores is based on one of: a lower frequency clock than that of the r g-p i t_ ro of processor cores, and use of nnd tiple clock cycles of a clock associated with the fi rst uroup ofp rocessor c o res to per fo rm one operat ion.

The chip multip rocessor of cla im 1, whe rein the gr aphene- contai n ing c omp utat ion e l ements includ e one or more of gates and sequential elements, 15.2 5. Canceled

3 0. Canceled

I. (C urrent ly A m ende d) A ch ip mu ltiprocessor, com prising; g p fi rst group of processor cores disposed on a die, whe r ein the g-first group o f processor c o res includes g raphene-containing computation elements;[[a ndfl a second gr oup o f processor cores disposed on the die, wherein the ty t sec pnd grou p of processor c o res includes a lower percentage of the graphene-co ntai ning com putation elements than the----g-p ir st group of processor cores; and a third group of pr tcessor cnres disposd o the die. herein the third group Qf proessor cores inclu des a lower prcentage of the gaphen-continng computati on elements _ han the second group of processor core s, !dl wherein. the first g roup of processor c o res a re hig h-speed processor c o res relative to the second eroup ofperoce sso r cores and the third gouof poessor coes. the first gro u p of processor c o res are configured to operate when a t least some p qotessor c of the second group of processor cores and the third g r oup of processor cores are c onfi gured to be gated j [and 1] r cy ra e g u p p c y n g -- p a ch processor core of the third g roup of processor coressarrang<ed_ to fcilithe thennal isolation o f e ach processor core of th fratjgrup of processor cores such that at least a processor core of the third g roup of processor cores is disposed in between every two ad ja cent cores of the f irs t gro up of processor cores, and to f acili t ate th erm al iso l ation of each processor core of th e second gr o up of processor cores such that at least another processor core of the th ird group of processor cores is disposed in between every two adjacent cores of the second group of processor cores, the facilitation of the thermal isolation of each processor core of the first group of processor cores and the second gro up of processor cores reduces an effect of le akage gyfrgid at is a ssoiated with the a nlieGCea~ta 1i}g ? tast leme'L"# d at leaston ro sor cor e ofthe sec ond ro frocesororesnd ales te procssetore fthethiraron f rocessor cores are dis o osed be t wee n eve t processorq h i g,m s t Up y t wo::.: adjacent cores of the first group of processor cores.

-5. Canceled

Canceled

6, (C urrently Amen ded) The chip mu lti p roc e ssor of claim [[2]1L wh e rein-p the f irst group of g processor cores are confi g ured to operate sequentially. Currently amended

(C urre ntly A mende d) Th e chip multipro ce ssor of claim [[6]] 1, wherein operation of an active processor core of-- the first group of p processor cores is t ransferre d to another processor core of the g-first gr o up o f processor cores p---based on an operati ng te m perature of the a c tive processor core. Currently amended

--- 9. Canceled

(C urrently Amended) T he chip mu ltip r ocess o r of c laim 1, wherein at least o ne processor core of t he onermer-gh-speed-first gro up of processor cores is disposed on an edge of the die. Currently amended

13, (Currently Amonded) TIh e chi p multip rocess or of cla im 1, wherein operation o f the group fprocessorcores and the thirgg pof p rocess o r cores is based on one of: a lower frequency clock than that of the r g-p i t_ ro of processor cores, and use of nnd tiple clock cycles of a clock associated with the fi rst uroup ofp rocessor c o res to per fo rm one operat ion.

The chip multip rocessor of cla im 1, whe rein the gr aphene- contai n ing c omp utat ion e l ements includ e one or more of gates and sequential elements, 15.2 5. Canceled

3 0. Canceled