Patent
Atlas literature
Patent
US 8,671,370Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 provides an exemplary representation of various materials and components discussed in the context of the invention
Figure 2 depicts exemplary circuit topologies and structures pertaining to the invention. [0030] Figure 3a depicts an exemplary representation of a family of exemplary approaches facilitating a chain of modules to share a common carbon nanotube, graphene ribbon, or other stripe or elongated …
Figure 8 depicts an exemplary arrangement comprising three exemplary C NFET differential amplifier modules pairwise-adjacently arranged on the same carbon nanotube. The arrangement can also be used with a flat strip of semiconducting material such as a graphene ribbon or printed strip of …
Figure 10 depicts an exemplary configuration wherein an exemplary differential amplifier ladder module that is configured to be driven by two current sources is additionally arranged so as to interconnect with a pair of internally-unspecified current source submodules, one on either side of the …
Figure 11 a depicts an exemplary simple current source employing a current mirror driven by a simple resistive current source.
Figure 17 shows an example of this wherein a simple example structure (here an adjacent contiguous N-type region, conductor region, and P- type region) is shown mapped to at least eight types of fabrication techniques, associated materials, and associated processes.
Figure 18 depicts an exemplary approach to printed electronics as provided for by the invention.
Figure 19 depicts a common framework for corresponding chain/leapfrog classes of carbon nanotube electronics, graphene ribbon electronics, semiconducting polymer chains or other at nanoscale or larger scale, and printed electronics as provided for by the invention.
Figure 20 depicts an exemplary overall approach to the emulation environment as provided for by the invention.
Figures 21-30 depict exemplary approaches to overall design software tools and simulation software tools as provided for by the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method, comprising: a computer system receiving design information specifying components of a circuit; the computer system accessing a library that includes design information for nanoelectronic components corresponding to one or more of the specified components, wherein the nanoelectronic components have a topology in which a nanostructure is placed over a plurality of underlying structures connected in a chain, wherein a first underlying structure of the plurality of underlying structures leapfrogs at least a second underlying structure of the plurality of underlying structures; and the computer system using the library to generate fabrication data usable to render the circuit using the corresponding nanoelectronic components.
The method of claim 21, wherein the nanostructure is a nanotube structure.
The method of claim 21, wherein the nanostructure is a nanoribbon structure.
The method of claim 21, further comprising: the computer system receiving an input from a user selecting one of a plurality of fabrication processes; based on the selected fabrication process, the computer system transforming a common high-level descriptor file into a fabrication data file including the fabrication data.
The method of claim 21, wherein the fabrication data includes one or more images to be printed, one or more inks to print the one or more images, and an ordering in which the one or more images are to be printed.
The method of claim 21, further comprising: the computer system simulating operation of the circuit using the corresponding nanoelectronic components.
The method of claim 21, wherein one of the nanoelectronic components is a differential amplifier.
A method, comprising: a computer system receiving design information specifying components of a circuit; the computer system accessing design information for nanoelectronic components corresponding to one or more of the specified components, wherein the nanoelectronic components have a topology in which a nanostructure is placed over a plurality of underlying structures connected in a chain, wherein a first underlying structure of the plurality of underlying structures leapfrogs at least a second underlying structure of the plurality of underlying structures; and the computer system using design information for one or more of the nanoelectronic components to simulate operation of the circuit.
The method of claim 31, further comprising: the computer system producing one or more visualizations of results generated from simulating operation of the circuit.
The method of claim 31, further comprising: selecting inks to create a prototype version of the circuit, wherein the prototype version has a larger scale than a corresponding version of the circuit that includes one or more of the nanoelectronic components, and wherein the selected inks have properties similar to properties of materials in the one or more nanoelectronic components.
The method of claim 31, wherein the using includes: producing a common high-level descriptor file for the circuit; and performing a simulation of the circuit from information specified in the common high- level descriptor file.
The method of claim 31, wherein one of the nanoelectronic components is an amplifier that includes a plurality of field effect transistors (FETs), and wherein the amplifier includes a first interconnecting structure coupling a gate of a first FET to a gate of a second FET and a source of the second FET, wherein the first interconnecting structure leapfrogs a drain of the first FET.
A non-transitory computer readable medium having program instructions stored thereon that, when executed by a computing device, cause the computing device to perform operations comprising: accessing design information for nanoelectronic components having a chain/leapfrog topology in which a nanostructure is draped over a plurality of underlying structures connected in a chain, wherein a first underlying structure of the plurality of underlying structures leapfrogs at least a second underlying structure of the plurality of underlying structures; and generating fabrication data from the design information, wherein the fabrication data is usable to render a circuit including one or more of the nanoelectronic components.
The computer readable medium of claim 38, wherein the operations further comprise: generating simulation data from the design information, wherein the simulation data is usable to simulate operation of the circuit.
The computer readable medium of claim 38, wherein the operations further comprise: receiving, via a user interface, a selection of one of a plurality of fabrication processes, wherein the fabrication data and the simulation data are generated for the selected fabrication process.
The computer readable medium of claim 38, wherein the operations further comprise: selecting inks to create a prototype version of the circuit, wherein the prototype version emulates operation of a fabricated version of the circuit, and wherein the prototype version has a larger scale than the fabricated version.
The computer readable medium of claim 38, wherein one of the nanoelectronic components includes a plurality of field effect transistors (FETs) coupled terminal to terminal, and wherein the component includes an interconnecting structure coupling a terminal of a first FET to a terminal of a second FET, wherein the interconnecting structure leapfrogs one or more structures of a third FET.
Layer stacks claimed or described, ordered top of device to substrate.
nanoelectronic component with chain/leapfrog topology
differential amplifier with FETs in chain/leapfrog topology
Materials described outside the worked examples.
carbon nanotube
graphene nanoribbon
Patent
Atlas literature
Patent
US 8,671,370Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 provides an exemplary representation of various materials and components discussed in the context of the invention
Figure 2 depicts exemplary circuit topologies and structures pertaining to the invention. [0030] Figure 3a depicts an exemplary representation of a family of exemplary approaches facilitating a chain of modules to share a common carbon nanotube, graphene ribbon, or other stripe or elongated …
Figure 8 depicts an exemplary arrangement comprising three exemplary C NFET differential amplifier modules pairwise-adjacently arranged on the same carbon nanotube. The arrangement can also be used with a flat strip of semiconducting material such as a graphene ribbon or printed strip of …
Figure 10 depicts an exemplary configuration wherein an exemplary differential amplifier ladder module that is configured to be driven by two current sources is additionally arranged so as to interconnect with a pair of internally-unspecified current source submodules, one on either side of the …
Figure 11 a depicts an exemplary simple current source employing a current mirror driven by a simple resistive current source.
Figure 17 shows an example of this wherein a simple example structure (here an adjacent contiguous N-type region, conductor region, and P- type region) is shown mapped to at least eight types of fabrication techniques, associated materials, and associated processes.
Figure 18 depicts an exemplary approach to printed electronics as provided for by the invention.
Figure 19 depicts a common framework for corresponding chain/leapfrog classes of carbon nanotube electronics, graphene ribbon electronics, semiconducting polymer chains or other at nanoscale or larger scale, and printed electronics as provided for by the invention.
Figure 20 depicts an exemplary overall approach to the emulation environment as provided for by the invention.
Figures 21-30 depict exemplary approaches to overall design software tools and simulation software tools as provided for by the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method, comprising: a computer system receiving design information specifying components of a circuit; the computer system accessing a library that includes design information for nanoelectronic components corresponding to one or more of the specified components, wherein the nanoelectronic components have a topology in which a nanostructure is placed over a plurality of underlying structures connected in a chain, wherein a first underlying structure of the plurality of underlying structures leapfrogs at least a second underlying structure of the plurality of underlying structures; and the computer system using the library to generate fabrication data usable to render the circuit using the corresponding nanoelectronic components.
The method of claim 21, wherein the nanostructure is a nanotube structure.
The method of claim 21, wherein the nanostructure is a nanoribbon structure.
The method of claim 21, further comprising: the computer system receiving an input from a user selecting one of a plurality of fabrication processes; based on the selected fabrication process, the computer system transforming a common high-level descriptor file into a fabrication data file including the fabrication data.
The method of claim 21, wherein the fabrication data includes one or more images to be printed, one or more inks to print the one or more images, and an ordering in which the one or more images are to be printed.
The method of claim 21, further comprising: the computer system simulating operation of the circuit using the corresponding nanoelectronic components.
The method of claim 21, wherein one of the nanoelectronic components is a differential amplifier.
A method, comprising: a computer system receiving design information specifying components of a circuit; the computer system accessing design information for nanoelectronic components corresponding to one or more of the specified components, wherein the nanoelectronic components have a topology in which a nanostructure is placed over a plurality of underlying structures connected in a chain, wherein a first underlying structure of the plurality of underlying structures leapfrogs at least a second underlying structure of the plurality of underlying structures; and the computer system using design information for one or more of the nanoelectronic components to simulate operation of the circuit.
The method of claim 31, further comprising: the computer system producing one or more visualizations of results generated from simulating operation of the circuit.
The method of claim 31, further comprising: selecting inks to create a prototype version of the circuit, wherein the prototype version has a larger scale than a corresponding version of the circuit that includes one or more of the nanoelectronic components, and wherein the selected inks have properties similar to properties of materials in the one or more nanoelectronic components.
The method of claim 31, wherein the using includes: producing a common high-level descriptor file for the circuit; and performing a simulation of the circuit from information specified in the common high- level descriptor file.
The method of claim 31, wherein one of the nanoelectronic components is an amplifier that includes a plurality of field effect transistors (FETs), and wherein the amplifier includes a first interconnecting structure coupling a gate of a first FET to a gate of a second FET and a source of the second FET, wherein the first interconnecting structure leapfrogs a drain of the first FET.
A non-transitory computer readable medium having program instructions stored thereon that, when executed by a computing device, cause the computing device to perform operations comprising: accessing design information for nanoelectronic components having a chain/leapfrog topology in which a nanostructure is draped over a plurality of underlying structures connected in a chain, wherein a first underlying structure of the plurality of underlying structures leapfrogs at least a second underlying structure of the plurality of underlying structures; and generating fabrication data from the design information, wherein the fabrication data is usable to render a circuit including one or more of the nanoelectronic components.
The computer readable medium of claim 38, wherein the operations further comprise: generating simulation data from the design information, wherein the simulation data is usable to simulate operation of the circuit.
The computer readable medium of claim 38, wherein the operations further comprise: receiving, via a user interface, a selection of one of a plurality of fabrication processes, wherein the fabrication data and the simulation data are generated for the selected fabrication process.
The computer readable medium of claim 38, wherein the operations further comprise: selecting inks to create a prototype version of the circuit, wherein the prototype version emulates operation of a fabricated version of the circuit, and wherein the prototype version has a larger scale than the fabricated version.
The computer readable medium of claim 38, wherein one of the nanoelectronic components includes a plurality of field effect transistors (FETs) coupled terminal to terminal, and wherein the component includes an interconnecting structure coupling a terminal of a first FET to a terminal of a second FET, wherein the interconnecting structure leapfrogs one or more structures of a third FET.
Layer stacks claimed or described, ordered top of device to substrate.
nanoelectronic component with chain/leapfrog topology
differential amplifier with FETs in chain/leapfrog topology
Materials described outside the worked examples.
carbon nanotube
graphene nanoribbon
Patent
Atlas literature
Patent
US 8,671,370Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 provides an exemplary representation of various materials and components discussed in the context of the invention
Figure 2 depicts exemplary circuit topologies and structures pertaining to the invention. [0030] Figure 3a depicts an exemplary representation of a family of exemplary approaches facilitating a chain of modules to share a common carbon nanotube, graphene ribbon, or other stripe or elongated …
Figure 8 depicts an exemplary arrangement comprising three exemplary C NFET differential amplifier modules pairwise-adjacently arranged on the same carbon nanotube. The arrangement can also be used with a flat strip of semiconducting material such as a graphene ribbon or printed strip of …
Figure 10 depicts an exemplary configuration wherein an exemplary differential amplifier ladder module that is configured to be driven by two current sources is additionally arranged so as to interconnect with a pair of internally-unspecified current source submodules, one on either side of the …
Figure 11 a depicts an exemplary simple current source employing a current mirror driven by a simple resistive current source.
Figure 17 shows an example of this wherein a simple example structure (here an adjacent contiguous N-type region, conductor region, and P- type region) is shown mapped to at least eight types of fabrication techniques, associated materials, and associated processes.
Figure 18 depicts an exemplary approach to printed electronics as provided for by the invention.
Figure 19 depicts a common framework for corresponding chain/leapfrog classes of carbon nanotube electronics, graphene ribbon electronics, semiconducting polymer chains or other at nanoscale or larger scale, and printed electronics as provided for by the invention.
Figure 20 depicts an exemplary overall approach to the emulation environment as provided for by the invention.
Figures 21-30 depict exemplary approaches to overall design software tools and simulation software tools as provided for by the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method, comprising: a computer system receiving design information specifying components of a circuit; the computer system accessing a library that includes design information for nanoelectronic components corresponding to one or more of the specified components, wherein the nanoelectronic components have a topology in which a nanostructure is placed over a plurality of underlying structures connected in a chain, wherein a first underlying structure of the plurality of underlying structures leapfrogs at least a second underlying structure of the plurality of underlying structures; and the computer system using the library to generate fabrication data usable to render the circuit using the corresponding nanoelectronic components.
The method of claim 21, wherein the nanostructure is a nanotube structure.
The method of claim 21, wherein the nanostructure is a nanoribbon structure.
The method of claim 21, further comprising: the computer system receiving an input from a user selecting one of a plurality of fabrication processes; based on the selected fabrication process, the computer system transforming a common high-level descriptor file into a fabrication data file including the fabrication data.
The method of claim 21, wherein the fabrication data includes one or more images to be printed, one or more inks to print the one or more images, and an ordering in which the one or more images are to be printed.
The method of claim 21, further comprising: the computer system simulating operation of the circuit using the corresponding nanoelectronic components.
The method of claim 21, wherein one of the nanoelectronic components is a differential amplifier.
A method, comprising: a computer system receiving design information specifying components of a circuit; the computer system accessing design information for nanoelectronic components corresponding to one or more of the specified components, wherein the nanoelectronic components have a topology in which a nanostructure is placed over a plurality of underlying structures connected in a chain, wherein a first underlying structure of the plurality of underlying structures leapfrogs at least a second underlying structure of the plurality of underlying structures; and the computer system using design information for one or more of the nanoelectronic components to simulate operation of the circuit.
The method of claim 31, further comprising: the computer system producing one or more visualizations of results generated from simulating operation of the circuit.
The method of claim 31, further comprising: selecting inks to create a prototype version of the circuit, wherein the prototype version has a larger scale than a corresponding version of the circuit that includes one or more of the nanoelectronic components, and wherein the selected inks have properties similar to properties of materials in the one or more nanoelectronic components.
The method of claim 31, wherein the using includes: producing a common high-level descriptor file for the circuit; and performing a simulation of the circuit from information specified in the common high- level descriptor file.
The method of claim 31, wherein one of the nanoelectronic components is an amplifier that includes a plurality of field effect transistors (FETs), and wherein the amplifier includes a first interconnecting structure coupling a gate of a first FET to a gate of a second FET and a source of the second FET, wherein the first interconnecting structure leapfrogs a drain of the first FET.
A non-transitory computer readable medium having program instructions stored thereon that, when executed by a computing device, cause the computing device to perform operations comprising: accessing design information for nanoelectronic components having a chain/leapfrog topology in which a nanostructure is draped over a plurality of underlying structures connected in a chain, wherein a first underlying structure of the plurality of underlying structures leapfrogs at least a second underlying structure of the plurality of underlying structures; and generating fabrication data from the design information, wherein the fabrication data is usable to render a circuit including one or more of the nanoelectronic components.
The computer readable medium of claim 38, wherein the operations further comprise: generating simulation data from the design information, wherein the simulation data is usable to simulate operation of the circuit.
The computer readable medium of claim 38, wherein the operations further comprise: receiving, via a user interface, a selection of one of a plurality of fabrication processes, wherein the fabrication data and the simulation data are generated for the selected fabrication process.
The computer readable medium of claim 38, wherein the operations further comprise: selecting inks to create a prototype version of the circuit, wherein the prototype version emulates operation of a fabricated version of the circuit, and wherein the prototype version has a larger scale than the fabricated version.
The computer readable medium of claim 38, wherein one of the nanoelectronic components includes a plurality of field effect transistors (FETs) coupled terminal to terminal, and wherein the component includes an interconnecting structure coupling a terminal of a first FET to a terminal of a second FET, wherein the interconnecting structure leapfrogs one or more structures of a third FET.
Layer stacks claimed or described, ordered top of device to substrate.
nanoelectronic component with chain/leapfrog topology
differential amplifier with FETs in chain/leapfrog topology
Materials described outside the worked examples.
carbon nanotube
graphene nanoribbon
Patent
Atlas literature
Patent
US 8,671,370Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 provides an exemplary representation of various materials and components discussed in the context of the invention
Figure 2 depicts exemplary circuit topologies and structures pertaining to the invention. [0030] Figure 3a depicts an exemplary representation of a family of exemplary approaches facilitating a chain of modules to share a common carbon nanotube, graphene ribbon, or other stripe or elongated …
Figure 8 depicts an exemplary arrangement comprising three exemplary C NFET differential amplifier modules pairwise-adjacently arranged on the same carbon nanotube. The arrangement can also be used with a flat strip of semiconducting material such as a graphene ribbon or printed strip of …
Figure 10 depicts an exemplary configuration wherein an exemplary differential amplifier ladder module that is configured to be driven by two current sources is additionally arranged so as to interconnect with a pair of internally-unspecified current source submodules, one on either side of the …
Figure 11 a depicts an exemplary simple current source employing a current mirror driven by a simple resistive current source.
Figure 17 shows an example of this wherein a simple example structure (here an adjacent contiguous N-type region, conductor region, and P- type region) is shown mapped to at least eight types of fabrication techniques, associated materials, and associated processes.
Figure 18 depicts an exemplary approach to printed electronics as provided for by the invention.
Figure 19 depicts a common framework for corresponding chain/leapfrog classes of carbon nanotube electronics, graphene ribbon electronics, semiconducting polymer chains or other at nanoscale or larger scale, and printed electronics as provided for by the invention.
Figure 20 depicts an exemplary overall approach to the emulation environment as provided for by the invention.
Figures 21-30 depict exemplary approaches to overall design software tools and simulation software tools as provided for by the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A method, comprising: a computer system receiving design information specifying components of a circuit; the computer system accessing a library that includes design information for nanoelectronic components corresponding to one or more of the specified components, wherein the nanoelectronic components have a topology in which a nanostructure is placed over a plurality of underlying structures connected in a chain, wherein a first underlying structure of the plurality of underlying structures leapfrogs at least a second underlying structure of the plurality of underlying structures; and the computer system using the library to generate fabrication data usable to render the circuit using the corresponding nanoelectronic components.
The method of claim 21, wherein the nanostructure is a nanotube structure.
The method of claim 21, wherein the nanostructure is a nanoribbon structure.
The method of claim 21, further comprising: the computer system receiving an input from a user selecting one of a plurality of fabrication processes; based on the selected fabrication process, the computer system transforming a common high-level descriptor file into a fabrication data file including the fabrication data.
The method of claim 21, wherein the fabrication data includes one or more images to be printed, one or more inks to print the one or more images, and an ordering in which the one or more images are to be printed.
The method of claim 21, further comprising: the computer system simulating operation of the circuit using the corresponding nanoelectronic components.
The method of claim 21, wherein one of the nanoelectronic components is a differential amplifier.
A method, comprising: a computer system receiving design information specifying components of a circuit; the computer system accessing design information for nanoelectronic components corresponding to one or more of the specified components, wherein the nanoelectronic components have a topology in which a nanostructure is placed over a plurality of underlying structures connected in a chain, wherein a first underlying structure of the plurality of underlying structures leapfrogs at least a second underlying structure of the plurality of underlying structures; and the computer system using design information for one or more of the nanoelectronic components to simulate operation of the circuit.
The method of claim 31, further comprising: the computer system producing one or more visualizations of results generated from simulating operation of the circuit.
The method of claim 31, further comprising: selecting inks to create a prototype version of the circuit, wherein the prototype version has a larger scale than a corresponding version of the circuit that includes one or more of the nanoelectronic components, and wherein the selected inks have properties similar to properties of materials in the one or more nanoelectronic components.
The method of claim 31, wherein the using includes: producing a common high-level descriptor file for the circuit; and performing a simulation of the circuit from information specified in the common high- level descriptor file.
The method of claim 31, wherein one of the nanoelectronic components is an amplifier that includes a plurality of field effect transistors (FETs), and wherein the amplifier includes a first interconnecting structure coupling a gate of a first FET to a gate of a second FET and a source of the second FET, wherein the first interconnecting structure leapfrogs a drain of the first FET.
A non-transitory computer readable medium having program instructions stored thereon that, when executed by a computing device, cause the computing device to perform operations comprising: accessing design information for nanoelectronic components having a chain/leapfrog topology in which a nanostructure is draped over a plurality of underlying structures connected in a chain, wherein a first underlying structure of the plurality of underlying structures leapfrogs at least a second underlying structure of the plurality of underlying structures; and generating fabrication data from the design information, wherein the fabrication data is usable to render a circuit including one or more of the nanoelectronic components.
The computer readable medium of claim 38, wherein the operations further comprise: generating simulation data from the design information, wherein the simulation data is usable to simulate operation of the circuit.
The computer readable medium of claim 38, wherein the operations further comprise: receiving, via a user interface, a selection of one of a plurality of fabrication processes, wherein the fabrication data and the simulation data are generated for the selected fabrication process.
The computer readable medium of claim 38, wherein the operations further comprise: selecting inks to create a prototype version of the circuit, wherein the prototype version emulates operation of a fabricated version of the circuit, and wherein the prototype version has a larger scale than the fabricated version.
The computer readable medium of claim 38, wherein one of the nanoelectronic components includes a plurality of field effect transistors (FETs) coupled terminal to terminal, and wherein the component includes an interconnecting structure coupling a terminal of a first FET to a terminal of a second FET, wherein the interconnecting structure leapfrogs one or more structures of a third FET.
Layer stacks claimed or described, ordered top of device to substrate.
nanoelectronic component with chain/leapfrog topology
differential amplifier with FETs in chain/leapfrog topology
Materials described outside the worked examples.
carbon nanotube
graphene nanoribbon
semiconducting polymer
semiconducting ink
semiconducting polymer
semiconducting ink
semiconducting polymer
semiconducting ink
semiconducting polymer
semiconducting ink
