Abstract

The continued evolution of CMOS technology demands materials and architectures that emphasize low-power consumption, particularly for computations involving large-scale data processing and multivariable optimization. Ferroelectric materials offer promising solutions through enabling dual-purpose memory units capable of performing both storage and logic operations. In this study, we demonstrate ferroelectric field-effect transistors (FeFETs) with MoS₂ monolayer channels fabricated on ultrathin 5 nm and 10 nm ferroelectric Aluminum Scandium Nitride (Al₁-xScxN) films. By decreasing the thickness of the ferroelectric film, we achieve significantly reduced gate voltages (<3V) required to switch the conductance of the devices, enabling operation at low voltages compatible with advanced CMOS. We observe a characteristic crossover in hysteresis behavior that varies with film thickness, channel fabrication method, and environmental conditions. Through systematic investigation of multiple parameters including channel fabrication methods, dimensional scaling, and environmental effects, we provide pathways to improve device performance. While our devices demonstrate clear ferroelectric switching behavior, further optimization is required to enhance the ON/OFF ratio at zero gate voltage while continuing to reduce the coercive field of these ultrathin films.

Abstract

The continued evolution of CMOS technology demands materials and architectures that emphasize low-power consumption, particularly for computations involving large-scale data processing and multivariable optimization. Ferroelectric materials offer promising solutions through enabling dual-purpose memory units capable of performing both storage and logic operations. In this study, we demonstrate ferroelectric field-effect transistors (FeFETs) with MoS₂ monolayer channels fabricated on ultrathin 5 nm and 10 nm ferroelectric Aluminum Scandium Nitride (Al₁-xScxN) films. By decreasing the thickness of the ferroelectric film, we achieve significantly reduced gate voltages (<3V) required to switch the conductance of the devices, enabling operation at low voltages compatible with advanced CMOS. We observe a characteristic crossover in hysteresis behavior that varies with film thickness, channel fabrication method, and environmental conditions. Through systematic investigation of multiple parameters including channel fabrication methods, dimensional scaling, and environmental effects, we provide pathways to improve device performance. While our devices demonstrate clear ferroelectric switching behavior, further optimization is required to enhance the ON/OFF ratio at zero gate voltage while continuing to reduce the coercive field of these ultrathin films.

Abstract

The continued evolution of CMOS technology demands materials and architectures that emphasize low-power consumption, particularly for computations involving large-scale data processing and multivariable optimization. Ferroelectric materials offer promising solutions through enabling dual-purpose memory units capable of performing both storage and logic operations. In this study, we demonstrate ferroelectric field-effect transistors (FeFETs) with MoS₂ monolayer channels fabricated on ultrathin 5 nm and 10 nm ferroelectric Aluminum Scandium Nitride (Al₁-xScxN) films. By decreasing the thickness of the ferroelectric film, we achieve significantly reduced gate voltages (<3V) required to switch the conductance of the devices, enabling operation at low voltages compatible with advanced CMOS. We observe a characteristic crossover in hysteresis behavior that varies with film thickness, channel fabrication method, and environmental conditions. Through systematic investigation of multiple parameters including channel fabrication methods, dimensional scaling, and environmental effects, we provide pathways to improve device performance. While our devices demonstrate clear ferroelectric switching behavior, further optimization is required to enhance the ON/OFF ratio at zero gate voltage while continuing to reduce the coercive field of these ultrathin films.

Abstract

The continued evolution of CMOS technology demands materials and architectures that emphasize low-power consumption, particularly for computations involving large-scale data processing and multivariable optimization. Ferroelectric materials offer promising solutions through enabling dual-purpose memory units capable of performing both storage and logic operations. In this study, we demonstrate ferroelectric field-effect transistors (FeFETs) with MoS₂ monolayer channels fabricated on ultrathin 5 nm and 10 nm ferroelectric Aluminum Scandium Nitride (Al₁-xScxN) films. By decreasing the thickness of the ferroelectric film, we achieve significantly reduced gate voltages (<3V) required to switch the conductance of the devices, enabling operation at low voltages compatible with advanced CMOS. We observe a characteristic crossover in hysteresis behavior that varies with film thickness, channel fabrication method, and environmental conditions. Through systematic investigation of multiple parameters including channel fabrication methods, dimensional scaling, and environmental effects, we provide pathways to improve device performance. While our devices demonstrate clear ferroelectric switching behavior, further optimization is required to enhance the ON/OFF ratio at zero gate voltage while continuing to reduce the coercive field of these ultrathin films.