Patent
US 10,586,866STRESSORS FOR COMPRESSIVELY STRAINED GAN P-CHANNEL
Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,586,866Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The two arrows pointing inwardly toward each other represent the 1.0% compressive strain that the channel portion is subjected to. Note that not all of …
FIG. 2 provides a simpli fi ed diagram to illustrate the difference in lattice constant between two different crystalline materials. [0004]
FIG. 3 illustrates schematically how the strain is distributed between two mismatched crystalline materials. [0005]
FIG. 4 provides a theoretical diagram illustrating the strain in different portions of an embodiment of a GaN p-channel device, according to an embodiment of …
FIG. 5 is a bar graph illustrating the band gap of various crystalline materials. [0007]
FIGS. 6A-6C provide cross-sectional views of three different embodi m ents of a p- channel device, according to the present disclosure. [0008]
FIG. 7 provides a cross-section view of an embodiment of a p-channel device that includes a doped connector layer. [0009]
FIG. 8 is a flow chart illustrating one embodiment of a method for making a compressively strained GaN p-channel device, according to the present disclosure. …
FIG. 9 illustrates a computing system implemented with one or more transistor structures in accordance with an example embodiment of the present disclosure. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit device, comprising: a substrate comprising a III -Nitride structure having a first lattice constant; and a source region, a drain region, and a region between the source and drain regions configured to act as a p-channel, the source and drain regions on the substrate and comprising corresponding structures having a second lattice constant wherein the second lattice constant is greater than the first lattice constant, the corresponding structures comprising oxygen, indium, tin, and titanium. Currently amended
The device of claim 1 wherein the I II -Nitride structure comprises nitrogen and at least one of gallium, aluminum, and indium. Previously presented
The device of claim 1 wherein the source and drain structures exhibit a band gap between 3.0 and 4.0 eV. Previously presented
The device of claim 1 wherein the source and drain structures exhibit a band gap between 3.3 and 3.7 eV. Previously presented
The device of claim 1 wherein the region between the source and drain regions is compressively strained. Previously presented
The device of claim 1 comprising a doped connector layer between the region between the source and drain regions, and one or both of the source and drain regions. Previously presented
The device of claim 1 wherein the III -Nitride structure is gallium nitride (GaN). Previously presented
The device of claim 1 wherein the region between the source and drain regions comprises gallium nitride (GaN). Previously presented
The device of claim 1 wherein the source and the drain structures comprise indium tin oxide (ITO) and titanium dioxide (T iO 2). Previously presented
The device of claim 1 wherein the source and the drain structures comprise titanium dioxide (Ti O 2) graded to indium tin oxide (ITO). Previously presented
The device of claim 1 wherein the source and the drain structures comprise titanium dioxide (Ti O 2), indium oxide (I n203), and indium tin oxide (ITO). Previously presented
Canceled
Canceled
Canceled
An integrated circuit device, comprising: a substrate comprising a I II -Nitride structure; a source region, a drain region, and a region between the source and drain regions configured to act as a p-channel each on the substrate, the source and drain regions comprising a structure having a lattice constant greater than a lattice constant of the III -Nitride structure, the source/drain structure comprising oxygen, indium, tin, and titanium; and a gate electrode above the region between the source and drain regions; wherein the region between the source and drain regions is compressively strained. Previously presented
The device of claim 14 wherein the I II -Nitride structure comprises aluminum nitride (A l N), gallium nitride (GaN), indium nitride (InN), or mixtures thereof. Previously presented
The device of claim 14 wherein the region between the source and drain regions comprises gallium nitride (GaN). Previously presented
The device of claim 14 wherein the I II -N structure and the source/drain structure each exhibit wurtzite crystalline structure. Previously presented
The device of claim 14 wherein the region between the source and drain regions has a first length, the source region has a second length and the drain region has a third length, and the ratio of the second length of the source region plus the third length of the drain region to the first length of the region between the source and drain regions is greater than or equal to 1. Previously presented
The device of claim 14 wherein the substrate comprises a region that is unstrained, and another region of the substrate is biaxially strained. Previously presented
The device of claim 14 comprising a doped connector layer between the region between the source and drain regions of the I II -Nitride structure and the source and drain regions. Previously presented
Canceled
Canceled
Canceled
A method for forming an integrated circuit device, the method comprising: forming at least two cavities in a substrate structure, the substrate structure comprised of at least one of aluminum nitride (A l N), gallium nitride (GaN), indium nitride (InN), and alloys thereof, forming a source and drain in the cavities by growing a crystalline structure in the cavities, the source and drain defining a region therebetween configured to act as a p-channel in the substrate, and the crystalline structure having a lattice constant greater than the lattice constant of the substrate structure, the crystalline structure comprising oxygen, indium, tin, and titanium; and reducing effective hole mass in the region between the source and drain regions. Previously presented
The method of claim 24 further comprising applying uniaxial strain to the region between the source and drain regions. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN p-channel transistor (claims 1-12)
GaN p-channel transistor with gate electrode (claim 14)
Materials described outside the worked examples.
III-Nitride structure
source/drain stressor material comprising oxygen, indium, tin, and titanium
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a bar graph illustrating the band gap of various crystalline materials. [0007]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Band gap range for source/drain structures (claim 3) | 3–4 eV | source/drain stressor material comprising oxygen, indium, tin, and titanium |
Band gap narrower range for source/drain structures (claim 4) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,586,866Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The two arrows pointing inwardly toward each other represent the 1.0% compressive strain that the channel portion is subjected to. Note that not all of …
FIG. 2 provides a simpli fi ed diagram to illustrate the difference in lattice constant between two different crystalline materials. [0004]
FIG. 3 illustrates schematically how the strain is distributed between two mismatched crystalline materials. [0005]
FIG. 4 provides a theoretical diagram illustrating the strain in different portions of an embodiment of a GaN p-channel device, according to an embodiment of …
FIG. 5 is a bar graph illustrating the band gap of various crystalline materials. [0007]
FIGS. 6A-6C provide cross-sectional views of three different embodi m ents of a p- channel device, according to the present disclosure. [0008]
FIG. 7 provides a cross-section view of an embodiment of a p-channel device that includes a doped connector layer. [0009]
FIG. 8 is a flow chart illustrating one embodiment of a method for making a compressively strained GaN p-channel device, according to the present disclosure. …
FIG. 9 illustrates a computing system implemented with one or more transistor structures in accordance with an example embodiment of the present disclosure. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit device, comprising: a substrate comprising a III -Nitride structure having a first lattice constant; and a source region, a drain region, and a region between the source and drain regions configured to act as a p-channel, the source and drain regions on the substrate and comprising corresponding structures having a second lattice constant wherein the second lattice constant is greater than the first lattice constant, the corresponding structures comprising oxygen, indium, tin, and titanium. Currently amended
The device of claim 1 wherein the I II -Nitride structure comprises nitrogen and at least one of gallium, aluminum, and indium. Previously presented
The device of claim 1 wherein the source and drain structures exhibit a band gap between 3.0 and 4.0 eV. Previously presented
The device of claim 1 wherein the source and drain structures exhibit a band gap between 3.3 and 3.7 eV. Previously presented
The device of claim 1 wherein the region between the source and drain regions is compressively strained. Previously presented
The device of claim 1 comprising a doped connector layer between the region between the source and drain regions, and one or both of the source and drain regions. Previously presented
The device of claim 1 wherein the III -Nitride structure is gallium nitride (GaN). Previously presented
The device of claim 1 wherein the region between the source and drain regions comprises gallium nitride (GaN). Previously presented
The device of claim 1 wherein the source and the drain structures comprise indium tin oxide (ITO) and titanium dioxide (T iO 2). Previously presented
The device of claim 1 wherein the source and the drain structures comprise titanium dioxide (Ti O 2) graded to indium tin oxide (ITO). Previously presented
The device of claim 1 wherein the source and the drain structures comprise titanium dioxide (Ti O 2), indium oxide (I n203), and indium tin oxide (ITO). Previously presented
Canceled
Canceled
Canceled
An integrated circuit device, comprising: a substrate comprising a I II -Nitride structure; a source region, a drain region, and a region between the source and drain regions configured to act as a p-channel each on the substrate, the source and drain regions comprising a structure having a lattice constant greater than a lattice constant of the III -Nitride structure, the source/drain structure comprising oxygen, indium, tin, and titanium; and a gate electrode above the region between the source and drain regions; wherein the region between the source and drain regions is compressively strained. Previously presented
The device of claim 14 wherein the I II -Nitride structure comprises aluminum nitride (A l N), gallium nitride (GaN), indium nitride (InN), or mixtures thereof. Previously presented
The device of claim 14 wherein the region between the source and drain regions comprises gallium nitride (GaN). Previously presented
The device of claim 14 wherein the I II -N structure and the source/drain structure each exhibit wurtzite crystalline structure. Previously presented
The device of claim 14 wherein the region between the source and drain regions has a first length, the source region has a second length and the drain region has a third length, and the ratio of the second length of the source region plus the third length of the drain region to the first length of the region between the source and drain regions is greater than or equal to 1. Previously presented
The device of claim 14 wherein the substrate comprises a region that is unstrained, and another region of the substrate is biaxially strained. Previously presented
The device of claim 14 comprising a doped connector layer between the region between the source and drain regions of the I II -Nitride structure and the source and drain regions. Previously presented
Canceled
Canceled
Canceled
A method for forming an integrated circuit device, the method comprising: forming at least two cavities in a substrate structure, the substrate structure comprised of at least one of aluminum nitride (A l N), gallium nitride (GaN), indium nitride (InN), and alloys thereof, forming a source and drain in the cavities by growing a crystalline structure in the cavities, the source and drain defining a region therebetween configured to act as a p-channel in the substrate, and the crystalline structure having a lattice constant greater than the lattice constant of the substrate structure, the crystalline structure comprising oxygen, indium, tin, and titanium; and reducing effective hole mass in the region between the source and drain regions. Previously presented
The method of claim 24 further comprising applying uniaxial strain to the region between the source and drain regions. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN p-channel transistor (claims 1-12)
GaN p-channel transistor with gate electrode (claim 14)
Materials described outside the worked examples.
III-Nitride structure
source/drain stressor material comprising oxygen, indium, tin, and titanium
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a bar graph illustrating the band gap of various crystalline materials. [0007]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Band gap range for source/drain structures (claim 3) | 3–4 eV | source/drain stressor material comprising oxygen, indium, tin, and titanium |
Band gap narrower range for source/drain structures (claim 4) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,586,866Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The two arrows pointing inwardly toward each other represent the 1.0% compressive strain that the channel portion is subjected to. Note that not all of …
FIG. 2 provides a simpli fi ed diagram to illustrate the difference in lattice constant between two different crystalline materials. [0004]
FIG. 3 illustrates schematically how the strain is distributed between two mismatched crystalline materials. [0005]
FIG. 4 provides a theoretical diagram illustrating the strain in different portions of an embodiment of a GaN p-channel device, according to an embodiment of …
FIG. 5 is a bar graph illustrating the band gap of various crystalline materials. [0007]
FIGS. 6A-6C provide cross-sectional views of three different embodi m ents of a p- channel device, according to the present disclosure. [0008]
FIG. 7 provides a cross-section view of an embodiment of a p-channel device that includes a doped connector layer. [0009]
FIG. 8 is a flow chart illustrating one embodiment of a method for making a compressively strained GaN p-channel device, according to the present disclosure. …
FIG. 9 illustrates a computing system implemented with one or more transistor structures in accordance with an example embodiment of the present disclosure. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit device, comprising: a substrate comprising a III -Nitride structure having a first lattice constant; and a source region, a drain region, and a region between the source and drain regions configured to act as a p-channel, the source and drain regions on the substrate and comprising corresponding structures having a second lattice constant wherein the second lattice constant is greater than the first lattice constant, the corresponding structures comprising oxygen, indium, tin, and titanium. Currently amended
The device of claim 1 wherein the I II -Nitride structure comprises nitrogen and at least one of gallium, aluminum, and indium. Previously presented
The device of claim 1 wherein the source and drain structures exhibit a band gap between 3.0 and 4.0 eV. Previously presented
The device of claim 1 wherein the source and drain structures exhibit a band gap between 3.3 and 3.7 eV. Previously presented
The device of claim 1 wherein the region between the source and drain regions is compressively strained. Previously presented
The device of claim 1 comprising a doped connector layer between the region between the source and drain regions, and one or both of the source and drain regions. Previously presented
The device of claim 1 wherein the III -Nitride structure is gallium nitride (GaN). Previously presented
The device of claim 1 wherein the region between the source and drain regions comprises gallium nitride (GaN). Previously presented
The device of claim 1 wherein the source and the drain structures comprise indium tin oxide (ITO) and titanium dioxide (T iO 2). Previously presented
The device of claim 1 wherein the source and the drain structures comprise titanium dioxide (Ti O 2) graded to indium tin oxide (ITO). Previously presented
The device of claim 1 wherein the source and the drain structures comprise titanium dioxide (Ti O 2), indium oxide (I n203), and indium tin oxide (ITO). Previously presented
Canceled
Canceled
Canceled
An integrated circuit device, comprising: a substrate comprising a I II -Nitride structure; a source region, a drain region, and a region between the source and drain regions configured to act as a p-channel each on the substrate, the source and drain regions comprising a structure having a lattice constant greater than a lattice constant of the III -Nitride structure, the source/drain structure comprising oxygen, indium, tin, and titanium; and a gate electrode above the region between the source and drain regions; wherein the region between the source and drain regions is compressively strained. Previously presented
The device of claim 14 wherein the I II -Nitride structure comprises aluminum nitride (A l N), gallium nitride (GaN), indium nitride (InN), or mixtures thereof. Previously presented
The device of claim 14 wherein the region between the source and drain regions comprises gallium nitride (GaN). Previously presented
The device of claim 14 wherein the I II -N structure and the source/drain structure each exhibit wurtzite crystalline structure. Previously presented
The device of claim 14 wherein the region between the source and drain regions has a first length, the source region has a second length and the drain region has a third length, and the ratio of the second length of the source region plus the third length of the drain region to the first length of the region between the source and drain regions is greater than or equal to 1. Previously presented
The device of claim 14 wherein the substrate comprises a region that is unstrained, and another region of the substrate is biaxially strained. Previously presented
The device of claim 14 comprising a doped connector layer between the region between the source and drain regions of the I II -Nitride structure and the source and drain regions. Previously presented
Canceled
Canceled
Canceled
A method for forming an integrated circuit device, the method comprising: forming at least two cavities in a substrate structure, the substrate structure comprised of at least one of aluminum nitride (A l N), gallium nitride (GaN), indium nitride (InN), and alloys thereof, forming a source and drain in the cavities by growing a crystalline structure in the cavities, the source and drain defining a region therebetween configured to act as a p-channel in the substrate, and the crystalline structure having a lattice constant greater than the lattice constant of the substrate structure, the crystalline structure comprising oxygen, indium, tin, and titanium; and reducing effective hole mass in the region between the source and drain regions. Previously presented
The method of claim 24 further comprising applying uniaxial strain to the region between the source and drain regions. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN p-channel transistor (claims 1-12)
GaN p-channel transistor with gate electrode (claim 14)
Materials described outside the worked examples.
III-Nitride structure
source/drain stressor material comprising oxygen, indium, tin, and titanium
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a bar graph illustrating the band gap of various crystalline materials. [0007]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Band gap range for source/drain structures (claim 3) | 3–4 eV | source/drain stressor material comprising oxygen, indium, tin, and titanium |
Band gap narrower range for source/drain structures (claim 4) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,586,866Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The two arrows pointing inwardly toward each other represent the 1.0% compressive strain that the channel portion is subjected to. Note that not all of …
FIG. 2 provides a simpli fi ed diagram to illustrate the difference in lattice constant between two different crystalline materials. [0004]
FIG. 3 illustrates schematically how the strain is distributed between two mismatched crystalline materials. [0005]
FIG. 4 provides a theoretical diagram illustrating the strain in different portions of an embodiment of a GaN p-channel device, according to an embodiment of …
FIG. 5 is a bar graph illustrating the band gap of various crystalline materials. [0007]
FIGS. 6A-6C provide cross-sectional views of three different embodi m ents of a p- channel device, according to the present disclosure. [0008]
FIG. 7 provides a cross-section view of an embodiment of a p-channel device that includes a doped connector layer. [0009]
FIG. 8 is a flow chart illustrating one embodiment of a method for making a compressively strained GaN p-channel device, according to the present disclosure. …
FIG. 9 illustrates a computing system implemented with one or more transistor structures in accordance with an example embodiment of the present disclosure. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit device, comprising: a substrate comprising a III -Nitride structure having a first lattice constant; and a source region, a drain region, and a region between the source and drain regions configured to act as a p-channel, the source and drain regions on the substrate and comprising corresponding structures having a second lattice constant wherein the second lattice constant is greater than the first lattice constant, the corresponding structures comprising oxygen, indium, tin, and titanium. Currently amended
The device of claim 1 wherein the I II -Nitride structure comprises nitrogen and at least one of gallium, aluminum, and indium. Previously presented
The device of claim 1 wherein the source and drain structures exhibit a band gap between 3.0 and 4.0 eV. Previously presented
The device of claim 1 wherein the source and drain structures exhibit a band gap between 3.3 and 3.7 eV. Previously presented
The device of claim 1 wherein the region between the source and drain regions is compressively strained. Previously presented
The device of claim 1 comprising a doped connector layer between the region between the source and drain regions, and one or both of the source and drain regions. Previously presented
The device of claim 1 wherein the III -Nitride structure is gallium nitride (GaN). Previously presented
The device of claim 1 wherein the region between the source and drain regions comprises gallium nitride (GaN). Previously presented
The device of claim 1 wherein the source and the drain structures comprise indium tin oxide (ITO) and titanium dioxide (T iO 2). Previously presented
The device of claim 1 wherein the source and the drain structures comprise titanium dioxide (Ti O 2) graded to indium tin oxide (ITO). Previously presented
The device of claim 1 wherein the source and the drain structures comprise titanium dioxide (Ti O 2), indium oxide (I n203), and indium tin oxide (ITO). Previously presented
Canceled
Canceled
Canceled
An integrated circuit device, comprising: a substrate comprising a I II -Nitride structure; a source region, a drain region, and a region between the source and drain regions configured to act as a p-channel each on the substrate, the source and drain regions comprising a structure having a lattice constant greater than a lattice constant of the III -Nitride structure, the source/drain structure comprising oxygen, indium, tin, and titanium; and a gate electrode above the region between the source and drain regions; wherein the region between the source and drain regions is compressively strained. Previously presented
The device of claim 14 wherein the I II -Nitride structure comprises aluminum nitride (A l N), gallium nitride (GaN), indium nitride (InN), or mixtures thereof. Previously presented
The device of claim 14 wherein the region between the source and drain regions comprises gallium nitride (GaN). Previously presented
The device of claim 14 wherein the I II -N structure and the source/drain structure each exhibit wurtzite crystalline structure. Previously presented
The device of claim 14 wherein the region between the source and drain regions has a first length, the source region has a second length and the drain region has a third length, and the ratio of the second length of the source region plus the third length of the drain region to the first length of the region between the source and drain regions is greater than or equal to 1. Previously presented
The device of claim 14 wherein the substrate comprises a region that is unstrained, and another region of the substrate is biaxially strained. Previously presented
The device of claim 14 comprising a doped connector layer between the region between the source and drain regions of the I II -Nitride structure and the source and drain regions. Previously presented
Canceled
Canceled
Canceled
A method for forming an integrated circuit device, the method comprising: forming at least two cavities in a substrate structure, the substrate structure comprised of at least one of aluminum nitride (A l N), gallium nitride (GaN), indium nitride (InN), and alloys thereof, forming a source and drain in the cavities by growing a crystalline structure in the cavities, the source and drain defining a region therebetween configured to act as a p-channel in the substrate, and the crystalline structure having a lattice constant greater than the lattice constant of the substrate structure, the crystalline structure comprising oxygen, indium, tin, and titanium; and reducing effective hole mass in the region between the source and drain regions. Previously presented
The method of claim 24 further comprising applying uniaxial strain to the region between the source and drain regions. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN p-channel transistor (claims 1-12)
GaN p-channel transistor with gate electrode (claim 14)
Materials described outside the worked examples.
III-Nitride structure
source/drain stressor material comprising oxygen, indium, tin, and titanium
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a bar graph illustrating the band gap of various crystalline materials. [0007]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Band gap range for source/drain structures (claim 3) | 3–4 eV | source/drain stressor material comprising oxygen, indium, tin, and titanium |
Band gap narrower range for source/drain structures (claim 4) |
Related documents with shared materials, methods, properties, or citations.
III-N p-channel transistor formed by cavity growth method (claim 24)
indium tin oxide
ITO
doped connector layer
aluminum nitride
AlN
indium nitride
InN
titanium dioxide
TiO₂
indium oxide
In₂O₃
hafnium dioxide
HfO₂
zirconium dioxide
ZrO₂
tin oxide
SnO₂
p-doped GaN connector
GaN:Mg
FIG. 5 is a bar graph illustrating the band gap of various crystalline materials. [0007]
FIG. 9 illustrates a computing system implemented with one or more transistor structures in accordance with an example embodiment of the present disclosure. …
source/drain stressor material comprising oxygen, indium, tin, and titanium |
GaN lattice constant a | 3.189 Angstrom | GaN |
GaN lattice constant c | 5.185 Angstrom | GaN |
III-N p-channel transistor formed by cavity growth method (claim 24)
indium tin oxide
ITO
doped connector layer
aluminum nitride
AlN
indium nitride
InN
titanium dioxide
TiO₂
indium oxide
In₂O₃
hafnium dioxide
HfO₂
zirconium dioxide
ZrO₂
tin oxide
SnO₂
p-doped GaN connector
GaN:Mg
FIG. 5 is a bar graph illustrating the band gap of various crystalline materials. [0007]
FIG. 9 illustrates a computing system implemented with one or more transistor structures in accordance with an example embodiment of the present disclosure. …
source/drain stressor material comprising oxygen, indium, tin, and titanium |
GaN lattice constant a | 3.189 Angstrom | GaN |
GaN lattice constant c | 5.185 Angstrom | GaN |
III-N p-channel transistor formed by cavity growth method (claim 24)
indium tin oxide
ITO
doped connector layer
aluminum nitride
AlN
indium nitride
InN
titanium dioxide
TiO₂
indium oxide
In₂O₃
hafnium dioxide
HfO₂
zirconium dioxide
ZrO₂
tin oxide
SnO₂
p-doped GaN connector
GaN:Mg
FIG. 5 is a bar graph illustrating the band gap of various crystalline materials. [0007]
FIG. 9 illustrates a computing system implemented with one or more transistor structures in accordance with an example embodiment of the present disclosure. …
source/drain stressor material comprising oxygen, indium, tin, and titanium |
GaN lattice constant a | 3.189 Angstrom | GaN |
GaN lattice constant c | 5.185 Angstrom | GaN |
III-N p-channel transistor formed by cavity growth method (claim 24)
indium tin oxide
ITO
doped connector layer
aluminum nitride
AlN
indium nitride
InN
titanium dioxide
TiO₂
indium oxide
In₂O₃
hafnium dioxide
HfO₂
zirconium dioxide
ZrO₂
tin oxide
SnO₂
p-doped GaN connector
GaN:Mg
FIG. 5 is a bar graph illustrating the band gap of various crystalline materials. [0007]
FIG. 9 illustrates a computing system implemented with one or more transistor structures in accordance with an example embodiment of the present disclosure. …
source/drain stressor material comprising oxygen, indium, tin, and titanium |
GaN lattice constant a | 3.189 Angstrom | GaN |
GaN lattice constant c | 5.185 Angstrom | GaN |