Patent
US 11,908,689 B2METHOD FOR FABRICATING GAN CHIP AND GAN CHIP
Fen Guo, Kang Su, Lang Zhou, Tuo Li et al.
INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)·Feb. 20, 2024·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,908,689 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a method for fabricating a GaN chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a hardware structure of a computer device for fabricating a GaN chip according to an embodiment of the present application; and
FIG. 3 is a schematic diagram of a computer storage medium for fabricating a GaN chip according to an embodi- ment of the present application.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a GaN chip, comprising: growing a Nb₂N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb₂N sac-rificial layer; growing a Ta₂N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta₂N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb₂N sacrificial layer and the Ta₂N sacrificial layer; and transferring remaining material after removal of the Nb₂N sacrificial layer and the Ta₂N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.
The method according to claim 1, wherein growing the Nb₂N sacrificial layer on the original substrate comprises: fabricating the Nb₂N sacrificial layer with a thickness of 0-50 nm on the original substrate.
The method according to claim 1, wherein growing the Ta₂N sacrificial layer on the GaN insertion layer comprises: fabricating the Ta₂N sacrificial layer with a thickness of 0-50 nm on the GaN insertion layer.
The method according to claim 1, wherein bonding the GaN wafer with the first surface of the temporary carrier comprises: coating the first surface of the temporary carrier with an adhesive material, placing the temporary carrier on a hot plate for baking, and then cooling the temporary carrier.
The method according to claim 1, wherein bonding the GaN wafer with the first surface of the temporary carrier comprises: controlling a bonding temperature to 200-350° C. and a bonding force to 1000-2000 N.
The method according to claim 1, wherein removing the Nb₂N sacrificial layer and the Ta₂N sacrificial layer comprises: removing the Nb₂N sacrificial layer and the Ta₂N sacri-ficial layer by etching with hydrochloric acid and hydrofluoric acid at a volume ratio of 1:1.
The method according to claim 1, wherein transferring the remaining material after removal of the Nb₂N sacrificial layer and the Ta₂N sacrificial layer to the target substrate comprises: activating the remaining material and the target substrate with nitrogen or oxygen, aligning the activated target substrate with the activated remaining material for attachment, and carrying out annealing.
A chip, fabricated by the method according to claim 1.
The method according to claim 1, wherein the material of the original substrate is one of SiC, GaN, sapphire, diamond, Ga₂O₃ and AlN.
The method according to claim 1, wherein in the step of growing the Ta₂N sacrificial layer on the GaN insertion layer, the Ta₂N sacrificial layer with hexagonal crystal structure symmetry is grown on the GaN insertion layer by thin film deposition.
The method according to claim 1, wherein in the step of bonding the GaN wafer with the first surface of the temporary carrier, the wafer bonding is carried out through a wafer bonding machine, a bonding temperature is 150-200° C., a bonding time is 5-10 min, and a pressure is 0.1 MPa.
Layer stacks claimed or described, ordered top of device to substrate.
GaN chip
Materials described outside the worked examples.
Nb₂N sacrificial layer
Nb₂N
GaN insertion layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–50 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 15
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,908,689 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a method for fabricating a GaN chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a hardware structure of a computer device for fabricating a GaN chip according to an embodiment of the present application; and
FIG. 3 is a schematic diagram of a computer storage medium for fabricating a GaN chip according to an embodi- ment of the present application.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a GaN chip, comprising: growing a Nb₂N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb₂N sac-rificial layer; growing a Ta₂N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta₂N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb₂N sacrificial layer and the Ta₂N sacrificial layer; and transferring remaining material after removal of the Nb₂N sacrificial layer and the Ta₂N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.
The method according to claim 1, wherein growing the Nb₂N sacrificial layer on the original substrate comprises: fabricating the Nb₂N sacrificial layer with a thickness of 0-50 nm on the original substrate.
The method according to claim 1, wherein growing the Ta₂N sacrificial layer on the GaN insertion layer comprises: fabricating the Ta₂N sacrificial layer with a thickness of 0-50 nm on the GaN insertion layer.
The method according to claim 1, wherein bonding the GaN wafer with the first surface of the temporary carrier comprises: coating the first surface of the temporary carrier with an adhesive material, placing the temporary carrier on a hot plate for baking, and then cooling the temporary carrier.
The method according to claim 1, wherein bonding the GaN wafer with the first surface of the temporary carrier comprises: controlling a bonding temperature to 200-350° C. and a bonding force to 1000-2000 N.
The method according to claim 1, wherein removing the Nb₂N sacrificial layer and the Ta₂N sacrificial layer comprises: removing the Nb₂N sacrificial layer and the Ta₂N sacri-ficial layer by etching with hydrochloric acid and hydrofluoric acid at a volume ratio of 1:1.
The method according to claim 1, wherein transferring the remaining material after removal of the Nb₂N sacrificial layer and the Ta₂N sacrificial layer to the target substrate comprises: activating the remaining material and the target substrate with nitrogen or oxygen, aligning the activated target substrate with the activated remaining material for attachment, and carrying out annealing.
A chip, fabricated by the method according to claim 1.
The method according to claim 1, wherein the material of the original substrate is one of SiC, GaN, sapphire, diamond, Ga₂O₃ and AlN.
The method according to claim 1, wherein in the step of growing the Ta₂N sacrificial layer on the GaN insertion layer, the Ta₂N sacrificial layer with hexagonal crystal structure symmetry is grown on the GaN insertion layer by thin film deposition.
The method according to claim 1, wherein in the step of bonding the GaN wafer with the first surface of the temporary carrier, the wafer bonding is carried out through a wafer bonding machine, a bonding temperature is 150-200° C., a bonding time is 5-10 min, and a pressure is 0.1 MPa.
Layer stacks claimed or described, ordered top of device to substrate.
GaN chip
Materials described outside the worked examples.
Nb₂N sacrificial layer
Nb₂N
GaN insertion layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–50 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 15
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,908,689 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a method for fabricating a GaN chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a hardware structure of a computer device for fabricating a GaN chip according to an embodiment of the present application; and
FIG. 3 is a schematic diagram of a computer storage medium for fabricating a GaN chip according to an embodi- ment of the present application.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a GaN chip, comprising: growing a Nb₂N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb₂N sac-rificial layer; growing a Ta₂N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta₂N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb₂N sacrificial layer and the Ta₂N sacrificial layer; and transferring remaining material after removal of the Nb₂N sacrificial layer and the Ta₂N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.
The method according to claim 1, wherein growing the Nb₂N sacrificial layer on the original substrate comprises: fabricating the Nb₂N sacrificial layer with a thickness of 0-50 nm on the original substrate.
The method according to claim 1, wherein growing the Ta₂N sacrificial layer on the GaN insertion layer comprises: fabricating the Ta₂N sacrificial layer with a thickness of 0-50 nm on the GaN insertion layer.
The method according to claim 1, wherein bonding the GaN wafer with the first surface of the temporary carrier comprises: coating the first surface of the temporary carrier with an adhesive material, placing the temporary carrier on a hot plate for baking, and then cooling the temporary carrier.
The method according to claim 1, wherein bonding the GaN wafer with the first surface of the temporary carrier comprises: controlling a bonding temperature to 200-350° C. and a bonding force to 1000-2000 N.
The method according to claim 1, wherein removing the Nb₂N sacrificial layer and the Ta₂N sacrificial layer comprises: removing the Nb₂N sacrificial layer and the Ta₂N sacri-ficial layer by etching with hydrochloric acid and hydrofluoric acid at a volume ratio of 1:1.
The method according to claim 1, wherein transferring the remaining material after removal of the Nb₂N sacrificial layer and the Ta₂N sacrificial layer to the target substrate comprises: activating the remaining material and the target substrate with nitrogen or oxygen, aligning the activated target substrate with the activated remaining material for attachment, and carrying out annealing.
A chip, fabricated by the method according to claim 1.
The method according to claim 1, wherein the material of the original substrate is one of SiC, GaN, sapphire, diamond, Ga₂O₃ and AlN.
The method according to claim 1, wherein in the step of growing the Ta₂N sacrificial layer on the GaN insertion layer, the Ta₂N sacrificial layer with hexagonal crystal structure symmetry is grown on the GaN insertion layer by thin film deposition.
The method according to claim 1, wherein in the step of bonding the GaN wafer with the first surface of the temporary carrier, the wafer bonding is carried out through a wafer bonding machine, a bonding temperature is 150-200° C., a bonding time is 5-10 min, and a pressure is 0.1 MPa.
Layer stacks claimed or described, ordered top of device to substrate.
GaN chip
Materials described outside the worked examples.
Nb₂N sacrificial layer
Nb₂N
GaN insertion layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–50 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 15
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,908,689 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a method for fabricating a GaN chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a hardware structure of a computer device for fabricating a GaN chip according to an embodiment of the present application; and
FIG. 3 is a schematic diagram of a computer storage medium for fabricating a GaN chip according to an embodi- ment of the present application.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a GaN chip, comprising: growing a Nb₂N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb₂N sac-rificial layer; growing a Ta₂N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta₂N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb₂N sacrificial layer and the Ta₂N sacrificial layer; and transferring remaining material after removal of the Nb₂N sacrificial layer and the Ta₂N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.
The method according to claim 1, wherein growing the Nb₂N sacrificial layer on the original substrate comprises: fabricating the Nb₂N sacrificial layer with a thickness of 0-50 nm on the original substrate.
The method according to claim 1, wherein growing the Ta₂N sacrificial layer on the GaN insertion layer comprises: fabricating the Ta₂N sacrificial layer with a thickness of 0-50 nm on the GaN insertion layer.
The method according to claim 1, wherein bonding the GaN wafer with the first surface of the temporary carrier comprises: coating the first surface of the temporary carrier with an adhesive material, placing the temporary carrier on a hot plate for baking, and then cooling the temporary carrier.
The method according to claim 1, wherein bonding the GaN wafer with the first surface of the temporary carrier comprises: controlling a bonding temperature to 200-350° C. and a bonding force to 1000-2000 N.
The method according to claim 1, wherein removing the Nb₂N sacrificial layer and the Ta₂N sacrificial layer comprises: removing the Nb₂N sacrificial layer and the Ta₂N sacri-ficial layer by etching with hydrochloric acid and hydrofluoric acid at a volume ratio of 1:1.
The method according to claim 1, wherein transferring the remaining material after removal of the Nb₂N sacrificial layer and the Ta₂N sacrificial layer to the target substrate comprises: activating the remaining material and the target substrate with nitrogen or oxygen, aligning the activated target substrate with the activated remaining material for attachment, and carrying out annealing.
A chip, fabricated by the method according to claim 1.
The method according to claim 1, wherein the material of the original substrate is one of SiC, GaN, sapphire, diamond, Ga₂O₃ and AlN.
The method according to claim 1, wherein in the step of growing the Ta₂N sacrificial layer on the GaN insertion layer, the Ta₂N sacrificial layer with hexagonal crystal structure symmetry is grown on the GaN insertion layer by thin film deposition.
The method according to claim 1, wherein in the step of bonding the GaN wafer with the first surface of the temporary carrier, the wafer bonding is carried out through a wafer bonding machine, a bonding temperature is 150-200° C., a bonding time is 5-10 min, and a pressure is 0.1 MPa.
Layer stacks claimed or described, ordered top of device to substrate.
GaN chip
Materials described outside the worked examples.
Nb₂N sacrificial layer
Nb₂N
GaN insertion layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–50 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 15
Related documents with shared materials, methods, properties, or citations.
Ta₂N sacrificial layer
Ta₂N
semiconductor layer
hydrochloric acid
HCl
hydrofluoric acid
HF
original substrate material
SiC substrate
SiC
sapphire substrate
diamond substrate
Ga₂O₃ substrate
Ga₂O₃
AlN substrate
AlN
| — |
Duration | 30–60 seconds | — |
Temperature | 200–350 °C | — |
Temperature | 150–200 °C | — |
Duration | 5–10 min | — |
Flow Rate | 50–200 sccm | — |
SELF-ALIGNED SIDEWALL GATE GAN HEMT
Ta₂N sacrificial layer
Ta₂N
semiconductor layer
hydrochloric acid
HCl
hydrofluoric acid
HF
original substrate material
SiC substrate
SiC
sapphire substrate
diamond substrate
Ga₂O₃ substrate
Ga₂O₃
AlN substrate
AlN
| — |
Duration | 30–60 seconds | — |
Temperature | 200–350 °C | — |
Temperature | 150–200 °C | — |
Duration | 5–10 min | — |
Flow Rate | 50–200 sccm | — |
SELF-ALIGNED SIDEWALL GATE GAN HEMT
Ta₂N sacrificial layer
Ta₂N
semiconductor layer
hydrochloric acid
HCl
hydrofluoric acid
HF
original substrate material
SiC substrate
SiC
sapphire substrate
diamond substrate
Ga₂O₃ substrate
Ga₂O₃
AlN substrate
AlN
| — |
Duration | 30–60 seconds | — |
Temperature | 200–350 °C | — |
Temperature | 150–200 °C | — |
Duration | 5–10 min | — |
Flow Rate | 50–200 sccm | — |
SELF-ALIGNED SIDEWALL GATE GAN HEMT
Ta₂N sacrificial layer
Ta₂N
semiconductor layer
hydrochloric acid
HCl
hydrofluoric acid
HF
original substrate material
SiC substrate
SiC
sapphire substrate
diamond substrate
Ga₂O₃ substrate
Ga₂O₃
AlN substrate
AlN
| — |
Duration | 30–60 seconds | — |
Temperature | 200–350 °C | — |
Temperature | 150–200 °C | — |
Duration | 5–10 min | — |
Flow Rate | 50–200 sccm | — |