Patent
Atlas literature
Patent
US 11,328,994Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flowchart illustrating a method for manufacturing an interconnect structure according to one embodiment of the present disclosure. The method may …
FIG. 2A. In one embodiment, the metal interconnect line may include, but not limited to, copper, and the first 5 dielectric layer may include silicon oxide, a …
FIG. 3A. For example, a portion of the metal layer on first dielectric layer 202, a portion of second barrier layer 302, and first hardmask layer 401 may be …
FIG. 4G is a cross-sectional view illustrating an intermediate stage of a substrate structure according to one embodiment of the present disclosure. DETAILED …
FIG. 20 3H may further include a dielectric layer (corresponding to third dielectric layer 209) on the dielectric layer (corresponding to second dielectric …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An interconnect structure, comprising: a substrate; a metal interconnect line including an upper surface and a side surface on the substrate; a graphene layer conformally covering the upper surface and the side surface of the metal interconnect line; a first barrier layer in contact with a surface portion of the substrate; a first dielectric layer on the first barrier layer and in contact with a portion of the graphene layer on the side surface of the metal interconnect line, the dielectric layer being made of a material different from a material of the first barrier layer and having an upper surface flush with an upper surface of the graphene layer, wherein the first dielectric layer has a first portion directly under the metal interconnect line; and a second barrier layer having a first portion directly between the metal interconnect line and the first portion of the first dielectric layer and a second portion directly between the metal interconnect line and the first barrier layer, wherein the first portion of the first dielectric layer is completely surrounded by the first portion of the second barrier layer and the first barrier layer. Currently amended
The interconnect structure of claim 1, wherein the dielectric layer does not cover a portion of the graphene layer on the upper surface of the metal interconnect line. Original
The interconnect structure of claim 1, further comprising: a second dielectric layer on the graphene layer for forming a second interconnect structure. Previously presented
The interconnect structure of claim 1, wherein the dielectric layer further covers a portion of the graphene layer on the upper surface of the metal interconnect line. Original
The interconnect structure of claim 1, further comprising an amorphous carbon layer between the first barrier layer and the dielectric layer. Previously presented
The interconnect structure of claim 1, wherein the first barrier layer comprises SiCN, and the second barrier layer comprises Ta, TaN, or stacked layers of Ta and TaN. Previously presented
The interconnect structure of claim 1, wherein the graphene layer comprises a layer of fluorinated graphene. Original
The interconnect structure of claim 1, wherein the metal interconnect line comprises a damascene structure. Original
The interconnect structure of claim 1, wherein the metal interconnect line comprises copper, and the dielectric layer comprises silicon oxide or a low-k dielectric material. Original
The interconnect structure of claim 1, wherein the graphene layer comprises 1 to 30 layers of monoatomic graphene layers. Previously presented
The interconnect structure of claim 1, wherein the metal interconnect line extends through the dielectric layer and the first barrier layer. Previously presented
The interconnect structure of claim 1, wherein the metal interconnect line comprises a lower portion surrounding a structure comprising a portion of the first barrier layer and a portion of the dielectric layer on the portion of the first barrier layer. Previously presented
Canceled
Canceled
- 20. -4- Canceled
Canceled
An interconnect structure, comprising: a substrate; a metal interconnect line including an upper surface and a side surface on the substrate; a graphene layer on the upper surface and the side surface of the metal interconnect line; a first barrier layer in contact with a surface portion of the substrate; -5- a second barrier layer having a bottom portion between the metal interconnect line and the substrate and a side portion between the metal interconnect line and the first barrier layer; and a dielectric layer on the first barrier on the side surface of the metal interconnect line, surface flash with an upper surface of the graphene
The interconnect structure of claim 25, wherein metal interconnect line is on the side portion of layer and covering a portion of the graphene layer wherein the dielectric layer comprises an upper layer. Withdrawn the graphene layer on the side surface of the second barrier layer. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
Cu interconnect structure with graphene capping (claim 1 embodiment)
Materials described outside the worked examples.
metal interconnect line
graphene layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 600–1500 °C | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,328,994Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flowchart illustrating a method for manufacturing an interconnect structure according to one embodiment of the present disclosure. The method may …
FIG. 2A. In one embodiment, the metal interconnect line may include, but not limited to, copper, and the first 5 dielectric layer may include silicon oxide, a …
FIG. 3A. For example, a portion of the metal layer on first dielectric layer 202, a portion of second barrier layer 302, and first hardmask layer 401 may be …
FIG. 4G is a cross-sectional view illustrating an intermediate stage of a substrate structure according to one embodiment of the present disclosure. DETAILED …
FIG. 20 3H may further include a dielectric layer (corresponding to third dielectric layer 209) on the dielectric layer (corresponding to second dielectric …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An interconnect structure, comprising: a substrate; a metal interconnect line including an upper surface and a side surface on the substrate; a graphene layer conformally covering the upper surface and the side surface of the metal interconnect line; a first barrier layer in contact with a surface portion of the substrate; a first dielectric layer on the first barrier layer and in contact with a portion of the graphene layer on the side surface of the metal interconnect line, the dielectric layer being made of a material different from a material of the first barrier layer and having an upper surface flush with an upper surface of the graphene layer, wherein the first dielectric layer has a first portion directly under the metal interconnect line; and a second barrier layer having a first portion directly between the metal interconnect line and the first portion of the first dielectric layer and a second portion directly between the metal interconnect line and the first barrier layer, wherein the first portion of the first dielectric layer is completely surrounded by the first portion of the second barrier layer and the first barrier layer. Currently amended
The interconnect structure of claim 1, wherein the dielectric layer does not cover a portion of the graphene layer on the upper surface of the metal interconnect line. Original
The interconnect structure of claim 1, further comprising: a second dielectric layer on the graphene layer for forming a second interconnect structure. Previously presented
The interconnect structure of claim 1, wherein the dielectric layer further covers a portion of the graphene layer on the upper surface of the metal interconnect line. Original
The interconnect structure of claim 1, further comprising an amorphous carbon layer between the first barrier layer and the dielectric layer. Previously presented
The interconnect structure of claim 1, wherein the first barrier layer comprises SiCN, and the second barrier layer comprises Ta, TaN, or stacked layers of Ta and TaN. Previously presented
The interconnect structure of claim 1, wherein the graphene layer comprises a layer of fluorinated graphene. Original
The interconnect structure of claim 1, wherein the metal interconnect line comprises a damascene structure. Original
The interconnect structure of claim 1, wherein the metal interconnect line comprises copper, and the dielectric layer comprises silicon oxide or a low-k dielectric material. Original
The interconnect structure of claim 1, wherein the graphene layer comprises 1 to 30 layers of monoatomic graphene layers. Previously presented
The interconnect structure of claim 1, wherein the metal interconnect line extends through the dielectric layer and the first barrier layer. Previously presented
The interconnect structure of claim 1, wherein the metal interconnect line comprises a lower portion surrounding a structure comprising a portion of the first barrier layer and a portion of the dielectric layer on the portion of the first barrier layer. Previously presented
Canceled
Canceled
- 20. -4- Canceled
Canceled
An interconnect structure, comprising: a substrate; a metal interconnect line including an upper surface and a side surface on the substrate; a graphene layer on the upper surface and the side surface of the metal interconnect line; a first barrier layer in contact with a surface portion of the substrate; -5- a second barrier layer having a bottom portion between the metal interconnect line and the substrate and a side portion between the metal interconnect line and the first barrier layer; and a dielectric layer on the first barrier on the side surface of the metal interconnect line, surface flash with an upper surface of the graphene
The interconnect structure of claim 25, wherein metal interconnect line is on the side portion of layer and covering a portion of the graphene layer wherein the dielectric layer comprises an upper layer. Withdrawn the graphene layer on the side surface of the second barrier layer. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
Cu interconnect structure with graphene capping (claim 1 embodiment)
Materials described outside the worked examples.
metal interconnect line
graphene layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 600–1500 °C | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,328,994Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flowchart illustrating a method for manufacturing an interconnect structure according to one embodiment of the present disclosure. The method may …
FIG. 2A. In one embodiment, the metal interconnect line may include, but not limited to, copper, and the first 5 dielectric layer may include silicon oxide, a …
FIG. 3A. For example, a portion of the metal layer on first dielectric layer 202, a portion of second barrier layer 302, and first hardmask layer 401 may be …
FIG. 4G is a cross-sectional view illustrating an intermediate stage of a substrate structure according to one embodiment of the present disclosure. DETAILED …
FIG. 20 3H may further include a dielectric layer (corresponding to third dielectric layer 209) on the dielectric layer (corresponding to second dielectric …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An interconnect structure, comprising: a substrate; a metal interconnect line including an upper surface and a side surface on the substrate; a graphene layer conformally covering the upper surface and the side surface of the metal interconnect line; a first barrier layer in contact with a surface portion of the substrate; a first dielectric layer on the first barrier layer and in contact with a portion of the graphene layer on the side surface of the metal interconnect line, the dielectric layer being made of a material different from a material of the first barrier layer and having an upper surface flush with an upper surface of the graphene layer, wherein the first dielectric layer has a first portion directly under the metal interconnect line; and a second barrier layer having a first portion directly between the metal interconnect line and the first portion of the first dielectric layer and a second portion directly between the metal interconnect line and the first barrier layer, wherein the first portion of the first dielectric layer is completely surrounded by the first portion of the second barrier layer and the first barrier layer. Currently amended
The interconnect structure of claim 1, wherein the dielectric layer does not cover a portion of the graphene layer on the upper surface of the metal interconnect line. Original
The interconnect structure of claim 1, further comprising: a second dielectric layer on the graphene layer for forming a second interconnect structure. Previously presented
The interconnect structure of claim 1, wherein the dielectric layer further covers a portion of the graphene layer on the upper surface of the metal interconnect line. Original
The interconnect structure of claim 1, further comprising an amorphous carbon layer between the first barrier layer and the dielectric layer. Previously presented
The interconnect structure of claim 1, wherein the first barrier layer comprises SiCN, and the second barrier layer comprises Ta, TaN, or stacked layers of Ta and TaN. Previously presented
The interconnect structure of claim 1, wherein the graphene layer comprises a layer of fluorinated graphene. Original
The interconnect structure of claim 1, wherein the metal interconnect line comprises a damascene structure. Original
The interconnect structure of claim 1, wherein the metal interconnect line comprises copper, and the dielectric layer comprises silicon oxide or a low-k dielectric material. Original
The interconnect structure of claim 1, wherein the graphene layer comprises 1 to 30 layers of monoatomic graphene layers. Previously presented
The interconnect structure of claim 1, wherein the metal interconnect line extends through the dielectric layer and the first barrier layer. Previously presented
The interconnect structure of claim 1, wherein the metal interconnect line comprises a lower portion surrounding a structure comprising a portion of the first barrier layer and a portion of the dielectric layer on the portion of the first barrier layer. Previously presented
Canceled
Canceled
- 20. -4- Canceled
Canceled
An interconnect structure, comprising: a substrate; a metal interconnect line including an upper surface and a side surface on the substrate; a graphene layer on the upper surface and the side surface of the metal interconnect line; a first barrier layer in contact with a surface portion of the substrate; -5- a second barrier layer having a bottom portion between the metal interconnect line and the substrate and a side portion between the metal interconnect line and the first barrier layer; and a dielectric layer on the first barrier on the side surface of the metal interconnect line, surface flash with an upper surface of the graphene
The interconnect structure of claim 25, wherein metal interconnect line is on the side portion of layer and covering a portion of the graphene layer wherein the dielectric layer comprises an upper layer. Withdrawn the graphene layer on the side surface of the second barrier layer. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
Cu interconnect structure with graphene capping (claim 1 embodiment)
Materials described outside the worked examples.
metal interconnect line
graphene layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 600–1500 °C | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,328,994Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flowchart illustrating a method for manufacturing an interconnect structure according to one embodiment of the present disclosure. The method may …
FIG. 2A. In one embodiment, the metal interconnect line may include, but not limited to, copper, and the first 5 dielectric layer may include silicon oxide, a …
FIG. 3A. For example, a portion of the metal layer on first dielectric layer 202, a portion of second barrier layer 302, and first hardmask layer 401 may be …
FIG. 4G is a cross-sectional view illustrating an intermediate stage of a substrate structure according to one embodiment of the present disclosure. DETAILED …
FIG. 20 3H may further include a dielectric layer (corresponding to third dielectric layer 209) on the dielectric layer (corresponding to second dielectric …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An interconnect structure, comprising: a substrate; a metal interconnect line including an upper surface and a side surface on the substrate; a graphene layer conformally covering the upper surface and the side surface of the metal interconnect line; a first barrier layer in contact with a surface portion of the substrate; a first dielectric layer on the first barrier layer and in contact with a portion of the graphene layer on the side surface of the metal interconnect line, the dielectric layer being made of a material different from a material of the first barrier layer and having an upper surface flush with an upper surface of the graphene layer, wherein the first dielectric layer has a first portion directly under the metal interconnect line; and a second barrier layer having a first portion directly between the metal interconnect line and the first portion of the first dielectric layer and a second portion directly between the metal interconnect line and the first barrier layer, wherein the first portion of the first dielectric layer is completely surrounded by the first portion of the second barrier layer and the first barrier layer. Currently amended
The interconnect structure of claim 1, wherein the dielectric layer does not cover a portion of the graphene layer on the upper surface of the metal interconnect line. Original
The interconnect structure of claim 1, further comprising: a second dielectric layer on the graphene layer for forming a second interconnect structure. Previously presented
The interconnect structure of claim 1, wherein the dielectric layer further covers a portion of the graphene layer on the upper surface of the metal interconnect line. Original
The interconnect structure of claim 1, further comprising an amorphous carbon layer between the first barrier layer and the dielectric layer. Previously presented
The interconnect structure of claim 1, wherein the first barrier layer comprises SiCN, and the second barrier layer comprises Ta, TaN, or stacked layers of Ta and TaN. Previously presented
The interconnect structure of claim 1, wherein the graphene layer comprises a layer of fluorinated graphene. Original
The interconnect structure of claim 1, wherein the metal interconnect line comprises a damascene structure. Original
The interconnect structure of claim 1, wherein the metal interconnect line comprises copper, and the dielectric layer comprises silicon oxide or a low-k dielectric material. Original
The interconnect structure of claim 1, wherein the graphene layer comprises 1 to 30 layers of monoatomic graphene layers. Previously presented
The interconnect structure of claim 1, wherein the metal interconnect line extends through the dielectric layer and the first barrier layer. Previously presented
The interconnect structure of claim 1, wherein the metal interconnect line comprises a lower portion surrounding a structure comprising a portion of the first barrier layer and a portion of the dielectric layer on the portion of the first barrier layer. Previously presented
Canceled
Canceled
- 20. -4- Canceled
Canceled
An interconnect structure, comprising: a substrate; a metal interconnect line including an upper surface and a side surface on the substrate; a graphene layer on the upper surface and the side surface of the metal interconnect line; a first barrier layer in contact with a surface portion of the substrate; -5- a second barrier layer having a bottom portion between the metal interconnect line and the substrate and a side portion between the metal interconnect line and the first barrier layer; and a dielectric layer on the first barrier on the side surface of the metal interconnect line, surface flash with an upper surface of the graphene
The interconnect structure of claim 25, wherein metal interconnect line is on the side portion of layer and covering a portion of the graphene layer wherein the dielectric layer comprises an upper layer. Withdrawn the graphene layer on the side surface of the second barrier layer. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
Cu interconnect structure with graphene capping (claim 1 embodiment)
Materials described outside the worked examples.
metal interconnect line
graphene layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 600–1500 °C | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
Cu interconnect structure with graphene capping (claim 25 embodiment)
first dielectric layer
first barrier layer
second barrier layer
second dielectric layer
third barrier layer
third dielectric layer
amorphous carbon layer
SiCN
Ta
TaN
fluorinated graphene
copper
Cu
silicon oxide
SiO₂
low-k dielectric material
methane
CH₄
hydrogen
H₂
| 5–300 minutes |
| — |
GRAPHENE AND METAL INTERCONNECTS WITH REDUCED CONTACT RESISTANCE
Cu interconnect structure with graphene capping (claim 25 embodiment)
first dielectric layer
first barrier layer
second barrier layer
second dielectric layer
third barrier layer
third dielectric layer
amorphous carbon layer
SiCN
Ta
TaN
fluorinated graphene
copper
Cu
silicon oxide
SiO₂
low-k dielectric material
methane
CH₄
hydrogen
H₂
| 5–300 minutes |
| — |
GRAPHENE AND METAL INTERCONNECTS WITH REDUCED CONTACT RESISTANCE
Cu interconnect structure with graphene capping (claim 25 embodiment)
first dielectric layer
first barrier layer
second barrier layer
second dielectric layer
third barrier layer
third dielectric layer
amorphous carbon layer
SiCN
Ta
TaN
fluorinated graphene
copper
Cu
silicon oxide
SiO₂
low-k dielectric material
methane
CH₄
hydrogen
H₂
| 5–300 minutes |
| — |
GRAPHENE AND METAL INTERCONNECTS WITH REDUCED CONTACT RESISTANCE
Cu interconnect structure with graphene capping (claim 25 embodiment)
first dielectric layer
first barrier layer
second barrier layer
second dielectric layer
third barrier layer
third dielectric layer
amorphous carbon layer
SiCN
Ta
TaN
fluorinated graphene
copper
Cu
silicon oxide
SiO₂
low-k dielectric material
methane
CH₄
hydrogen
H₂
| 5–300 minutes |
| — |
GRAPHENE AND METAL INTERCONNECTS WITH REDUCED CONTACT RESISTANCE
