A method o f f abricating a gallium nitride semiconductor lateral device structure, the method comprising: forming a continuous gallium n itr ide layer on a substrate; forming a periodic array of columns (5) and tr enches within said gallium n itr ide layer using photolithography techniques; growing a second gallium ni tri de layer comprising periodic arrays of high and low defect density regions using lateral epitaxial growth techniques; wherein on top o f t he second gallium nitride layer that comprises the low defect density regions ove r tr enches there is a gate (20) comprising a Schottky contact; the method further comprising vertically aligning an active region of a semiconductor lateral device with the low defect density regions o f t he second gallium nitride layer, wherein said semiconductor lateral device extends between greater than two columns (5) and has multip le active regions wherein each active region is aligned so tha t t he curren t fl ows only in the low defect densi ty r egions; wherein said semiconducto r d evice active regions are between an edge of a Source (S) and an edge of a Drain (D), and further wherein the Source (S) edge and Drain (D) are positioned so that curren t fl ows only in low defec t d ensi ty r egions; wherein the curren t f lows only in areas of low defect density and Source (S), Gate (G), and Drain (D) are on one plane, on top o f t he device; and further wherein said gate (20) fi nger (20a) is within and on top of the low defect density region. withdrawn

A gallium n itri de semiconductor made-by4he-met Gf-Glamwth galu idsmcnutr device comprising: a fi rs t g allium n itri de layer comprising a plura lit y of gallium n itri de columns and trenches etched into said fi rst gallium n itr ide layer and a firs t di slocation density; and a second gallium n itri de laye r t hat comprises of two regions, a fi rs t r egion tha t i s adjacen t t o the side walls o f t he gallium nitride columns further comprisinQ a second layer o f r ecions with a low and a high dislocation density having a_ lower dislocation density and a second region that extends over said gallium n itr ide columns and com pri ses a higher dislocation density than the dislocation density of the first region; wherein on to o f t he second allium n itrid e Iave r t hat com rises a low defect densit re ion ove r tr enches there is a Schottky contact, said Schottky contact com rised of about 500 A of nickel and about 1,500 A of old; the device fu rth er com rising ve rti call ali ned active re ions of a semiconductor lateral device with the low defect densit regions o f t he second alliurn n itr ide ia er wherein sa id semiconductor lateral device extends be ond the to of two or more couamn the rn hs onl tin te wregi wherein each active rdeifec is aline r s tha t t e' curren~ t f lows only ine the low defect density regions; wherein said sericonductor device active regions are between an edge of a Source (S) and an edge of a Drain (D), and further wherein the Source (5) edge and Drain (D) are positioned so that curren t fl ows only in low defect density regions: wherein the curren t fl ows only in areas of low defect density and Source (S), Gate (G). and Drain (D) are on one plane, on top o f t he device: and further wherein said gate (20) finger (20a) is within and on top o f t he low defect density regior

A semiconducto r d evice 1, the semiconductor dvico comprising: a substrate; a plurality of gallium n itrid e columns coupled to sa id substrate; a plurality o f g allium n itrid e tr enches, couple d t o said substrate, wherein each of sa id plurality o f g allium n itrid e columns are pos iti oned alterate with each of said plurality of gallium n itrid e tr enches; a low defec t d ensity region in the second gallium n itrid e laye r f ormed over said gallium n itrid e tr enches; and an active region of a tr ansistor w the device further comprising ve rti cally aligned active regions of a semiconductor latera l d evice with the low defec t d ensity regions o f t he second gallium n itrid e layer, wherein sa id semiconductor lateral device extends beyond the top of two or more columns te rnd fls onl tin tie wregion de reins h ative region is aliged s tha t t he curren~ t f lows only ine the ow defec t d ensity regions;° wherein sa id semiconducto r d evice active regions are between an edge of a Source (S) and an edge of a Drain (D), an d f urther wherein the Source (S) edge and Drain (D) are positioned so that curren t fl ows only in low defec t d ensity regions; wherein the curren t fl ows only in areas of l ow defe c t d ensity and Source (S) Gate (G).and Drain (D) are on one plane, on to p of t he device: and further wherein sa id gate (20) finger (20a) is within and on to p of t he low defe ct dtre gion.

A method o f f abricating a gallium nitride semiconductor lateral device structure, the method comprising: forming a continuous gallium n itr ide layer on a substrate; forming a periodic array of columns (5) and tr enches within said gallium n itr ide layer using photolithography techniques; growing a second gallium ni tri de layer comprising periodic arrays of high and low defect density regions using lateral epitaxial growth techniques; wherein on top o f t he second gallium nitride layer that comprises the low defect density regions ove r tr enches there is a gate (20) comprising a Schottky contact; the method further comprising vertically aligning an active region of a semiconductor lateral device with the low defect density regions o f t he second gallium nitride layer, wherein said semiconductor lateral device extends between greater than two columns (5) and has multip le active regions wherein each active region is aligned so tha t t he curren t fl ows only in the low defect densi ty r egions; wherein said semiconducto r d evice active regions are between an edge of a Source (S) and an edge of a Drain (D), and further wherein the Source (S) edge and Drain (D) are positioned so that curren t fl ows only in low defec t d ensi ty r egions; wherein the curren t f lows only in areas of low defect density and Source (S), Gate (G), and Drain (D) are on one plane, on top o f t he device; and further wherein said gate (20) fi nger (20a) is within and on top of the low defect density region. withdrawn

A gallium n itri de semiconductor made-by4he-met Gf-Glamwth galu idsmcnutr device comprising: a fi rs t g allium n itri de layer comprising a plura lit y of gallium n itri de columns and trenches etched into said fi rst gallium n itr ide layer and a firs t di slocation density; and a second gallium n itri de laye r t hat comprises of two regions, a fi rs t r egion tha t i s adjacen t t o the side walls o f t he gallium nitride columns further comprisinQ a second layer o f r ecions with a low and a high dislocation density having a_ lower dislocation density and a second region that extends over said gallium n itr ide columns and com pri ses a higher dislocation density than the dislocation density of the first region; wherein on to o f t he second allium n itrid e Iave r t hat com rises a low defect densit re ion ove r tr enches there is a Schottky contact, said Schottky contact com rised of about 500 A of nickel and about 1,500 A of old; the device fu rth er com rising ve rti call ali ned active re ions of a semiconductor lateral device with the low defect densit regions o f t he second alliurn n itr ide ia er wherein sa id semiconductor lateral device extends be ond the to of two or more couamn the rn hs onl tin te wregi wherein each active rdeifec is aline r s tha t t e' curren~ t f lows only ine the low defect density regions; wherein said sericonductor device active regions are between an edge of a Source (S) and an edge of a Drain (D), and further wherein the Source (5) edge and Drain (D) are positioned so that curren t fl ows only in low defect density regions: wherein the curren t fl ows only in areas of low defect density and Source (S), Gate (G). and Drain (D) are on one plane, on top o f t he device: and further wherein said gate (20) finger (20a) is within and on top o f t he low defect density regior

A semiconducto r d evice 1, the semiconductor dvico comprising: a substrate; a plurality of gallium n itrid e columns coupled to sa id substrate; a plurality o f g allium n itrid e tr enches, couple d t o said substrate, wherein each of sa id plurality o f g allium n itrid e columns are pos iti oned alterate with each of said plurality of gallium n itrid e tr enches; a low defec t d ensity region in the second gallium n itrid e laye r f ormed over said gallium n itrid e tr enches; and an active region of a tr ansistor w the device further comprising ve rti cally aligned active regions of a semiconductor latera l d evice with the low defec t d ensity regions o f t he second gallium n itrid e layer, wherein sa id semiconductor lateral device extends beyond the top of two or more columns te rnd fls onl tin tie wregion de reins h ative region is aliged s tha t t he curren~ t f lows only ine the ow defec t d ensity regions;° wherein sa id semiconducto r d evice active regions are between an edge of a Source (S) and an edge of a Drain (D), an d f urther wherein the Source (S) edge and Drain (D) are positioned so that curren t fl ows only in low defec t d ensity regions; wherein the curren t fl ows only in areas of l ow defe c t d ensity and Source (S) Gate (G).and Drain (D) are on one plane, on to p of t he device: and further wherein sa id gate (20) finger (20a) is within and on to p of t he low defe ct dtre gion.

A method o f f abricating a gallium nitride semiconductor lateral device structure, the method comprising: forming a continuous gallium n itr ide layer on a substrate; forming a periodic array of columns (5) and tr enches within said gallium n itr ide layer using photolithography techniques; growing a second gallium ni tri de layer comprising periodic arrays of high and low defect density regions using lateral epitaxial growth techniques; wherein on top o f t he second gallium nitride layer that comprises the low defect density regions ove r tr enches there is a gate (20) comprising a Schottky contact; the method further comprising vertically aligning an active region of a semiconductor lateral device with the low defect density regions o f t he second gallium nitride layer, wherein said semiconductor lateral device extends between greater than two columns (5) and has multip le active regions wherein each active region is aligned so tha t t he curren t fl ows only in the low defect densi ty r egions; wherein said semiconducto r d evice active regions are between an edge of a Source (S) and an edge of a Drain (D), and further wherein the Source (S) edge and Drain (D) are positioned so that curren t fl ows only in low defec t d ensi ty r egions; wherein the curren t f lows only in areas of low defect density and Source (S), Gate (G), and Drain (D) are on one plane, on top o f t he device; and further wherein said gate (20) fi nger (20a) is within and on top of the low defect density region. withdrawn

A gallium n itri de semiconductor made-by4he-met Gf-Glamwth galu idsmcnutr device comprising: a fi rs t g allium n itri de layer comprising a plura lit y of gallium n itri de columns and trenches etched into said fi rst gallium n itr ide layer and a firs t di slocation density; and a second gallium n itri de laye r t hat comprises of two regions, a fi rs t r egion tha t i s adjacen t t o the side walls o f t he gallium nitride columns further comprisinQ a second layer o f r ecions with a low and a high dislocation density having a_ lower dislocation density and a second region that extends over said gallium n itr ide columns and com pri ses a higher dislocation density than the dislocation density of the first region; wherein on to o f t he second allium n itrid e Iave r t hat com rises a low defect densit re ion ove r tr enches there is a Schottky contact, said Schottky contact com rised of about 500 A of nickel and about 1,500 A of old; the device fu rth er com rising ve rti call ali ned active re ions of a semiconductor lateral device with the low defect densit regions o f t he second alliurn n itr ide ia er wherein sa id semiconductor lateral device extends be ond the to of two or more couamn the rn hs onl tin te wregi wherein each active rdeifec is aline r s tha t t e' curren~ t f lows only ine the low defect density regions; wherein said sericonductor device active regions are between an edge of a Source (S) and an edge of a Drain (D), and further wherein the Source (5) edge and Drain (D) are positioned so that curren t fl ows only in low defect density regions: wherein the curren t fl ows only in areas of low defect density and Source (S), Gate (G). and Drain (D) are on one plane, on top o f t he device: and further wherein said gate (20) finger (20a) is within and on top o f t he low defect density regior

A semiconducto r d evice 1, the semiconductor dvico comprising: a substrate; a plurality of gallium n itrid e columns coupled to sa id substrate; a plurality o f g allium n itrid e tr enches, couple d t o said substrate, wherein each of sa id plurality o f g allium n itrid e columns are pos iti oned alterate with each of said plurality of gallium n itrid e tr enches; a low defec t d ensity region in the second gallium n itrid e laye r f ormed over said gallium n itrid e tr enches; and an active region of a tr ansistor w the device further comprising ve rti cally aligned active regions of a semiconductor latera l d evice with the low defec t d ensity regions o f t he second gallium n itrid e layer, wherein sa id semiconductor lateral device extends beyond the top of two or more columns te rnd fls onl tin tie wregion de reins h ative region is aliged s tha t t he curren~ t f lows only ine the ow defec t d ensity regions;° wherein sa id semiconducto r d evice active regions are between an edge of a Source (S) and an edge of a Drain (D), an d f urther wherein the Source (S) edge and Drain (D) are positioned so that curren t fl ows only in low defec t d ensity regions; wherein the curren t fl ows only in areas of l ow defe c t d ensity and Source (S) Gate (G).and Drain (D) are on one plane, on to p of t he device: and further wherein sa id gate (20) finger (20a) is within and on to p of t he low defe ct dtre gion.

A method o f f abricating a gallium nitride semiconductor lateral device structure, the method comprising: forming a continuous gallium n itr ide layer on a substrate; forming a periodic array of columns (5) and tr enches within said gallium n itr ide layer using photolithography techniques; growing a second gallium ni tri de layer comprising periodic arrays of high and low defect density regions using lateral epitaxial growth techniques; wherein on top o f t he second gallium nitride layer that comprises the low defect density regions ove r tr enches there is a gate (20) comprising a Schottky contact; the method further comprising vertically aligning an active region of a semiconductor lateral device with the low defect density regions o f t he second gallium nitride layer, wherein said semiconductor lateral device extends between greater than two columns (5) and has multip le active regions wherein each active region is aligned so tha t t he curren t fl ows only in the low defect densi ty r egions; wherein said semiconducto r d evice active regions are between an edge of a Source (S) and an edge of a Drain (D), and further wherein the Source (S) edge and Drain (D) are positioned so that curren t fl ows only in low defec t d ensi ty r egions; wherein the curren t f lows only in areas of low defect density and Source (S), Gate (G), and Drain (D) are on one plane, on top o f t he device; and further wherein said gate (20) fi nger (20a) is within and on top of the low defect density region. withdrawn

A gallium n itri de semiconductor made-by4he-met Gf-Glamwth galu idsmcnutr device comprising: a fi rs t g allium n itri de layer comprising a plura lit y of gallium n itri de columns and trenches etched into said fi rst gallium n itr ide layer and a firs t di slocation density; and a second gallium n itri de laye r t hat comprises of two regions, a fi rs t r egion tha t i s adjacen t t o the side walls o f t he gallium nitride columns further comprisinQ a second layer o f r ecions with a low and a high dislocation density having a_ lower dislocation density and a second region that extends over said gallium n itr ide columns and com pri ses a higher dislocation density than the dislocation density of the first region; wherein on to o f t he second allium n itrid e Iave r t hat com rises a low defect densit re ion ove r tr enches there is a Schottky contact, said Schottky contact com rised of about 500 A of nickel and about 1,500 A of old; the device fu rth er com rising ve rti call ali ned active re ions of a semiconductor lateral device with the low defect densit regions o f t he second alliurn n itr ide ia er wherein sa id semiconductor lateral device extends be ond the to of two or more couamn the rn hs onl tin te wregi wherein each active rdeifec is aline r s tha t t e' curren~ t f lows only ine the low defect density regions; wherein said sericonductor device active regions are between an edge of a Source (S) and an edge of a Drain (D), and further wherein the Source (5) edge and Drain (D) are positioned so that curren t fl ows only in low defect density regions: wherein the curren t fl ows only in areas of low defect density and Source (S), Gate (G). and Drain (D) are on one plane, on top o f t he device: and further wherein said gate (20) finger (20a) is within and on top o f t he low defect density regior

A semiconducto r d evice 1, the semiconductor dvico comprising: a substrate; a plurality of gallium n itrid e columns coupled to sa id substrate; a plurality o f g allium n itrid e tr enches, couple d t o said substrate, wherein each of sa id plurality o f g allium n itrid e columns are pos iti oned alterate with each of said plurality of gallium n itrid e tr enches; a low defec t d ensity region in the second gallium n itrid e laye r f ormed over said gallium n itrid e tr enches; and an active region of a tr ansistor w the device further comprising ve rti cally aligned active regions of a semiconductor latera l d evice with the low defec t d ensity regions o f t he second gallium n itrid e layer, wherein sa id semiconductor lateral device extends beyond the top of two or more columns te rnd fls onl tin tie wregion de reins h ative region is aliged s tha t t he curren~ t f lows only ine the ow defec t d ensity regions;° wherein sa id semiconducto r d evice active regions are between an edge of a Source (S) and an edge of a Drain (D), an d f urther wherein the Source (S) edge and Drain (D) are positioned so that curren t fl ows only in low defec t d ensity regions; wherein the curren t fl ows only in areas of l ow defe c t d ensity and Source (S) Gate (G).and Drain (D) are on one plane, on to p of t he device: and further wherein sa id gate (20) finger (20a) is within and on to p of t he low defe ct dtre gion.