Patent
US 9,233,844GRADED ALUMINUM-GALLIUM-NITRIDE AND SUPERLATTICE BUFFER LAYER FOR III-V NITRIDE LAYER ON SILICON SUBSTRATE
Chi-Ming Chen
US
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Patent
Atlas literature
Patent
US 9,233,844Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a silicon substrate having a first lattice structure; a group I II nitride layer overlying the silicon substrate and having a second lattice structure; a lattice-matching structure arranged between the silicon substrate and the group I II nitride layer, comprising: a first buffer region disposed over the substrate and comprising a first aluminum nitride (AIN) layer in direct contact with a second AIN layer and with the silicon substrate; a second buffer region disposed over the first buffer region and comprising a plurality of graded A IxGa 1.x N layers in direct contact with one another and with the second AIN layer; and a superlattice structure comprising a first AIGaN layer in direct contact with one of the plurality of graded A IxGa 1.x N layers, a second AIGaN layer in direct contact with the first AIGaN layer, a third AIGaN layer in direct contact with the second AIGaN layer and a fourth AIGaN layer in direct contact with the third AIGaN layer, wherein the first AIGaN layer and the third AIGaN layer each have a first aluminum concentration that is greater than a second aluminum contraction of each of the second AIGaN layer and the fourth AIGaN layer.
The integrated circuit of claim 1, wherein the first AIN layer has a thickness from about 20 nm to about 80 nm, and the second AIN layer P₂₀₁₂₀₃₃₅ US00 App. No. 13/534,368 Page 3 has a different thickness of from about 50 to about 200 nm.
The integrated circuit of claim 1, wherein the plurality of graded A IxGa 1.x N layers have aluminum content ranges distinct from one another.
1 0. The integrated circuit of claim 1, wherein the first AIGaN layer and the third AIGaN layer have a smaller thickness than the second AIGaN layer and the fourth AIGaN layer. P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 4
1 2. The integrated circuit of claim 1, wherein the group I II nitride layer comprises a GaN layer.
The integrated circuit of claim 1, wherein the first AIGaN layer and the third AIGaN layer have an aluminum concentration in a range of greater than 0.8 and less than 1 and the second AIGaN layer and the fourth AIGaN layer have an aluminum concentration in a range of greater than 0.1 and less than 0.3.
The integrated circuit of claim 1, further comprising: a source region comprising a metal material and in direct contact with an upper surface of the group I II nitride layer; a drain region comprising the metal material and in direct contact with the upper surface of the group I II nitride layer; and an active layer in direct contact with the upper surface of the group I II nitride layer and with sidewalls of the source region and the drain region.
The integrated circuit of claim 1, wherein the plurality of graded A IxGa 1.x N layers comprise a first graded A IxGa 1.x N layer, a second P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 7 graded AI xGa 1.x N layer, and a third graded AI xGa 1.x N layer, wherein the third graded AIxGa 1.x N layer has a greater thickness than the first graded AI xGa 1.x N layer and the second graded A IxGa 1.x N layer.
The integrated circuit of claim 1, wherein an aluminum content of the first AIGaN layer is a graded aluminum content.
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A method of fabricating a semiconductor structure, comprising: providing a substrate; forming a lattice-matching structure on the substrate, the lattice-matching structure comprising: a first buffer region disposed over the substrate and comprising a plurality of aluminum nitride (AIN) layers in direct contact with one another and with the substrate, a second buffer region disposed over the first buffer region and comprising a plurality of graded AIGaN layers in direct contact with one another and with one of the plurality of AIN layers, and a superlattice structure comprising a first AIGaN layer in direct contact with one of the plurality of graded AIGaN layers, a second AIGaN layer in direct contact with the first AIGaN layer, a third AIGaN layer in direct contact with the second AIGaN layer and a fourth AIGaN layer in direct contact with the third AIGaN layer, wherein x is in a range of between greater than 0.8 and less than 1 and y is in a range of between greater than 0.1 and less than 0.3; and P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 5 forming a group I II nitride layer overlying the lattice-matching structure.
The method of claim 14, wherein forming the lattice-matching structure comprises forming the first buffer region by: forming a first layer of AIN onto and in direct contact with the substrate at a first temperature; and forming a second layer of AIN onto and in direct contact with the first layer of AIN at a second temperature greater than the first temperature.
The method of claim 14, wherein the plurality of graded AIGaN layers have distinct aluminum content ranges.
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A semiconductor structure, comprising: a semiconductor substrate; a first buffer region disposed over the semiconductor substrate and comprising a plurality of AIN layers in direct contact with one another and with the semiconductor substrate; a second buffer region arranged over the first buffer region and comprising a plurality of graded AIGaN layers in direct contact with one another and with one of the plurality of AIN layers; a superlattice structure comprising a first AIGaN layer in direct contact with one of the plurality of graded A I[[x]]Ga[[1 x]]N layers, a second AIGaN layer in direct contact with the first AIGaN layer, a third AIGaN layer in direct contact with the second AIGaN layer and a fourth AIGaN layer in direct contact with the third AIGaN layer, wherein x is in a range of between greater than 0.8 and less than 1 and y is in a range of between greater than 0.1 and less than 0.3; and P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 6 a group I II nitride layer overlying the superlattice structure.
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Layer stacks claimed or described, ordered top of device to substrate.
Integrated circuit with lattice-matching structure on silicon (Group III nitride on Si)
Materials described outside the worked examples.
GaN (Group III nitride layer)
GaN
Aluminum nitride (AlN)
AlN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–80 nm | — |
Thickness | 50–200 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,233,844Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a silicon substrate having a first lattice structure; a group I II nitride layer overlying the silicon substrate and having a second lattice structure; a lattice-matching structure arranged between the silicon substrate and the group I II nitride layer, comprising: a first buffer region disposed over the substrate and comprising a first aluminum nitride (AIN) layer in direct contact with a second AIN layer and with the silicon substrate; a second buffer region disposed over the first buffer region and comprising a plurality of graded A IxGa 1.x N layers in direct contact with one another and with the second AIN layer; and a superlattice structure comprising a first AIGaN layer in direct contact with one of the plurality of graded A IxGa 1.x N layers, a second AIGaN layer in direct contact with the first AIGaN layer, a third AIGaN layer in direct contact with the second AIGaN layer and a fourth AIGaN layer in direct contact with the third AIGaN layer, wherein the first AIGaN layer and the third AIGaN layer each have a first aluminum concentration that is greater than a second aluminum contraction of each of the second AIGaN layer and the fourth AIGaN layer.
The integrated circuit of claim 1, wherein the first AIN layer has a thickness from about 20 nm to about 80 nm, and the second AIN layer P₂₀₁₂₀₃₃₅ US00 App. No. 13/534,368 Page 3 has a different thickness of from about 50 to about 200 nm.
The integrated circuit of claim 1, wherein the plurality of graded A IxGa 1.x N layers have aluminum content ranges distinct from one another.
1 0. The integrated circuit of claim 1, wherein the first AIGaN layer and the third AIGaN layer have a smaller thickness than the second AIGaN layer and the fourth AIGaN layer. P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 4
1 2. The integrated circuit of claim 1, wherein the group I II nitride layer comprises a GaN layer.
The integrated circuit of claim 1, wherein the first AIGaN layer and the third AIGaN layer have an aluminum concentration in a range of greater than 0.8 and less than 1 and the second AIGaN layer and the fourth AIGaN layer have an aluminum concentration in a range of greater than 0.1 and less than 0.3.
The integrated circuit of claim 1, further comprising: a source region comprising a metal material and in direct contact with an upper surface of the group I II nitride layer; a drain region comprising the metal material and in direct contact with the upper surface of the group I II nitride layer; and an active layer in direct contact with the upper surface of the group I II nitride layer and with sidewalls of the source region and the drain region.
The integrated circuit of claim 1, wherein the plurality of graded A IxGa 1.x N layers comprise a first graded A IxGa 1.x N layer, a second P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 7 graded AI xGa 1.x N layer, and a third graded AI xGa 1.x N layer, wherein the third graded AIxGa 1.x N layer has a greater thickness than the first graded AI xGa 1.x N layer and the second graded A IxGa 1.x N layer.
The integrated circuit of claim 1, wherein an aluminum content of the first AIGaN layer is a graded aluminum content.
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A method of fabricating a semiconductor structure, comprising: providing a substrate; forming a lattice-matching structure on the substrate, the lattice-matching structure comprising: a first buffer region disposed over the substrate and comprising a plurality of aluminum nitride (AIN) layers in direct contact with one another and with the substrate, a second buffer region disposed over the first buffer region and comprising a plurality of graded AIGaN layers in direct contact with one another and with one of the plurality of AIN layers, and a superlattice structure comprising a first AIGaN layer in direct contact with one of the plurality of graded AIGaN layers, a second AIGaN layer in direct contact with the first AIGaN layer, a third AIGaN layer in direct contact with the second AIGaN layer and a fourth AIGaN layer in direct contact with the third AIGaN layer, wherein x is in a range of between greater than 0.8 and less than 1 and y is in a range of between greater than 0.1 and less than 0.3; and P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 5 forming a group I II nitride layer overlying the lattice-matching structure.
The method of claim 14, wherein forming the lattice-matching structure comprises forming the first buffer region by: forming a first layer of AIN onto and in direct contact with the substrate at a first temperature; and forming a second layer of AIN onto and in direct contact with the first layer of AIN at a second temperature greater than the first temperature.
The method of claim 14, wherein the plurality of graded AIGaN layers have distinct aluminum content ranges.
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A semiconductor structure, comprising: a semiconductor substrate; a first buffer region disposed over the semiconductor substrate and comprising a plurality of AIN layers in direct contact with one another and with the semiconductor substrate; a second buffer region arranged over the first buffer region and comprising a plurality of graded AIGaN layers in direct contact with one another and with one of the plurality of AIN layers; a superlattice structure comprising a first AIGaN layer in direct contact with one of the plurality of graded A I[[x]]Ga[[1 x]]N layers, a second AIGaN layer in direct contact with the first AIGaN layer, a third AIGaN layer in direct contact with the second AIGaN layer and a fourth AIGaN layer in direct contact with the third AIGaN layer, wherein x is in a range of between greater than 0.8 and less than 1 and y is in a range of between greater than 0.1 and less than 0.3; and P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 6 a group I II nitride layer overlying the superlattice structure.
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Layer stacks claimed or described, ordered top of device to substrate.
Integrated circuit with lattice-matching structure on silicon (Group III nitride on Si)
Materials described outside the worked examples.
GaN (Group III nitride layer)
GaN
Aluminum nitride (AlN)
AlN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–80 nm | — |
Thickness | 50–200 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,233,844Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a silicon substrate having a first lattice structure; a group I II nitride layer overlying the silicon substrate and having a second lattice structure; a lattice-matching structure arranged between the silicon substrate and the group I II nitride layer, comprising: a first buffer region disposed over the substrate and comprising a first aluminum nitride (AIN) layer in direct contact with a second AIN layer and with the silicon substrate; a second buffer region disposed over the first buffer region and comprising a plurality of graded A IxGa 1.x N layers in direct contact with one another and with the second AIN layer; and a superlattice structure comprising a first AIGaN layer in direct contact with one of the plurality of graded A IxGa 1.x N layers, a second AIGaN layer in direct contact with the first AIGaN layer, a third AIGaN layer in direct contact with the second AIGaN layer and a fourth AIGaN layer in direct contact with the third AIGaN layer, wherein the first AIGaN layer and the third AIGaN layer each have a first aluminum concentration that is greater than a second aluminum contraction of each of the second AIGaN layer and the fourth AIGaN layer.
The integrated circuit of claim 1, wherein the first AIN layer has a thickness from about 20 nm to about 80 nm, and the second AIN layer P₂₀₁₂₀₃₃₅ US00 App. No. 13/534,368 Page 3 has a different thickness of from about 50 to about 200 nm.
The integrated circuit of claim 1, wherein the plurality of graded A IxGa 1.x N layers have aluminum content ranges distinct from one another.
1 0. The integrated circuit of claim 1, wherein the first AIGaN layer and the third AIGaN layer have a smaller thickness than the second AIGaN layer and the fourth AIGaN layer. P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 4
1 2. The integrated circuit of claim 1, wherein the group I II nitride layer comprises a GaN layer.
The integrated circuit of claim 1, wherein the first AIGaN layer and the third AIGaN layer have an aluminum concentration in a range of greater than 0.8 and less than 1 and the second AIGaN layer and the fourth AIGaN layer have an aluminum concentration in a range of greater than 0.1 and less than 0.3.
The integrated circuit of claim 1, further comprising: a source region comprising a metal material and in direct contact with an upper surface of the group I II nitride layer; a drain region comprising the metal material and in direct contact with the upper surface of the group I II nitride layer; and an active layer in direct contact with the upper surface of the group I II nitride layer and with sidewalls of the source region and the drain region.
The integrated circuit of claim 1, wherein the plurality of graded A IxGa 1.x N layers comprise a first graded A IxGa 1.x N layer, a second P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 7 graded AI xGa 1.x N layer, and a third graded AI xGa 1.x N layer, wherein the third graded AIxGa 1.x N layer has a greater thickness than the first graded AI xGa 1.x N layer and the second graded A IxGa 1.x N layer.
The integrated circuit of claim 1, wherein an aluminum content of the first AIGaN layer is a graded aluminum content.
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A method of fabricating a semiconductor structure, comprising: providing a substrate; forming a lattice-matching structure on the substrate, the lattice-matching structure comprising: a first buffer region disposed over the substrate and comprising a plurality of aluminum nitride (AIN) layers in direct contact with one another and with the substrate, a second buffer region disposed over the first buffer region and comprising a plurality of graded AIGaN layers in direct contact with one another and with one of the plurality of AIN layers, and a superlattice structure comprising a first AIGaN layer in direct contact with one of the plurality of graded AIGaN layers, a second AIGaN layer in direct contact with the first AIGaN layer, a third AIGaN layer in direct contact with the second AIGaN layer and a fourth AIGaN layer in direct contact with the third AIGaN layer, wherein x is in a range of between greater than 0.8 and less than 1 and y is in a range of between greater than 0.1 and less than 0.3; and P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 5 forming a group I II nitride layer overlying the lattice-matching structure.
The method of claim 14, wherein forming the lattice-matching structure comprises forming the first buffer region by: forming a first layer of AIN onto and in direct contact with the substrate at a first temperature; and forming a second layer of AIN onto and in direct contact with the first layer of AIN at a second temperature greater than the first temperature.
The method of claim 14, wherein the plurality of graded AIGaN layers have distinct aluminum content ranges.
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A semiconductor structure, comprising: a semiconductor substrate; a first buffer region disposed over the semiconductor substrate and comprising a plurality of AIN layers in direct contact with one another and with the semiconductor substrate; a second buffer region arranged over the first buffer region and comprising a plurality of graded AIGaN layers in direct contact with one another and with one of the plurality of AIN layers; a superlattice structure comprising a first AIGaN layer in direct contact with one of the plurality of graded A I[[x]]Ga[[1 x]]N layers, a second AIGaN layer in direct contact with the first AIGaN layer, a third AIGaN layer in direct contact with the second AIGaN layer and a fourth AIGaN layer in direct contact with the third AIGaN layer, wherein x is in a range of between greater than 0.8 and less than 1 and y is in a range of between greater than 0.1 and less than 0.3; and P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 6 a group I II nitride layer overlying the superlattice structure.
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Layer stacks claimed or described, ordered top of device to substrate.
Integrated circuit with lattice-matching structure on silicon (Group III nitride on Si)
Materials described outside the worked examples.
GaN (Group III nitride layer)
GaN
Aluminum nitride (AlN)
AlN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–80 nm | — |
Thickness | 50–200 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,233,844Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a silicon substrate having a first lattice structure; a group I II nitride layer overlying the silicon substrate and having a second lattice structure; a lattice-matching structure arranged between the silicon substrate and the group I II nitride layer, comprising: a first buffer region disposed over the substrate and comprising a first aluminum nitride (AIN) layer in direct contact with a second AIN layer and with the silicon substrate; a second buffer region disposed over the first buffer region and comprising a plurality of graded A IxGa 1.x N layers in direct contact with one another and with the second AIN layer; and a superlattice structure comprising a first AIGaN layer in direct contact with one of the plurality of graded A IxGa 1.x N layers, a second AIGaN layer in direct contact with the first AIGaN layer, a third AIGaN layer in direct contact with the second AIGaN layer and a fourth AIGaN layer in direct contact with the third AIGaN layer, wherein the first AIGaN layer and the third AIGaN layer each have a first aluminum concentration that is greater than a second aluminum contraction of each of the second AIGaN layer and the fourth AIGaN layer.
The integrated circuit of claim 1, wherein the first AIN layer has a thickness from about 20 nm to about 80 nm, and the second AIN layer P₂₀₁₂₀₃₃₅ US00 App. No. 13/534,368 Page 3 has a different thickness of from about 50 to about 200 nm.
The integrated circuit of claim 1, wherein the plurality of graded A IxGa 1.x N layers have aluminum content ranges distinct from one another.
1 0. The integrated circuit of claim 1, wherein the first AIGaN layer and the third AIGaN layer have a smaller thickness than the second AIGaN layer and the fourth AIGaN layer. P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 4
1 2. The integrated circuit of claim 1, wherein the group I II nitride layer comprises a GaN layer.
The integrated circuit of claim 1, wherein the first AIGaN layer and the third AIGaN layer have an aluminum concentration in a range of greater than 0.8 and less than 1 and the second AIGaN layer and the fourth AIGaN layer have an aluminum concentration in a range of greater than 0.1 and less than 0.3.
The integrated circuit of claim 1, further comprising: a source region comprising a metal material and in direct contact with an upper surface of the group I II nitride layer; a drain region comprising the metal material and in direct contact with the upper surface of the group I II nitride layer; and an active layer in direct contact with the upper surface of the group I II nitride layer and with sidewalls of the source region and the drain region.
The integrated circuit of claim 1, wherein the plurality of graded A IxGa 1.x N layers comprise a first graded A IxGa 1.x N layer, a second P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 7 graded AI xGa 1.x N layer, and a third graded AI xGa 1.x N layer, wherein the third graded AIxGa 1.x N layer has a greater thickness than the first graded AI xGa 1.x N layer and the second graded A IxGa 1.x N layer.
The integrated circuit of claim 1, wherein an aluminum content of the first AIGaN layer is a graded aluminum content.
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A method of fabricating a semiconductor structure, comprising: providing a substrate; forming a lattice-matching structure on the substrate, the lattice-matching structure comprising: a first buffer region disposed over the substrate and comprising a plurality of aluminum nitride (AIN) layers in direct contact with one another and with the substrate, a second buffer region disposed over the first buffer region and comprising a plurality of graded AIGaN layers in direct contact with one another and with one of the plurality of AIN layers, and a superlattice structure comprising a first AIGaN layer in direct contact with one of the plurality of graded AIGaN layers, a second AIGaN layer in direct contact with the first AIGaN layer, a third AIGaN layer in direct contact with the second AIGaN layer and a fourth AIGaN layer in direct contact with the third AIGaN layer, wherein x is in a range of between greater than 0.8 and less than 1 and y is in a range of between greater than 0.1 and less than 0.3; and P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 5 forming a group I II nitride layer overlying the lattice-matching structure.
The method of claim 14, wherein forming the lattice-matching structure comprises forming the first buffer region by: forming a first layer of AIN onto and in direct contact with the substrate at a first temperature; and forming a second layer of AIN onto and in direct contact with the first layer of AIN at a second temperature greater than the first temperature.
The method of claim 14, wherein the plurality of graded AIGaN layers have distinct aluminum content ranges.
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A semiconductor structure, comprising: a semiconductor substrate; a first buffer region disposed over the semiconductor substrate and comprising a plurality of AIN layers in direct contact with one another and with the semiconductor substrate; a second buffer region arranged over the first buffer region and comprising a plurality of graded AIGaN layers in direct contact with one another and with one of the plurality of AIN layers; a superlattice structure comprising a first AIGaN layer in direct contact with one of the plurality of graded A I[[x]]Ga[[1 x]]N layers, a second AIGaN layer in direct contact with the first AIGaN layer, a third AIGaN layer in direct contact with the second AIGaN layer and a fourth AIGaN layer in direct contact with the third AIGaN layer, wherein x is in a range of between greater than 0.8 and less than 1 and y is in a range of between greater than 0.1 and less than 0.3; and P₂₀₁₂₀₃₃₅US00 App. No. 13/534,368 Page 6 a group I II nitride layer overlying the superlattice structure.
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Layer stacks claimed or described, ordered top of device to substrate.
Integrated circuit with lattice-matching structure on silicon (Group III nitride on Si)
Materials described outside the worked examples.
GaN (Group III nitride layer)
GaN
Aluminum nitride (AlN)
AlN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–80 nm | — |
Thickness | 50–200 nm |
Related documents with shared materials, methods, properties, or citations.
Semiconductor structure fabrication method (Group III nitride on substrate)
Semiconductor structure with superlattice and Group III nitride layer
Graded AlxGa₁-xN
AlxGa₁-xN
AlyGa₁-yN (low-Al superlattice layer)
AlyGa₁-yN
Metal (source/drain)
Silicon substrate
Si
| — |
Thickness | 150–250 nm | — |
Thickness | 350–600 nm | — |
Thickness | 4–8 nm | — |
Thickness | 5–40 nm | — |
Thickness | 0.5–1.5 nm | — |
Thickness | 10–40 nm | — |
Pressure | 20–100 pa | — |
Thickness | 15–40 nm | — |
Semiconductor structure fabrication method (Group III nitride on substrate)
Semiconductor structure with superlattice and Group III nitride layer
Graded AlxGa₁-xN
AlxGa₁-xN
AlyGa₁-yN (low-Al superlattice layer)
AlyGa₁-yN
Metal (source/drain)
Silicon substrate
Si
| — |
Thickness | 150–250 nm | — |
Thickness | 350–600 nm | — |
Thickness | 4–8 nm | — |
Thickness | 5–40 nm | — |
Thickness | 0.5–1.5 nm | — |
Thickness | 10–40 nm | — |
Pressure | 20–100 pa | — |
Thickness | 15–40 nm | — |
Semiconductor structure fabrication method (Group III nitride on substrate)
Semiconductor structure with superlattice and Group III nitride layer
Graded AlxGa₁-xN
AlxGa₁-xN
AlyGa₁-yN (low-Al superlattice layer)
AlyGa₁-yN
Metal (source/drain)
Silicon substrate
Si
| — |
Thickness | 150–250 nm | — |
Thickness | 350–600 nm | — |
Thickness | 4–8 nm | — |
Thickness | 5–40 nm | — |
Thickness | 0.5–1.5 nm | — |
Thickness | 10–40 nm | — |
Pressure | 20–100 pa | — |
Thickness | 15–40 nm | — |
Semiconductor structure fabrication method (Group III nitride on substrate)
Semiconductor structure with superlattice and Group III nitride layer
Graded AlxGa₁-xN
AlxGa₁-xN
AlyGa₁-yN (low-Al superlattice layer)
AlyGa₁-yN
Metal (source/drain)
Silicon substrate
Si
| — |
Thickness | 150–250 nm | — |
Thickness | 350–600 nm | — |
Thickness | 4–8 nm | — |
Thickness | 5–40 nm | — |
Thickness | 0.5–1.5 nm | — |
Thickness | 10–40 nm | — |
Pressure | 20–100 pa | — |
Thickness | 15–40 nm | — |