Patent
US 11,258,231GaN-Based VCSEL Chip Based on Porous DBR and Manufacturing Method of the Same
Lixia Zhao
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,258,231Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural view according to an embodiment of the present disclosure; 5 {0034J003 21
FIG. 2 is a flow chart of the manufacturing according to an embodiment of the present disclosure; {003210
FIG. 3 is a picture of a scanning electron microscope of the bottom porous DBR of
FIG. 4 is the reflection spectrum corresponding to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-5. Canceled
Canceled
A method for manufacturing a GaN-based VCSEL chip based on porous DBR, comprising: step 1: growing a buffer layer, alternately stacked lightly doped layers and heavily doped layers, an n-type doped GaN layer, an active layer, an electron blocking layer, and a p-type doped GaN layer on a substrate sequentially, wherein the substrate is made of sapphire, Si or SiC; step 2: performing lateral etching on the alternately stacked lightly doped layers and heavily doped layers by using an electrochemical etching method, so as to transform them to a bottom porous DBR layer in which porous layers and non-porous layers are alternately stacked; step 3: etching down on a periphery of the p-type doped GaN layer by a depth so that a portion of the n-type doped GaN layer is etched, so as to form a mesa on the periphery of the n- type doped GaN layer; step 4: forming a current limiting layer on sidewalls of the p-type doped GaN layer, the mesa, the active layer, and the electron blocking layer; step 5: forming a current window on the current limiting layer, and removing a portion of the current limiting layer on the mesa, using a photolithography and etching technique; step 6: forming a transparent electrode at the current window on the p-type doped GaN layer; step 7: forming an n-electrode and a p-electrode on the mesa on which a portion of the current limiting layer is removed and a periphery of the transparent electrode respectively, wherein a recess is formed in a middle of the p-electrode; and First Named Inventor Lixia Zhao Attorney Docket: 39564- 000 6US₁/FP₁₉ 0 321US step 8: forming a dielectric DBR layer on an upper surface of the transparent electrode in the recess of the p-electrode, so as to complete the manufacturing. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the dielectric DBR layer and the bottom porous DBR layer constitute upper and lower mirrors of the VCSEL chip respectively, and the bottom porous DBR layer has a reflectivity of above 95 % at a peak wavelength of the active layer, which is higher than the reflectivity of the dielectric DBR layer. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the bottom porous DBR layer has a material of a multi-periodic DBR formed by stacking porous nitride layers and non-porous nitride layers alternately. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the current limiting layer is made of Si O 2, SiN X, H fD 2 or A 120 3. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein an n-type GaN layer is further grown between the bottom porous DBR layer and the buffer layer, and is used as a current spreading layer applied for electrochemical etching to form the bottom porous DBR layer. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the lightly doped layers have a doping concentration of 5 x 10 16 cm- 3 and the heavily doped layers have a doping concentration of 1x 10 19 cm 3. New
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based VCSEL chip based on porous DBR
Materials described outside the worked examples.
n-type doped GaN
GaN
bottom porous DBR layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a picture of a scanning electron microscope of the bottom porous DBR of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
bottom porous DBR layer reflectivity at active layer peak wavelength | >95 % | bottom porous DBR layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,258,231Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural view according to an embodiment of the present disclosure; 5 {0034J003 21
FIG. 2 is a flow chart of the manufacturing according to an embodiment of the present disclosure; {003210
FIG. 3 is a picture of a scanning electron microscope of the bottom porous DBR of
FIG. 4 is the reflection spectrum corresponding to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-5. Canceled
Canceled
A method for manufacturing a GaN-based VCSEL chip based on porous DBR, comprising: step 1: growing a buffer layer, alternately stacked lightly doped layers and heavily doped layers, an n-type doped GaN layer, an active layer, an electron blocking layer, and a p-type doped GaN layer on a substrate sequentially, wherein the substrate is made of sapphire, Si or SiC; step 2: performing lateral etching on the alternately stacked lightly doped layers and heavily doped layers by using an electrochemical etching method, so as to transform them to a bottom porous DBR layer in which porous layers and non-porous layers are alternately stacked; step 3: etching down on a periphery of the p-type doped GaN layer by a depth so that a portion of the n-type doped GaN layer is etched, so as to form a mesa on the periphery of the n- type doped GaN layer; step 4: forming a current limiting layer on sidewalls of the p-type doped GaN layer, the mesa, the active layer, and the electron blocking layer; step 5: forming a current window on the current limiting layer, and removing a portion of the current limiting layer on the mesa, using a photolithography and etching technique; step 6: forming a transparent electrode at the current window on the p-type doped GaN layer; step 7: forming an n-electrode and a p-electrode on the mesa on which a portion of the current limiting layer is removed and a periphery of the transparent electrode respectively, wherein a recess is formed in a middle of the p-electrode; and First Named Inventor Lixia Zhao Attorney Docket: 39564- 000 6US₁/FP₁₉ 0 321US step 8: forming a dielectric DBR layer on an upper surface of the transparent electrode in the recess of the p-electrode, so as to complete the manufacturing. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the dielectric DBR layer and the bottom porous DBR layer constitute upper and lower mirrors of the VCSEL chip respectively, and the bottom porous DBR layer has a reflectivity of above 95 % at a peak wavelength of the active layer, which is higher than the reflectivity of the dielectric DBR layer. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the bottom porous DBR layer has a material of a multi-periodic DBR formed by stacking porous nitride layers and non-porous nitride layers alternately. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the current limiting layer is made of Si O 2, SiN X, H fD 2 or A 120 3. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein an n-type GaN layer is further grown between the bottom porous DBR layer and the buffer layer, and is used as a current spreading layer applied for electrochemical etching to form the bottom porous DBR layer. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the lightly doped layers have a doping concentration of 5 x 10 16 cm- 3 and the heavily doped layers have a doping concentration of 1x 10 19 cm 3. New
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based VCSEL chip based on porous DBR
Materials described outside the worked examples.
n-type doped GaN
GaN
bottom porous DBR layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a picture of a scanning electron microscope of the bottom porous DBR of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
bottom porous DBR layer reflectivity at active layer peak wavelength | >95 % | bottom porous DBR layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,258,231Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural view according to an embodiment of the present disclosure; 5 {0034J003 21
FIG. 2 is a flow chart of the manufacturing according to an embodiment of the present disclosure; {003210
FIG. 3 is a picture of a scanning electron microscope of the bottom porous DBR of
FIG. 4 is the reflection spectrum corresponding to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-5. Canceled
Canceled
A method for manufacturing a GaN-based VCSEL chip based on porous DBR, comprising: step 1: growing a buffer layer, alternately stacked lightly doped layers and heavily doped layers, an n-type doped GaN layer, an active layer, an electron blocking layer, and a p-type doped GaN layer on a substrate sequentially, wherein the substrate is made of sapphire, Si or SiC; step 2: performing lateral etching on the alternately stacked lightly doped layers and heavily doped layers by using an electrochemical etching method, so as to transform them to a bottom porous DBR layer in which porous layers and non-porous layers are alternately stacked; step 3: etching down on a periphery of the p-type doped GaN layer by a depth so that a portion of the n-type doped GaN layer is etched, so as to form a mesa on the periphery of the n- type doped GaN layer; step 4: forming a current limiting layer on sidewalls of the p-type doped GaN layer, the mesa, the active layer, and the electron blocking layer; step 5: forming a current window on the current limiting layer, and removing a portion of the current limiting layer on the mesa, using a photolithography and etching technique; step 6: forming a transparent electrode at the current window on the p-type doped GaN layer; step 7: forming an n-electrode and a p-electrode on the mesa on which a portion of the current limiting layer is removed and a periphery of the transparent electrode respectively, wherein a recess is formed in a middle of the p-electrode; and First Named Inventor Lixia Zhao Attorney Docket: 39564- 000 6US₁/FP₁₉ 0 321US step 8: forming a dielectric DBR layer on an upper surface of the transparent electrode in the recess of the p-electrode, so as to complete the manufacturing. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the dielectric DBR layer and the bottom porous DBR layer constitute upper and lower mirrors of the VCSEL chip respectively, and the bottom porous DBR layer has a reflectivity of above 95 % at a peak wavelength of the active layer, which is higher than the reflectivity of the dielectric DBR layer. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the bottom porous DBR layer has a material of a multi-periodic DBR formed by stacking porous nitride layers and non-porous nitride layers alternately. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the current limiting layer is made of Si O 2, SiN X, H fD 2 or A 120 3. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein an n-type GaN layer is further grown between the bottom porous DBR layer and the buffer layer, and is used as a current spreading layer applied for electrochemical etching to form the bottom porous DBR layer. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the lightly doped layers have a doping concentration of 5 x 10 16 cm- 3 and the heavily doped layers have a doping concentration of 1x 10 19 cm 3. New
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based VCSEL chip based on porous DBR
Materials described outside the worked examples.
n-type doped GaN
GaN
bottom porous DBR layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a picture of a scanning electron microscope of the bottom porous DBR of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
bottom porous DBR layer reflectivity at active layer peak wavelength | >95 % | bottom porous DBR layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,258,231Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural view according to an embodiment of the present disclosure; 5 {0034J003 21
FIG. 2 is a flow chart of the manufacturing according to an embodiment of the present disclosure; {003210
FIG. 3 is a picture of a scanning electron microscope of the bottom porous DBR of
FIG. 4 is the reflection spectrum corresponding to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-5. Canceled
Canceled
A method for manufacturing a GaN-based VCSEL chip based on porous DBR, comprising: step 1: growing a buffer layer, alternately stacked lightly doped layers and heavily doped layers, an n-type doped GaN layer, an active layer, an electron blocking layer, and a p-type doped GaN layer on a substrate sequentially, wherein the substrate is made of sapphire, Si or SiC; step 2: performing lateral etching on the alternately stacked lightly doped layers and heavily doped layers by using an electrochemical etching method, so as to transform them to a bottom porous DBR layer in which porous layers and non-porous layers are alternately stacked; step 3: etching down on a periphery of the p-type doped GaN layer by a depth so that a portion of the n-type doped GaN layer is etched, so as to form a mesa on the periphery of the n- type doped GaN layer; step 4: forming a current limiting layer on sidewalls of the p-type doped GaN layer, the mesa, the active layer, and the electron blocking layer; step 5: forming a current window on the current limiting layer, and removing a portion of the current limiting layer on the mesa, using a photolithography and etching technique; step 6: forming a transparent electrode at the current window on the p-type doped GaN layer; step 7: forming an n-electrode and a p-electrode on the mesa on which a portion of the current limiting layer is removed and a periphery of the transparent electrode respectively, wherein a recess is formed in a middle of the p-electrode; and First Named Inventor Lixia Zhao Attorney Docket: 39564- 000 6US₁/FP₁₉ 0 321US step 8: forming a dielectric DBR layer on an upper surface of the transparent electrode in the recess of the p-electrode, so as to complete the manufacturing. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the dielectric DBR layer and the bottom porous DBR layer constitute upper and lower mirrors of the VCSEL chip respectively, and the bottom porous DBR layer has a reflectivity of above 95 % at a peak wavelength of the active layer, which is higher than the reflectivity of the dielectric DBR layer. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the bottom porous DBR layer has a material of a multi-periodic DBR formed by stacking porous nitride layers and non-porous nitride layers alternately. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the current limiting layer is made of Si O 2, SiN X, H fD 2 or A 120 3. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein an n-type GaN layer is further grown between the bottom porous DBR layer and the buffer layer, and is used as a current spreading layer applied for electrochemical etching to form the bottom porous DBR layer. Original
The method for manufacturing the GaN-based VCSEL chip based on porous DBR of claim 6, wherein the lightly doped layers have a doping concentration of 5 x 10 16 cm- 3 and the heavily doped layers have a doping concentration of 1x 10 19 cm 3. New
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based VCSEL chip based on porous DBR
Materials described outside the worked examples.
n-type doped GaN
GaN
bottom porous DBR layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a picture of a scanning electron microscope of the bottom porous DBR of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
bottom porous DBR layer reflectivity at active layer peak wavelength | >95 % | bottom porous DBR layer |
Related documents with shared materials, methods, properties, or citations.
active layer
dielectric DBR layer
silicon dioxide
SiO₂
silicon nitride
SiNx
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
sapphire/Si/SiC substrate
active layer
dielectric DBR layer
silicon dioxide
SiO₂
silicon nitride
SiNx
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
sapphire/Si/SiC substrate
active layer
dielectric DBR layer
silicon dioxide
SiO₂
silicon nitride
SiNx
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
sapphire/Si/SiC substrate
active layer
dielectric DBR layer
silicon dioxide
SiO₂
silicon nitride
SiNx
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
sapphire/Si/SiC substrate