Patent
US 10,741,653BOND-OVER-ACTIVE CIRCUITY GALLIUM NITRIDE DEVICES
Woochul JEON
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,741,653Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 0 A is an implementation of a semiconductor device having a BOA structure; [0049] FIG. lO B-1O C are schematics showing the concentration of electric …
FIG. 2 is a top view of a BOA device; [0035]
FIG. 3A is a schematic of an implementation of a semiconductor device having a drain- source-drain (DSD) pad; [0036]
FIG. 4C is a top view of the high electron mobility transistor (HEMT) cell from the semiconductor device in
FIG. 5B is a cross sectional view of an implementation of a transistor with an enlarged drain contact; [0042]
FIG. 6B is a perspective view of an implementation of a cascode using an implementation of the device illustrated in
FIG. 7A is a top view of an implementation of semiconductor having a multi- source BOA pad; [0045]
FIG. 8A-8C are examples of different implementations semiconductor devices having multi-source BOA pads; [0047]
FIG. 9A-9C are enlarged views of a semiconductor device having a multi- source BOA pad; [0048]
FIG. 10A-10 C, a semiconductor device 140 having a BOA pad structure is illustrated. This device has interdigitated source fingers 142 and drain fingers 144. A …
FIG. 11 B is a schematic of a top view of the device from
FIG. 12B is a top view of another implementation of a semiconductor device having semi- BOA structure; [0055]
FIG. 13A is an implementation of a semiconductor device having a semi-BOA structure; [0056]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a first metal layer comprising an active area and a nonactive area; a second metal layer comprising at least one drain pad, at least one source pad and at least one gate pad; and at least one gate bus; wherein the active area comprises a plurality of source fingers and a plurality of drain fingers interdigitated with one another; wherein the at least one drain pad is coupled to the plurality of drain fingers at one end of the plurality of drain fingers; wherein the at least one drain pad is located only in the non-active area of the first metal layer; and wherein the first metal layer is electrically coupled to the second metal layer.
The semiconductor device of claim 1, wherein the plurality of drain fingers are coupled together at one end.
The semiconductor device of claim 1, further comprising a single contact between the at least one drain pad and the plurality of drain fingers.
The semiconductor device of claim 1, wherein the at least one source pad is located
The semiconductor device of claim 1, further comprising a second source pad and wherein the at least one drain pad is located between the at least one source pad and the second source pad.
The semiconductor device of claim 1, further comprising a second drain pad, wherein the at least one source pad is located between the at least one drain pad and the second drain
A semiconductor device comprising: a first metal layer comprising an active area and a nonactive area; and a second metal layer comprising at least one drain pad, at least one source pad and at least one gate pad; wherein the active area comprises a plurality of source fingers and a plurality of drain fingers interdigitated with one another; wherein the at least one drain pad is coupled to the plurality of drain fingers at one end of the plurality of drain fingers; wherein the at least one drain pad is located only in the non-active area of the first metal layer; and wherein the first metal layer is electrically coupled to the second metal layer.
The semiconductor device of claim 7, wherein the plurality of drain fingers are coupled together at one end.
The semiconductor device of claim 7, further comprising a single contact between the at least one drain pad and the plurality of drain fingers.
The semiconductor device of claim 7, wherein the at least one source pad is located
The semiconductor device of claim 7, further comprising a second source pad and wherein the at least one drain pad is located between the at least one source pad and the second source pad.
The semiconductor device of claim 7, further comprising a second drain pad, wherein the at least one source pad is located between the at least one drain pad and the second drain
A semiconductor device comprising: a first metal layer comprising an active area and a nonactive area; a second metal layer comprising at least one drain pad and at least one source pad; and one of at least one gate bus, at least one gate pad, or at least one gate bus and at least one gate pad; wherein the active area comprises a plurality of source fingers and a plurality of drain fingers interdigitated with one another; wherein the at least one drain pad is coupled to the plurality of drain fingers at one end of the plurality of drain fingers; wherein the at least one drain pad is located only in the non-active area of the first metal layer; and wherein the first metal layer is electrically coupled to the second metal layer.
The semiconductor device of claim 13, wherein together at one end.
The semiconductor device of claim 13, further least one drain pad and the plurality of drain fingers.
The semiconductor device of claim 13, wherein
The semiconductor device of claim 13, further the at least one drain pad is located between the pad.
The semiconductor device of claim 13, further least one source pad is located between the at least the plurality of drain fingers are coupled comprising a single contact between the at the at least one source pad is located comprising a second source pad and wherein at least one source pad and the second source comprising a second drain pad, wherein the at one drain pad and the second drain
Layer stacks claimed or described, ordered top of device to substrate.
Bond-Over-Active GaN HEMT semiconductor device
GaN HEMT cascode device
Materials described outside the worked examples.
Gallium Nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A is a schematic of an implementation of a semiconductor device having a drain- source-drain (DSD) pad; [0036]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
on-resistance (Ron) limit for thin metal process | 100 mOhm | — |
Rdson target for DSD device combining two 120 mOhm devices |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,741,653Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 0 A is an implementation of a semiconductor device having a BOA structure; [0049] FIG. lO B-1O C are schematics showing the concentration of electric …
FIG. 2 is a top view of a BOA device; [0035]
FIG. 3A is a schematic of an implementation of a semiconductor device having a drain- source-drain (DSD) pad; [0036]
FIG. 4C is a top view of the high electron mobility transistor (HEMT) cell from the semiconductor device in
FIG. 5B is a cross sectional view of an implementation of a transistor with an enlarged drain contact; [0042]
FIG. 6B is a perspective view of an implementation of a cascode using an implementation of the device illustrated in
FIG. 7A is a top view of an implementation of semiconductor having a multi- source BOA pad; [0045]
FIG. 8A-8C are examples of different implementations semiconductor devices having multi-source BOA pads; [0047]
FIG. 9A-9C are enlarged views of a semiconductor device having a multi- source BOA pad; [0048]
FIG. 10A-10 C, a semiconductor device 140 having a BOA pad structure is illustrated. This device has interdigitated source fingers 142 and drain fingers 144. A …
FIG. 11 B is a schematic of a top view of the device from
FIG. 12B is a top view of another implementation of a semiconductor device having semi- BOA structure; [0055]
FIG. 13A is an implementation of a semiconductor device having a semi-BOA structure; [0056]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a first metal layer comprising an active area and a nonactive area; a second metal layer comprising at least one drain pad, at least one source pad and at least one gate pad; and at least one gate bus; wherein the active area comprises a plurality of source fingers and a plurality of drain fingers interdigitated with one another; wherein the at least one drain pad is coupled to the plurality of drain fingers at one end of the plurality of drain fingers; wherein the at least one drain pad is located only in the non-active area of the first metal layer; and wherein the first metal layer is electrically coupled to the second metal layer.
The semiconductor device of claim 1, wherein the plurality of drain fingers are coupled together at one end.
The semiconductor device of claim 1, further comprising a single contact between the at least one drain pad and the plurality of drain fingers.
The semiconductor device of claim 1, wherein the at least one source pad is located
The semiconductor device of claim 1, further comprising a second source pad and wherein the at least one drain pad is located between the at least one source pad and the second source pad.
The semiconductor device of claim 1, further comprising a second drain pad, wherein the at least one source pad is located between the at least one drain pad and the second drain
A semiconductor device comprising: a first metal layer comprising an active area and a nonactive area; and a second metal layer comprising at least one drain pad, at least one source pad and at least one gate pad; wherein the active area comprises a plurality of source fingers and a plurality of drain fingers interdigitated with one another; wherein the at least one drain pad is coupled to the plurality of drain fingers at one end of the plurality of drain fingers; wherein the at least one drain pad is located only in the non-active area of the first metal layer; and wherein the first metal layer is electrically coupled to the second metal layer.
The semiconductor device of claim 7, wherein the plurality of drain fingers are coupled together at one end.
The semiconductor device of claim 7, further comprising a single contact between the at least one drain pad and the plurality of drain fingers.
The semiconductor device of claim 7, wherein the at least one source pad is located
The semiconductor device of claim 7, further comprising a second source pad and wherein the at least one drain pad is located between the at least one source pad and the second source pad.
The semiconductor device of claim 7, further comprising a second drain pad, wherein the at least one source pad is located between the at least one drain pad and the second drain
A semiconductor device comprising: a first metal layer comprising an active area and a nonactive area; a second metal layer comprising at least one drain pad and at least one source pad; and one of at least one gate bus, at least one gate pad, or at least one gate bus and at least one gate pad; wherein the active area comprises a plurality of source fingers and a plurality of drain fingers interdigitated with one another; wherein the at least one drain pad is coupled to the plurality of drain fingers at one end of the plurality of drain fingers; wherein the at least one drain pad is located only in the non-active area of the first metal layer; and wherein the first metal layer is electrically coupled to the second metal layer.
The semiconductor device of claim 13, wherein together at one end.
The semiconductor device of claim 13, further least one drain pad and the plurality of drain fingers.
The semiconductor device of claim 13, wherein
The semiconductor device of claim 13, further the at least one drain pad is located between the pad.
The semiconductor device of claim 13, further least one source pad is located between the at least the plurality of drain fingers are coupled comprising a single contact between the at the at least one source pad is located comprising a second source pad and wherein at least one source pad and the second source comprising a second drain pad, wherein the at one drain pad and the second drain
Layer stacks claimed or described, ordered top of device to substrate.
Bond-Over-Active GaN HEMT semiconductor device
GaN HEMT cascode device
Materials described outside the worked examples.
Gallium Nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A is a schematic of an implementation of a semiconductor device having a drain- source-drain (DSD) pad; [0036]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
on-resistance (Ron) limit for thin metal process | 100 mOhm | — |
Rdson target for DSD device combining two 120 mOhm devices |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,741,653Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 0 A is an implementation of a semiconductor device having a BOA structure; [0049] FIG. lO B-1O C are schematics showing the concentration of electric …
FIG. 2 is a top view of a BOA device; [0035]
FIG. 3A is a schematic of an implementation of a semiconductor device having a drain- source-drain (DSD) pad; [0036]
FIG. 4C is a top view of the high electron mobility transistor (HEMT) cell from the semiconductor device in
FIG. 5B is a cross sectional view of an implementation of a transistor with an enlarged drain contact; [0042]
FIG. 6B is a perspective view of an implementation of a cascode using an implementation of the device illustrated in
FIG. 7A is a top view of an implementation of semiconductor having a multi- source BOA pad; [0045]
FIG. 8A-8C are examples of different implementations semiconductor devices having multi-source BOA pads; [0047]
FIG. 9A-9C are enlarged views of a semiconductor device having a multi- source BOA pad; [0048]
FIG. 10A-10 C, a semiconductor device 140 having a BOA pad structure is illustrated. This device has interdigitated source fingers 142 and drain fingers 144. A …
FIG. 11 B is a schematic of a top view of the device from
FIG. 12B is a top view of another implementation of a semiconductor device having semi- BOA structure; [0055]
FIG. 13A is an implementation of a semiconductor device having a semi-BOA structure; [0056]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a first metal layer comprising an active area and a nonactive area; a second metal layer comprising at least one drain pad, at least one source pad and at least one gate pad; and at least one gate bus; wherein the active area comprises a plurality of source fingers and a plurality of drain fingers interdigitated with one another; wherein the at least one drain pad is coupled to the plurality of drain fingers at one end of the plurality of drain fingers; wherein the at least one drain pad is located only in the non-active area of the first metal layer; and wherein the first metal layer is electrically coupled to the second metal layer.
The semiconductor device of claim 1, wherein the plurality of drain fingers are coupled together at one end.
The semiconductor device of claim 1, further comprising a single contact between the at least one drain pad and the plurality of drain fingers.
The semiconductor device of claim 1, wherein the at least one source pad is located
The semiconductor device of claim 1, further comprising a second source pad and wherein the at least one drain pad is located between the at least one source pad and the second source pad.
The semiconductor device of claim 1, further comprising a second drain pad, wherein the at least one source pad is located between the at least one drain pad and the second drain
A semiconductor device comprising: a first metal layer comprising an active area and a nonactive area; and a second metal layer comprising at least one drain pad, at least one source pad and at least one gate pad; wherein the active area comprises a plurality of source fingers and a plurality of drain fingers interdigitated with one another; wherein the at least one drain pad is coupled to the plurality of drain fingers at one end of the plurality of drain fingers; wherein the at least one drain pad is located only in the non-active area of the first metal layer; and wherein the first metal layer is electrically coupled to the second metal layer.
The semiconductor device of claim 7, wherein the plurality of drain fingers are coupled together at one end.
The semiconductor device of claim 7, further comprising a single contact between the at least one drain pad and the plurality of drain fingers.
The semiconductor device of claim 7, wherein the at least one source pad is located
The semiconductor device of claim 7, further comprising a second source pad and wherein the at least one drain pad is located between the at least one source pad and the second source pad.
The semiconductor device of claim 7, further comprising a second drain pad, wherein the at least one source pad is located between the at least one drain pad and the second drain
A semiconductor device comprising: a first metal layer comprising an active area and a nonactive area; a second metal layer comprising at least one drain pad and at least one source pad; and one of at least one gate bus, at least one gate pad, or at least one gate bus and at least one gate pad; wherein the active area comprises a plurality of source fingers and a plurality of drain fingers interdigitated with one another; wherein the at least one drain pad is coupled to the plurality of drain fingers at one end of the plurality of drain fingers; wherein the at least one drain pad is located only in the non-active area of the first metal layer; and wherein the first metal layer is electrically coupled to the second metal layer.
The semiconductor device of claim 13, wherein together at one end.
The semiconductor device of claim 13, further least one drain pad and the plurality of drain fingers.
The semiconductor device of claim 13, wherein
The semiconductor device of claim 13, further the at least one drain pad is located between the pad.
The semiconductor device of claim 13, further least one source pad is located between the at least the plurality of drain fingers are coupled comprising a single contact between the at the at least one source pad is located comprising a second source pad and wherein at least one source pad and the second source comprising a second drain pad, wherein the at one drain pad and the second drain
Layer stacks claimed or described, ordered top of device to substrate.
Bond-Over-Active GaN HEMT semiconductor device
GaN HEMT cascode device
Materials described outside the worked examples.
Gallium Nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A is a schematic of an implementation of a semiconductor device having a drain- source-drain (DSD) pad; [0036]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
on-resistance (Ron) limit for thin metal process | 100 mOhm | — |
Rdson target for DSD device combining two 120 mOhm devices |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,741,653Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 0 A is an implementation of a semiconductor device having a BOA structure; [0049] FIG. lO B-1O C are schematics showing the concentration of electric …
FIG. 2 is a top view of a BOA device; [0035]
FIG. 3A is a schematic of an implementation of a semiconductor device having a drain- source-drain (DSD) pad; [0036]
FIG. 4C is a top view of the high electron mobility transistor (HEMT) cell from the semiconductor device in
FIG. 5B is a cross sectional view of an implementation of a transistor with an enlarged drain contact; [0042]
FIG. 6B is a perspective view of an implementation of a cascode using an implementation of the device illustrated in
FIG. 7A is a top view of an implementation of semiconductor having a multi- source BOA pad; [0045]
FIG. 8A-8C are examples of different implementations semiconductor devices having multi-source BOA pads; [0047]
FIG. 9A-9C are enlarged views of a semiconductor device having a multi- source BOA pad; [0048]
FIG. 10A-10 C, a semiconductor device 140 having a BOA pad structure is illustrated. This device has interdigitated source fingers 142 and drain fingers 144. A …
FIG. 11 B is a schematic of a top view of the device from
FIG. 12B is a top view of another implementation of a semiconductor device having semi- BOA structure; [0055]
FIG. 13A is an implementation of a semiconductor device having a semi-BOA structure; [0056]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a first metal layer comprising an active area and a nonactive area; a second metal layer comprising at least one drain pad, at least one source pad and at least one gate pad; and at least one gate bus; wherein the active area comprises a plurality of source fingers and a plurality of drain fingers interdigitated with one another; wherein the at least one drain pad is coupled to the plurality of drain fingers at one end of the plurality of drain fingers; wherein the at least one drain pad is located only in the non-active area of the first metal layer; and wherein the first metal layer is electrically coupled to the second metal layer.
The semiconductor device of claim 1, wherein the plurality of drain fingers are coupled together at one end.
The semiconductor device of claim 1, further comprising a single contact between the at least one drain pad and the plurality of drain fingers.
The semiconductor device of claim 1, wherein the at least one source pad is located
The semiconductor device of claim 1, further comprising a second source pad and wherein the at least one drain pad is located between the at least one source pad and the second source pad.
The semiconductor device of claim 1, further comprising a second drain pad, wherein the at least one source pad is located between the at least one drain pad and the second drain
A semiconductor device comprising: a first metal layer comprising an active area and a nonactive area; and a second metal layer comprising at least one drain pad, at least one source pad and at least one gate pad; wherein the active area comprises a plurality of source fingers and a plurality of drain fingers interdigitated with one another; wherein the at least one drain pad is coupled to the plurality of drain fingers at one end of the plurality of drain fingers; wherein the at least one drain pad is located only in the non-active area of the first metal layer; and wherein the first metal layer is electrically coupled to the second metal layer.
The semiconductor device of claim 7, wherein the plurality of drain fingers are coupled together at one end.
The semiconductor device of claim 7, further comprising a single contact between the at least one drain pad and the plurality of drain fingers.
The semiconductor device of claim 7, wherein the at least one source pad is located
The semiconductor device of claim 7, further comprising a second source pad and wherein the at least one drain pad is located between the at least one source pad and the second source pad.
The semiconductor device of claim 7, further comprising a second drain pad, wherein the at least one source pad is located between the at least one drain pad and the second drain
A semiconductor device comprising: a first metal layer comprising an active area and a nonactive area; a second metal layer comprising at least one drain pad and at least one source pad; and one of at least one gate bus, at least one gate pad, or at least one gate bus and at least one gate pad; wherein the active area comprises a plurality of source fingers and a plurality of drain fingers interdigitated with one another; wherein the at least one drain pad is coupled to the plurality of drain fingers at one end of the plurality of drain fingers; wherein the at least one drain pad is located only in the non-active area of the first metal layer; and wherein the first metal layer is electrically coupled to the second metal layer.
The semiconductor device of claim 13, wherein together at one end.
The semiconductor device of claim 13, further least one drain pad and the plurality of drain fingers.
The semiconductor device of claim 13, wherein
The semiconductor device of claim 13, further the at least one drain pad is located between the pad.
The semiconductor device of claim 13, further least one source pad is located between the at least the plurality of drain fingers are coupled comprising a single contact between the at the at least one source pad is located comprising a second source pad and wherein at least one source pad and the second source comprising a second drain pad, wherein the at one drain pad and the second drain
Layer stacks claimed or described, ordered top of device to substrate.
Bond-Over-Active GaN HEMT semiconductor device
GaN HEMT cascode device
Materials described outside the worked examples.
Gallium Nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A is a schematic of an implementation of a semiconductor device having a drain- source-drain (DSD) pad; [0036]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
on-resistance (Ron) limit for thin metal process | 100 mOhm | — |
Rdson target for DSD device combining two 120 mOhm devices |
Related documents with shared materials, methods, properties, or citations.
Drain-Source-Drain (DSD) pad structure GaN HEMT
FIG. 4C is a top view of the high electron mobility transistor (HEMT) cell from the semiconductor device in
FIG. 5B is a cross sectional view of an implementation of a transistor with an enlarged drain contact; [0042]
| 60 mOhm |
| — |
Thickness | 4–12 µm | — |
Drain-Source-Drain (DSD) pad structure GaN HEMT
FIG. 4C is a top view of the high electron mobility transistor (HEMT) cell from the semiconductor device in
FIG. 5B is a cross sectional view of an implementation of a transistor with an enlarged drain contact; [0042]
| 60 mOhm |
| — |
Thickness | 4–12 µm | — |
Drain-Source-Drain (DSD) pad structure GaN HEMT
FIG. 4C is a top view of the high electron mobility transistor (HEMT) cell from the semiconductor device in
FIG. 5B is a cross sectional view of an implementation of a transistor with an enlarged drain contact; [0042]
| 60 mOhm |
| — |
Thickness | 4–12 µm | — |
Drain-Source-Drain (DSD) pad structure GaN HEMT
FIG. 4C is a top view of the high electron mobility transistor (HEMT) cell from the semiconductor device in
FIG. 5B is a cross sectional view of an implementation of a transistor with an enlarged drain contact; [0042]
| 60 mOhm |
| — |
Thickness | 4–12 µm | — |