Copyright © 2026 Matter42. All rights reserved.

; both applications are incorporated herein by reference in their entirety. 10 [0002] This | Matter42 Literature

Patent

Atlas literature

Patent

US 9,824,949

; both applications are incorporated herein by reference in their entirety. 10 [0002] This

Cameron MCKNIGHT-MACNEIL

US

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 2

FIG. 3

FIG. 4

FIG. 5

FIG. 6

FIG. 7

FIG. 8

FIG. 9

FIG. 10

FIG. 11

FIG. 12

FIG. 13

FIG. 14

FIG. 15

FIG. 16

FIG. 17

FIG. 18

FIG. 19

FIG. 20

FIG. 21

FIG. 22

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

2 independent · 19 dependent

1
IndependentGaNcopper or copper alloyelectrically and thermally conductive attachment materiallateral GaN power transistor dual leadframe package
A semiconductor device structure comprising an assembly of: a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising a ﬁrst leadframe layer and a second leadframe layer; 5 the GaN die comprising a front surface providing source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach; the GaN die being sandwiched between the ﬁrst and second leadframe layers; the ﬁrst leadframe layer being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die; 10 the second leadframe layer comprising a thermal pad and a die-attach area for the back surface of the GaN die; the back surface of the GaN die being attached to the die-attach area of the second leadframe layer by a low inductance layer of an electrically and thermally conductive attachment material; 15 the source, drain and gate contact areas of the GaN die being attached and electrically connected to respective source, drain and gate portions of the ﬁrst leadframe layer by low inductance interconnections; a package body comprising an over-molding of encapsulation which leaves exposed the thermal pad of the second leadframe layer and leaves exposed external contact pads for the 20 source, drain and gate of the lateral GaN transistor; and wherein said external contact pads for the source, drain and gate contacts are parts of the ﬁrst leadframe layer and are provided on a front-side of the package body and the thermal pad is provided on a back-side of the package body.
1. 2
  Dependent← claim 1lateral GaN power transistor dual leadframe package
  The device structure of claim 1, wherein one of the ﬁrst and second leadframe layers further comprises a source clip portion, laterally spaced from the die substrate, which vertically interconnects the second leadframe layer and the source portion of the ﬁrst leadframe layer, thereby providing a substrate source connection for grounding the die substrate to the source. 29
15
IndependentGaNcopper or copper alloyelectrically and thermally conductive attachment materiallateral GaN power transistor dual leadframe package
A method of fabricating a semiconductor device structure comprising an assembly of: a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising ﬁrst and second leadframe layers for encapsulation within 10 a package body, the method comprising: providing the GaN die comprising a front surface comprising source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach; providing a ﬁrst leadframe layer and a second leadframe layer; the ﬁrst leadframe layer being patterned to provide source, drain and gate portions, the source 15 portion comprising an external source pad and a plurality of source ﬁngers extending laterally from the source pad, the drain portion comprising an external drain pad and a plurality of drain ﬁngers extending laterally from the drain pad, to provide source, drain and gate contact areas of the source, gate and drain portions corresponding to the source, drain and gate contact areas on the front surface of the GaN die; 20 the second leadframe layer providing a thermal pad and die-attach area for the back surface of the GaN die, at least one of the ﬁrst and second leadframe layers comprising a source clip portion which extends laterally of the die attach area of the second leadframe layer for vertical interconnection with the source portion of the ﬁrst leadframe layer; 25 attaching the back surface of the GaN die to the die-attach area of the second leadframe layer with a layer electrically and thermally conductive material; providing low inductance metal bump or metal post connections for source, drain and gate contact areas of the GaN die, and providing a layer of electrically and thermally conductive attachment material for any other surfaces to be electrically interconnected; 32 mutually positioning the ﬁrst and second leadframes to align respective source, drain and gate contacts thereof, with at least one of bump connections, post connections and attachment material therebetween; processing the respective bump connections, post connections and the attachment material to 5 vertically attach, and thermally and electrically interconnect the source, drain and gate contact areas of the GaN die and respective source, drain and gate portions of the ﬁrst copper leadframe layer; and providing a package body comprising an over-molding of encapsulation, exposing the thermal pad of second copper leadframe layer and exposing the external contact pads for the source, 10 drain and gate of the lateral GaN transistor.
1. 16
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, comprising interconnecting the source, drain and gate contact areas on the front side of the GaN die with the respective source, drain and gate portions of the ﬁrst leadframe layer, and subsequently attaching the backside of the GaN die to the die attach 15 area of the thermal pad of second leadframe layer.
2. 17
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, comprising attaching the backside of GaN die to the die attach area of the thermal pad of the second leadframe layer prior to aligning and interconnecting the respective source, drain and gate portions of the ﬁrst leadframe layer with 20 the source, drain and gate contact areas of the GaN die.
3. 18
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein, the ﬁrst lead frame layer is patterned to provide source, drain and gate portions comprising areas for the external source, drain and gate pads; the source portion further comprises tapered source ﬁngers extending laterally from the source 25 pad; the drain portion further comprises tapered drain ﬁngers extending laterally from the drain pad; and the source portions and drain portions being half-etched so that the source ﬁngers and drain ﬁngers are thinner than the source pad and the drain pad. 33
4. 19
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein, the ﬁrst lead frame layer is patterned to provide source, drain and gate portions comprising areas for the external source, drain and gate pads; the source portion further comprises tapered source ﬁngers extending laterally from the source pad; the drain portion further comprises tapered drain ﬁngers extending laterally from the 5 drain pad; and wherein the source ﬁngers and the source pad and the drain ﬁngers and the drain pad have the same thickness, so that after providing an over-molding of encapsulation, the source portion comprising the source pad and the source ﬁngers and the drain portion comprising the drain pad and the drain ﬁngers are exposed on the back surface of the package body, and further comprising: 10 half etching the exposed source ﬁngers and drain ﬁngers to thin the source ﬁngers and drain ﬁngers to a thickness less than that of the source pad and drain pad and then providing a second encapsulation to embed the source ﬁngers and the drain ﬁngers within the package body, leaving the source, drain and gate pads exposed on the back side of the package body.
5. 20
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein the ﬁrst leadframe layer comprises a supporting frame surrounding said source, drain, gate or thermal pad portions and further comprising: removing said supporting frame during device singulation.
6. 21
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein said ﬁrst and second leadframe layers are provided 20 with registration means comprising tabs of one of the leadframe layers for inter-engagement with slots of the other leadframe layer, and further comprising: inter-engaging said tabs and slots for mutual registration, vertically and horizontally, of the ﬁrst and second leadframe layers.

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

lateral GaN power transistor dual leadframe package

copper or copper alloyfront leadframe source drain gate portions

copper or copper alloylow inductance interconnections

GaNGaN die substrate

electrically and thermally conductive attachment materialdie attach

copper or copper alloyback leadframe thermal pad

Materials

Materials described outside the worked examples.

GaN (gallium nitride)

GaN

Transistor Active Material

copper or copper alloy

Leadframe Material

electrically and thermally conductive attachment material

Why these are connected

Related documents with shared materials, methods, properties, or citations.

Patent

Atlas literature

Patent

US 9,824,949

; both applications are incorporated herein by reference in their entirety. 10 [0002] This

Cameron MCKNIGHT-MACNEIL

US

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 2

FIG. 3

FIG. 4

FIG. 5

FIG. 6

FIG. 7

FIG. 8

FIG. 9

FIG. 10

FIG. 11

FIG. 12

FIG. 13

FIG. 14

FIG. 15

FIG. 16

FIG. 17

FIG. 18

FIG. 19

FIG. 20

FIG. 21

FIG. 22

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

2 independent · 19 dependent

1
IndependentGaNcopper or copper alloyelectrically and thermally conductive attachment materiallateral GaN power transistor dual leadframe package
A semiconductor device structure comprising an assembly of: a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising a ﬁrst leadframe layer and a second leadframe layer; 5 the GaN die comprising a front surface providing source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach; the GaN die being sandwiched between the ﬁrst and second leadframe layers; the ﬁrst leadframe layer being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die; 10 the second leadframe layer comprising a thermal pad and a die-attach area for the back surface of the GaN die; the back surface of the GaN die being attached to the die-attach area of the second leadframe layer by a low inductance layer of an electrically and thermally conductive attachment material; 15 the source, drain and gate contact areas of the GaN die being attached and electrically connected to respective source, drain and gate portions of the ﬁrst leadframe layer by low inductance interconnections; a package body comprising an over-molding of encapsulation which leaves exposed the thermal pad of the second leadframe layer and leaves exposed external contact pads for the 20 source, drain and gate of the lateral GaN transistor; and wherein said external contact pads for the source, drain and gate contacts are parts of the ﬁrst leadframe layer and are provided on a front-side of the package body and the thermal pad is provided on a back-side of the package body.
1. 2
  Dependent← claim 1lateral GaN power transistor dual leadframe package
  The device structure of claim 1, wherein one of the ﬁrst and second leadframe layers further comprises a source clip portion, laterally spaced from the die substrate, which vertically interconnects the second leadframe layer and the source portion of the ﬁrst leadframe layer, thereby providing a substrate source connection for grounding the die substrate to the source. 29
15
IndependentGaNcopper or copper alloyelectrically and thermally conductive attachment materiallateral GaN power transistor dual leadframe package
A method of fabricating a semiconductor device structure comprising an assembly of: a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising ﬁrst and second leadframe layers for encapsulation within 10 a package body, the method comprising: providing the GaN die comprising a front surface comprising source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach; providing a ﬁrst leadframe layer and a second leadframe layer; the ﬁrst leadframe layer being patterned to provide source, drain and gate portions, the source 15 portion comprising an external source pad and a plurality of source ﬁngers extending laterally from the source pad, the drain portion comprising an external drain pad and a plurality of drain ﬁngers extending laterally from the drain pad, to provide source, drain and gate contact areas of the source, gate and drain portions corresponding to the source, drain and gate contact areas on the front surface of the GaN die; 20 the second leadframe layer providing a thermal pad and die-attach area for the back surface of the GaN die, at least one of the ﬁrst and second leadframe layers comprising a source clip portion which extends laterally of the die attach area of the second leadframe layer for vertical interconnection with the source portion of the ﬁrst leadframe layer; 25 attaching the back surface of the GaN die to the die-attach area of the second leadframe layer with a layer electrically and thermally conductive material; providing low inductance metal bump or metal post connections for source, drain and gate contact areas of the GaN die, and providing a layer of electrically and thermally conductive attachment material for any other surfaces to be electrically interconnected; 32 mutually positioning the ﬁrst and second leadframes to align respective source, drain and gate contacts thereof, with at least one of bump connections, post connections and attachment material therebetween; processing the respective bump connections, post connections and the attachment material to 5 vertically attach, and thermally and electrically interconnect the source, drain and gate contact areas of the GaN die and respective source, drain and gate portions of the ﬁrst copper leadframe layer; and providing a package body comprising an over-molding of encapsulation, exposing the thermal pad of second copper leadframe layer and exposing the external contact pads for the source, 10 drain and gate of the lateral GaN transistor.
1. 16
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, comprising interconnecting the source, drain and gate contact areas on the front side of the GaN die with the respective source, drain and gate portions of the ﬁrst leadframe layer, and subsequently attaching the backside of the GaN die to the die attach 15 area of the thermal pad of second leadframe layer.
2. 17
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, comprising attaching the backside of GaN die to the die attach area of the thermal pad of the second leadframe layer prior to aligning and interconnecting the respective source, drain and gate portions of the ﬁrst leadframe layer with 20 the source, drain and gate contact areas of the GaN die.
3. 18
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein, the ﬁrst lead frame layer is patterned to provide source, drain and gate portions comprising areas for the external source, drain and gate pads; the source portion further comprises tapered source ﬁngers extending laterally from the source 25 pad; the drain portion further comprises tapered drain ﬁngers extending laterally from the drain pad; and the source portions and drain portions being half-etched so that the source ﬁngers and drain ﬁngers are thinner than the source pad and the drain pad. 33
4. 19
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein, the ﬁrst lead frame layer is patterned to provide source, drain and gate portions comprising areas for the external source, drain and gate pads; the source portion further comprises tapered source ﬁngers extending laterally from the source pad; the drain portion further comprises tapered drain ﬁngers extending laterally from the 5 drain pad; and wherein the source ﬁngers and the source pad and the drain ﬁngers and the drain pad have the same thickness, so that after providing an over-molding of encapsulation, the source portion comprising the source pad and the source ﬁngers and the drain portion comprising the drain pad and the drain ﬁngers are exposed on the back surface of the package body, and further comprising: 10 half etching the exposed source ﬁngers and drain ﬁngers to thin the source ﬁngers and drain ﬁngers to a thickness less than that of the source pad and drain pad and then providing a second encapsulation to embed the source ﬁngers and the drain ﬁngers within the package body, leaving the source, drain and gate pads exposed on the back side of the package body.
5. 20
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein the ﬁrst leadframe layer comprises a supporting frame surrounding said source, drain, gate or thermal pad portions and further comprising: removing said supporting frame during device singulation.
6. 21
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein said ﬁrst and second leadframe layers are provided 20 with registration means comprising tabs of one of the leadframe layers for inter-engagement with slots of the other leadframe layer, and further comprising: inter-engaging said tabs and slots for mutual registration, vertically and horizontally, of the ﬁrst and second leadframe layers.

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

lateral GaN power transistor dual leadframe package

copper or copper alloyfront leadframe source drain gate portions

copper or copper alloylow inductance interconnections

GaNGaN die substrate

electrically and thermally conductive attachment materialdie attach

copper or copper alloyback leadframe thermal pad

Materials

Materials described outside the worked examples.

GaN (gallium nitride)

GaN

Transistor Active Material

copper or copper alloy

Leadframe Material

electrically and thermally conductive attachment material

Why these are connected

Related documents with shared materials, methods, properties, or citations.

Patent

Atlas literature

Patent

US 9,824,949

; both applications are incorporated herein by reference in their entirety. 10 [0002] This

Cameron MCKNIGHT-MACNEIL

US

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 2

FIG. 3

FIG. 4

FIG. 5

FIG. 6

FIG. 7

FIG. 8

FIG. 9

FIG. 10

FIG. 11

FIG. 12

FIG. 13

FIG. 14

FIG. 15

FIG. 16

FIG. 17

FIG. 18

FIG. 19

FIG. 20

FIG. 21

FIG. 22

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

2 independent · 19 dependent

1
IndependentGaNcopper or copper alloyelectrically and thermally conductive attachment materiallateral GaN power transistor dual leadframe package
A semiconductor device structure comprising an assembly of: a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising a ﬁrst leadframe layer and a second leadframe layer; 5 the GaN die comprising a front surface providing source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach; the GaN die being sandwiched between the ﬁrst and second leadframe layers; the ﬁrst leadframe layer being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die; 10 the second leadframe layer comprising a thermal pad and a die-attach area for the back surface of the GaN die; the back surface of the GaN die being attached to the die-attach area of the second leadframe layer by a low inductance layer of an electrically and thermally conductive attachment material; 15 the source, drain and gate contact areas of the GaN die being attached and electrically connected to respective source, drain and gate portions of the ﬁrst leadframe layer by low inductance interconnections; a package body comprising an over-molding of encapsulation which leaves exposed the thermal pad of the second leadframe layer and leaves exposed external contact pads for the 20 source, drain and gate of the lateral GaN transistor; and wherein said external contact pads for the source, drain and gate contacts are parts of the ﬁrst leadframe layer and are provided on a front-side of the package body and the thermal pad is provided on a back-side of the package body.
1. 2
  Dependent← claim 1lateral GaN power transistor dual leadframe package
  The device structure of claim 1, wherein one of the ﬁrst and second leadframe layers further comprises a source clip portion, laterally spaced from the die substrate, which vertically interconnects the second leadframe layer and the source portion of the ﬁrst leadframe layer, thereby providing a substrate source connection for grounding the die substrate to the source. 29
15
IndependentGaNcopper or copper alloyelectrically and thermally conductive attachment materiallateral GaN power transistor dual leadframe package
A method of fabricating a semiconductor device structure comprising an assembly of: a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising ﬁrst and second leadframe layers for encapsulation within 10 a package body, the method comprising: providing the GaN die comprising a front surface comprising source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach; providing a ﬁrst leadframe layer and a second leadframe layer; the ﬁrst leadframe layer being patterned to provide source, drain and gate portions, the source 15 portion comprising an external source pad and a plurality of source ﬁngers extending laterally from the source pad, the drain portion comprising an external drain pad and a plurality of drain ﬁngers extending laterally from the drain pad, to provide source, drain and gate contact areas of the source, gate and drain portions corresponding to the source, drain and gate contact areas on the front surface of the GaN die; 20 the second leadframe layer providing a thermal pad and die-attach area for the back surface of the GaN die, at least one of the ﬁrst and second leadframe layers comprising a source clip portion which extends laterally of the die attach area of the second leadframe layer for vertical interconnection with the source portion of the ﬁrst leadframe layer; 25 attaching the back surface of the GaN die to the die-attach area of the second leadframe layer with a layer electrically and thermally conductive material; providing low inductance metal bump or metal post connections for source, drain and gate contact areas of the GaN die, and providing a layer of electrically and thermally conductive attachment material for any other surfaces to be electrically interconnected; 32 mutually positioning the ﬁrst and second leadframes to align respective source, drain and gate contacts thereof, with at least one of bump connections, post connections and attachment material therebetween; processing the respective bump connections, post connections and the attachment material to 5 vertically attach, and thermally and electrically interconnect the source, drain and gate contact areas of the GaN die and respective source, drain and gate portions of the ﬁrst copper leadframe layer; and providing a package body comprising an over-molding of encapsulation, exposing the thermal pad of second copper leadframe layer and exposing the external contact pads for the source, 10 drain and gate of the lateral GaN transistor.
1. 16
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, comprising interconnecting the source, drain and gate contact areas on the front side of the GaN die with the respective source, drain and gate portions of the ﬁrst leadframe layer, and subsequently attaching the backside of the GaN die to the die attach 15 area of the thermal pad of second leadframe layer.
2. 17
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, comprising attaching the backside of GaN die to the die attach area of the thermal pad of the second leadframe layer prior to aligning and interconnecting the respective source, drain and gate portions of the ﬁrst leadframe layer with 20 the source, drain and gate contact areas of the GaN die.
3. 18
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein, the ﬁrst lead frame layer is patterned to provide source, drain and gate portions comprising areas for the external source, drain and gate pads; the source portion further comprises tapered source ﬁngers extending laterally from the source 25 pad; the drain portion further comprises tapered drain ﬁngers extending laterally from the drain pad; and the source portions and drain portions being half-etched so that the source ﬁngers and drain ﬁngers are thinner than the source pad and the drain pad. 33
4. 19
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein, the ﬁrst lead frame layer is patterned to provide source, drain and gate portions comprising areas for the external source, drain and gate pads; the source portion further comprises tapered source ﬁngers extending laterally from the source pad; the drain portion further comprises tapered drain ﬁngers extending laterally from the 5 drain pad; and wherein the source ﬁngers and the source pad and the drain ﬁngers and the drain pad have the same thickness, so that after providing an over-molding of encapsulation, the source portion comprising the source pad and the source ﬁngers and the drain portion comprising the drain pad and the drain ﬁngers are exposed on the back surface of the package body, and further comprising: 10 half etching the exposed source ﬁngers and drain ﬁngers to thin the source ﬁngers and drain ﬁngers to a thickness less than that of the source pad and drain pad and then providing a second encapsulation to embed the source ﬁngers and the drain ﬁngers within the package body, leaving the source, drain and gate pads exposed on the back side of the package body.
5. 20
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein the ﬁrst leadframe layer comprises a supporting frame surrounding said source, drain, gate or thermal pad portions and further comprising: removing said supporting frame during device singulation.
6. 21
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein said ﬁrst and second leadframe layers are provided 20 with registration means comprising tabs of one of the leadframe layers for inter-engagement with slots of the other leadframe layer, and further comprising: inter-engaging said tabs and slots for mutual registration, vertically and horizontally, of the ﬁrst and second leadframe layers.

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

lateral GaN power transistor dual leadframe package

copper or copper alloyfront leadframe source drain gate portions

copper or copper alloylow inductance interconnections

GaNGaN die substrate

electrically and thermally conductive attachment materialdie attach

copper or copper alloyback leadframe thermal pad

Materials

Materials described outside the worked examples.

GaN (gallium nitride)

GaN

Transistor Active Material

copper or copper alloy

Leadframe Material

electrically and thermally conductive attachment material

Why these are connected

Related documents with shared materials, methods, properties, or citations.

Patent

Atlas literature

Patent

US 9,824,949

; both applications are incorporated herein by reference in their entirety. 10 [0002] This

Cameron MCKNIGHT-MACNEIL

US

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 2

FIG. 3

FIG. 4

FIG. 5

FIG. 6

FIG. 7

FIG. 8

FIG. 9

FIG. 10

FIG. 11

FIG. 12

FIG. 13

FIG. 14

FIG. 15

FIG. 16

FIG. 17

FIG. 18

FIG. 19

FIG. 20

FIG. 21

FIG. 22

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

2 independent · 19 dependent

1
IndependentGaNcopper or copper alloyelectrically and thermally conductive attachment materiallateral GaN power transistor dual leadframe package
A semiconductor device structure comprising an assembly of: a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising a ﬁrst leadframe layer and a second leadframe layer; 5 the GaN die comprising a front surface providing source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach; the GaN die being sandwiched between the ﬁrst and second leadframe layers; the ﬁrst leadframe layer being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die; 10 the second leadframe layer comprising a thermal pad and a die-attach area for the back surface of the GaN die; the back surface of the GaN die being attached to the die-attach area of the second leadframe layer by a low inductance layer of an electrically and thermally conductive attachment material; 15 the source, drain and gate contact areas of the GaN die being attached and electrically connected to respective source, drain and gate portions of the ﬁrst leadframe layer by low inductance interconnections; a package body comprising an over-molding of encapsulation which leaves exposed the thermal pad of the second leadframe layer and leaves exposed external contact pads for the 20 source, drain and gate of the lateral GaN transistor; and wherein said external contact pads for the source, drain and gate contacts are parts of the ﬁrst leadframe layer and are provided on a front-side of the package body and the thermal pad is provided on a back-side of the package body.
1. 2
  Dependent← claim 1lateral GaN power transistor dual leadframe package
  The device structure of claim 1, wherein one of the ﬁrst and second leadframe layers further comprises a source clip portion, laterally spaced from the die substrate, which vertically interconnects the second leadframe layer and the source portion of the ﬁrst leadframe layer, thereby providing a substrate source connection for grounding the die substrate to the source. 29
15
IndependentGaNcopper or copper alloyelectrically and thermally conductive attachment materiallateral GaN power transistor dual leadframe package
A method of fabricating a semiconductor device structure comprising an assembly of: a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising ﬁrst and second leadframe layers for encapsulation within 10 a package body, the method comprising: providing the GaN die comprising a front surface comprising source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach; providing a ﬁrst leadframe layer and a second leadframe layer; the ﬁrst leadframe layer being patterned to provide source, drain and gate portions, the source 15 portion comprising an external source pad and a plurality of source ﬁngers extending laterally from the source pad, the drain portion comprising an external drain pad and a plurality of drain ﬁngers extending laterally from the drain pad, to provide source, drain and gate contact areas of the source, gate and drain portions corresponding to the source, drain and gate contact areas on the front surface of the GaN die; 20 the second leadframe layer providing a thermal pad and die-attach area for the back surface of the GaN die, at least one of the ﬁrst and second leadframe layers comprising a source clip portion which extends laterally of the die attach area of the second leadframe layer for vertical interconnection with the source portion of the ﬁrst leadframe layer; 25 attaching the back surface of the GaN die to the die-attach area of the second leadframe layer with a layer electrically and thermally conductive material; providing low inductance metal bump or metal post connections for source, drain and gate contact areas of the GaN die, and providing a layer of electrically and thermally conductive attachment material for any other surfaces to be electrically interconnected; 32 mutually positioning the ﬁrst and second leadframes to align respective source, drain and gate contacts thereof, with at least one of bump connections, post connections and attachment material therebetween; processing the respective bump connections, post connections and the attachment material to 5 vertically attach, and thermally and electrically interconnect the source, drain and gate contact areas of the GaN die and respective source, drain and gate portions of the ﬁrst copper leadframe layer; and providing a package body comprising an over-molding of encapsulation, exposing the thermal pad of second copper leadframe layer and exposing the external contact pads for the source, 10 drain and gate of the lateral GaN transistor.
1. 16
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, comprising interconnecting the source, drain and gate contact areas on the front side of the GaN die with the respective source, drain and gate portions of the ﬁrst leadframe layer, and subsequently attaching the backside of the GaN die to the die attach 15 area of the thermal pad of second leadframe layer.
2. 17
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, comprising attaching the backside of GaN die to the die attach area of the thermal pad of the second leadframe layer prior to aligning and interconnecting the respective source, drain and gate portions of the ﬁrst leadframe layer with 20 the source, drain and gate contact areas of the GaN die.
3. 18
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein, the ﬁrst lead frame layer is patterned to provide source, drain and gate portions comprising areas for the external source, drain and gate pads; the source portion further comprises tapered source ﬁngers extending laterally from the source 25 pad; the drain portion further comprises tapered drain ﬁngers extending laterally from the drain pad; and the source portions and drain portions being half-etched so that the source ﬁngers and drain ﬁngers are thinner than the source pad and the drain pad. 33
4. 19
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein, the ﬁrst lead frame layer is patterned to provide source, drain and gate portions comprising areas for the external source, drain and gate pads; the source portion further comprises tapered source ﬁngers extending laterally from the source pad; the drain portion further comprises tapered drain ﬁngers extending laterally from the 5 drain pad; and wherein the source ﬁngers and the source pad and the drain ﬁngers and the drain pad have the same thickness, so that after providing an over-molding of encapsulation, the source portion comprising the source pad and the source ﬁngers and the drain portion comprising the drain pad and the drain ﬁngers are exposed on the back surface of the package body, and further comprising: 10 half etching the exposed source ﬁngers and drain ﬁngers to thin the source ﬁngers and drain ﬁngers to a thickness less than that of the source pad and drain pad and then providing a second encapsulation to embed the source ﬁngers and the drain ﬁngers within the package body, leaving the source, drain and gate pads exposed on the back side of the package body.
5. 20
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein the ﬁrst leadframe layer comprises a supporting frame surrounding said source, drain, gate or thermal pad portions and further comprising: removing said supporting frame during device singulation.
6. 21
  Dependent← claim 15lateral GaN power transistor dual leadframe package
  The method of claim 15, wherein said ﬁrst and second leadframe layers are provided 20 with registration means comprising tabs of one of the leadframe layers for inter-engagement with slots of the other leadframe layer, and further comprising: inter-engaging said tabs and slots for mutual registration, vertically and horizontally, of the ﬁrst and second leadframe layers.

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

lateral GaN power transistor dual leadframe package

copper or copper alloyfront leadframe source drain gate portions

copper or copper alloylow inductance interconnections

GaNGaN die substrate

electrically and thermally conductive attachment materialdie attach

copper or copper alloyback leadframe thermal pad

Materials

Materials described outside the worked examples.

GaN (gallium nitride)

GaN

Transistor Active Material

copper or copper alloy

Leadframe Material

electrically and thermally conductive attachment material

Why these are connected

Related documents with shared materials, methods, properties, or citations.