Patent
US 11,107,753PACKAGING STRUCTURE FOR GALLIUM NITRIDE DEVICES
Stephen ST. GERMAIN
US
Copyright © 2026 Matter42. All rights reserved.
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US 11,107,753Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross sectional view of an implementation of a semiconductor package; [0029]
FIG. 2 is a cross sectional view of another implementation of a semiconductor package; [0030]
FIG. 3 is a cross sectional view of an implementation of a semiconductor package; [0031]
FIG. 4 is a top perspective view of an implementation of a semiconductor package having two die; [0032]
FIG. 5 is a top view of an implementation of a semiconductor package; [0033]
FIG. 6 is a perspective view of an implementation of a semiconductor package having one die; [0034]
FIG. 7 is a perspective view of an implementation of a semiconductor package; [0035]
FIG. 8 is a perspective view of an implementation of a substrate having vias extending from a first side of the substrate to the second side of the substrate; …
FIG. 9 is a perspective view of an implementation of a panel of substrates having traces; [0037]
FIG. 10 is a perspective view of an implementation of a substrate having die attach material on the traces; [0038]
FIG. 11 is a perspective view of an implementation of die coupled to a substrate; [0039]
FIG. 12 is a perspective view of an implementation of adhesive on die; [0040]
FIG. 13 is a perspective view of an implementation of clips coupled to the die and the substrate; [0041]
FIG. 14 is a perspective view of an implementation of a components on a substrate coupled through wire bonds; [0042]
FIG. 15 is a perspective view of an implementation of two substrates after singulation; [0043]
FIG. 16 is a side view of substrate coupled to a mounting tape; [0044]
FIG. 17 is a perspective view of an implementation of a first side semiconductor after encapsulation; [0045]
FIG. 18 is a perspective view of an implementation of a second side of an encapsulated semiconductor package; [0046]
FIG. 19 is a top view of an implementation of a first side of a semiconductor package; [0047]
FIG. 20 is a top view of an implementation of a second side of a semiconductor package; [0048]
FIG. 21 is a side view of an implementation of a power module; and [0049]
FIG. 22 is a perspective view of an implementation of a semiconductor module.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A semiconductor package comprising: a substrate comprising one or more traces on a first side and one or more traces on a second side of the substrate opposite the first side of the substrate, wherein the substrate is rigid; at least one die mechanically and electrically coupled to the first side of the substrate, wherein the die is a high voltage die; one or more traces extending fully across one or more external edges of the substrate, the one or more traces extending across a full thickness of the substrate located between the first side and the second side; and a molding compound covering at least the first side of the substrate and directly coupled to and covering the one or more traces that extend fully across the one or more external edges of the substrate; wherein the one or more traces that extend fully across the one or more edges of the substrate across the full thickness physically and electrically connect the one or more traces on the first side of the substrate with the one or more traces on the second side of the substrate. Currently amended
The semiconductor package of claim 1, wherein the substrate is ceramic and comprises one of aluminum nitride, aluminum oxide, or any combination thereof. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the substrate is a direct bonded copper substrate. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the die comprises gallium nitride (GaN). Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, further comprising one of a clip or two or more wirebonds electrically coupling the one or more die to the substrate. Currently amended
(Withdrawn-Currently Amended) The semiconductor package of claim 1, further comprising one or more copper pillars coupled to one of the first side or the second side of the substrate. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the substrate is ceramic and comprises one of aluminum nitride, aluminum oxide, or any combination thereof. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the substrate is a direct bonded copper substrate. Currently amended
The semiconductor package of claim 1, wherein the molding compound is an insulative molding compound. New
A semiconductor package comprising: a ceramic substrate comprising one or more traces on a first side and one or more traces on a second side of the ceramic substrate opposite the first side of the ceramic substrate, wherein the ceramic substrate is rigid and electrically insulative; at least one high voltage die mechanically and electrically coupled to the first side of the ceramic substrate; one or more traces extending from the first side to the second side of the ceramic substrate across a full thickness of the ceramic substrate and completely across an external surface of the ceramic substrate located across the full thickness; and a molding compound encapsulating at least the first side and fully encapsulating the one or more traces that extend completely across the external surface of the ceramic substrate; wherein the molding compound is directly coupled to the one or more traces that extend completely across the external surface of the ceramic substrate; and wherein the one or more traces that extend completely across the external surface of the ceramic substrate provide electrical connectivity between the one or more traces on the first side of the ceramic substrate and the one or more traces on the second side of the ceramic substrate. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 8, wherein the ceramic substrate omprises one of aluminum nitride, aluminum oxide, or any combination thereof. Currently amended
The semiconductor package of claim 8, wherein the die comprises gallium nitride (GaN). Currently amended
(Cu rr ently Amended) The semiconductor package of claim 8, further comprising one of a clip of two or more wirebonds electrically coupling the one or more die to the ceramic substrate. Currently amended
(Withdrawn-Currently Amended) The semiconductor package of claim 8, further comprising one or more copper pillars coupled to one of the first side or the second side of the ceramic substrate. Currently amended
14-20.. Canceled
Canceled
A substrate for a semiconductor package, the substrate comprising: one or more traces on a first side of a substrate and one or more traces on a second side of the substrate, the first side opposite the second side; one or more traces extending across one or more external edges of the substrate, the one or more traces extending across a full thickness of the substrate located between the first side and second side; and an insulative molding compound directly coupled to and encapsulating the one or more traces extending across the full thickness of the substrate; wherein the one or more traces that extend along the one or more external edges of the substrate across the full thickness physically and electrically connect the one or more traces on the first side of the substrate with the one or more traces on the second side of the substrate. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor package with rigid substrate and edge traces
semiconductor package with ceramic substrate and edge traces
Materials described outside the worked examples.
aluminum nitride
AlN
aluminum oxide
Al₂O₃
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 200 V | — |
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Patent
Atlas literature
Patent
US 11,107,753Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross sectional view of an implementation of a semiconductor package; [0029]
FIG. 2 is a cross sectional view of another implementation of a semiconductor package; [0030]
FIG. 3 is a cross sectional view of an implementation of a semiconductor package; [0031]
FIG. 4 is a top perspective view of an implementation of a semiconductor package having two die; [0032]
FIG. 5 is a top view of an implementation of a semiconductor package; [0033]
FIG. 6 is a perspective view of an implementation of a semiconductor package having one die; [0034]
FIG. 7 is a perspective view of an implementation of a semiconductor package; [0035]
FIG. 8 is a perspective view of an implementation of a substrate having vias extending from a first side of the substrate to the second side of the substrate; …
FIG. 9 is a perspective view of an implementation of a panel of substrates having traces; [0037]
FIG. 10 is a perspective view of an implementation of a substrate having die attach material on the traces; [0038]
FIG. 11 is a perspective view of an implementation of die coupled to a substrate; [0039]
FIG. 12 is a perspective view of an implementation of adhesive on die; [0040]
FIG. 13 is a perspective view of an implementation of clips coupled to the die and the substrate; [0041]
FIG. 14 is a perspective view of an implementation of a components on a substrate coupled through wire bonds; [0042]
FIG. 15 is a perspective view of an implementation of two substrates after singulation; [0043]
FIG. 16 is a side view of substrate coupled to a mounting tape; [0044]
FIG. 17 is a perspective view of an implementation of a first side semiconductor after encapsulation; [0045]
FIG. 18 is a perspective view of an implementation of a second side of an encapsulated semiconductor package; [0046]
FIG. 19 is a top view of an implementation of a first side of a semiconductor package; [0047]
FIG. 20 is a top view of an implementation of a second side of a semiconductor package; [0048]
FIG. 21 is a side view of an implementation of a power module; and [0049]
FIG. 22 is a perspective view of an implementation of a semiconductor module.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A semiconductor package comprising: a substrate comprising one or more traces on a first side and one or more traces on a second side of the substrate opposite the first side of the substrate, wherein the substrate is rigid; at least one die mechanically and electrically coupled to the first side of the substrate, wherein the die is a high voltage die; one or more traces extending fully across one or more external edges of the substrate, the one or more traces extending across a full thickness of the substrate located between the first side and the second side; and a molding compound covering at least the first side of the substrate and directly coupled to and covering the one or more traces that extend fully across the one or more external edges of the substrate; wherein the one or more traces that extend fully across the one or more edges of the substrate across the full thickness physically and electrically connect the one or more traces on the first side of the substrate with the one or more traces on the second side of the substrate. Currently amended
The semiconductor package of claim 1, wherein the substrate is ceramic and comprises one of aluminum nitride, aluminum oxide, or any combination thereof. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the substrate is a direct bonded copper substrate. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the die comprises gallium nitride (GaN). Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, further comprising one of a clip or two or more wirebonds electrically coupling the one or more die to the substrate. Currently amended
(Withdrawn-Currently Amended) The semiconductor package of claim 1, further comprising one or more copper pillars coupled to one of the first side or the second side of the substrate. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the substrate is ceramic and comprises one of aluminum nitride, aluminum oxide, or any combination thereof. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the substrate is a direct bonded copper substrate. Currently amended
The semiconductor package of claim 1, wherein the molding compound is an insulative molding compound. New
A semiconductor package comprising: a ceramic substrate comprising one or more traces on a first side and one or more traces on a second side of the ceramic substrate opposite the first side of the ceramic substrate, wherein the ceramic substrate is rigid and electrically insulative; at least one high voltage die mechanically and electrically coupled to the first side of the ceramic substrate; one or more traces extending from the first side to the second side of the ceramic substrate across a full thickness of the ceramic substrate and completely across an external surface of the ceramic substrate located across the full thickness; and a molding compound encapsulating at least the first side and fully encapsulating the one or more traces that extend completely across the external surface of the ceramic substrate; wherein the molding compound is directly coupled to the one or more traces that extend completely across the external surface of the ceramic substrate; and wherein the one or more traces that extend completely across the external surface of the ceramic substrate provide electrical connectivity between the one or more traces on the first side of the ceramic substrate and the one or more traces on the second side of the ceramic substrate. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 8, wherein the ceramic substrate omprises one of aluminum nitride, aluminum oxide, or any combination thereof. Currently amended
The semiconductor package of claim 8, wherein the die comprises gallium nitride (GaN). Currently amended
(Cu rr ently Amended) The semiconductor package of claim 8, further comprising one of a clip of two or more wirebonds electrically coupling the one or more die to the ceramic substrate. Currently amended
(Withdrawn-Currently Amended) The semiconductor package of claim 8, further comprising one or more copper pillars coupled to one of the first side or the second side of the ceramic substrate. Currently amended
14-20.. Canceled
Canceled
A substrate for a semiconductor package, the substrate comprising: one or more traces on a first side of a substrate and one or more traces on a second side of the substrate, the first side opposite the second side; one or more traces extending across one or more external edges of the substrate, the one or more traces extending across a full thickness of the substrate located between the first side and second side; and an insulative molding compound directly coupled to and encapsulating the one or more traces extending across the full thickness of the substrate; wherein the one or more traces that extend along the one or more external edges of the substrate across the full thickness physically and electrically connect the one or more traces on the first side of the substrate with the one or more traces on the second side of the substrate. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor package with rigid substrate and edge traces
semiconductor package with ceramic substrate and edge traces
Materials described outside the worked examples.
aluminum nitride
AlN
aluminum oxide
Al₂O₃
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 200 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,107,753Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross sectional view of an implementation of a semiconductor package; [0029]
FIG. 2 is a cross sectional view of another implementation of a semiconductor package; [0030]
FIG. 3 is a cross sectional view of an implementation of a semiconductor package; [0031]
FIG. 4 is a top perspective view of an implementation of a semiconductor package having two die; [0032]
FIG. 5 is a top view of an implementation of a semiconductor package; [0033]
FIG. 6 is a perspective view of an implementation of a semiconductor package having one die; [0034]
FIG. 7 is a perspective view of an implementation of a semiconductor package; [0035]
FIG. 8 is a perspective view of an implementation of a substrate having vias extending from a first side of the substrate to the second side of the substrate; …
FIG. 9 is a perspective view of an implementation of a panel of substrates having traces; [0037]
FIG. 10 is a perspective view of an implementation of a substrate having die attach material on the traces; [0038]
FIG. 11 is a perspective view of an implementation of die coupled to a substrate; [0039]
FIG. 12 is a perspective view of an implementation of adhesive on die; [0040]
FIG. 13 is a perspective view of an implementation of clips coupled to the die and the substrate; [0041]
FIG. 14 is a perspective view of an implementation of a components on a substrate coupled through wire bonds; [0042]
FIG. 15 is a perspective view of an implementation of two substrates after singulation; [0043]
FIG. 16 is a side view of substrate coupled to a mounting tape; [0044]
FIG. 17 is a perspective view of an implementation of a first side semiconductor after encapsulation; [0045]
FIG. 18 is a perspective view of an implementation of a second side of an encapsulated semiconductor package; [0046]
FIG. 19 is a top view of an implementation of a first side of a semiconductor package; [0047]
FIG. 20 is a top view of an implementation of a second side of a semiconductor package; [0048]
FIG. 21 is a side view of an implementation of a power module; and [0049]
FIG. 22 is a perspective view of an implementation of a semiconductor module.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A semiconductor package comprising: a substrate comprising one or more traces on a first side and one or more traces on a second side of the substrate opposite the first side of the substrate, wherein the substrate is rigid; at least one die mechanically and electrically coupled to the first side of the substrate, wherein the die is a high voltage die; one or more traces extending fully across one or more external edges of the substrate, the one or more traces extending across a full thickness of the substrate located between the first side and the second side; and a molding compound covering at least the first side of the substrate and directly coupled to and covering the one or more traces that extend fully across the one or more external edges of the substrate; wherein the one or more traces that extend fully across the one or more edges of the substrate across the full thickness physically and electrically connect the one or more traces on the first side of the substrate with the one or more traces on the second side of the substrate. Currently amended
The semiconductor package of claim 1, wherein the substrate is ceramic and comprises one of aluminum nitride, aluminum oxide, or any combination thereof. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the substrate is a direct bonded copper substrate. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the die comprises gallium nitride (GaN). Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, further comprising one of a clip or two or more wirebonds electrically coupling the one or more die to the substrate. Currently amended
(Withdrawn-Currently Amended) The semiconductor package of claim 1, further comprising one or more copper pillars coupled to one of the first side or the second side of the substrate. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the substrate is ceramic and comprises one of aluminum nitride, aluminum oxide, or any combination thereof. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the substrate is a direct bonded copper substrate. Currently amended
The semiconductor package of claim 1, wherein the molding compound is an insulative molding compound. New
A semiconductor package comprising: a ceramic substrate comprising one or more traces on a first side and one or more traces on a second side of the ceramic substrate opposite the first side of the ceramic substrate, wherein the ceramic substrate is rigid and electrically insulative; at least one high voltage die mechanically and electrically coupled to the first side of the ceramic substrate; one or more traces extending from the first side to the second side of the ceramic substrate across a full thickness of the ceramic substrate and completely across an external surface of the ceramic substrate located across the full thickness; and a molding compound encapsulating at least the first side and fully encapsulating the one or more traces that extend completely across the external surface of the ceramic substrate; wherein the molding compound is directly coupled to the one or more traces that extend completely across the external surface of the ceramic substrate; and wherein the one or more traces that extend completely across the external surface of the ceramic substrate provide electrical connectivity between the one or more traces on the first side of the ceramic substrate and the one or more traces on the second side of the ceramic substrate. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 8, wherein the ceramic substrate omprises one of aluminum nitride, aluminum oxide, or any combination thereof. Currently amended
The semiconductor package of claim 8, wherein the die comprises gallium nitride (GaN). Currently amended
(Cu rr ently Amended) The semiconductor package of claim 8, further comprising one of a clip of two or more wirebonds electrically coupling the one or more die to the ceramic substrate. Currently amended
(Withdrawn-Currently Amended) The semiconductor package of claim 8, further comprising one or more copper pillars coupled to one of the first side or the second side of the ceramic substrate. Currently amended
14-20.. Canceled
Canceled
A substrate for a semiconductor package, the substrate comprising: one or more traces on a first side of a substrate and one or more traces on a second side of the substrate, the first side opposite the second side; one or more traces extending across one or more external edges of the substrate, the one or more traces extending across a full thickness of the substrate located between the first side and second side; and an insulative molding compound directly coupled to and encapsulating the one or more traces extending across the full thickness of the substrate; wherein the one or more traces that extend along the one or more external edges of the substrate across the full thickness physically and electrically connect the one or more traces on the first side of the substrate with the one or more traces on the second side of the substrate. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor package with rigid substrate and edge traces
semiconductor package with ceramic substrate and edge traces
Materials described outside the worked examples.
aluminum nitride
AlN
aluminum oxide
Al₂O₃
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 200 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,107,753Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross sectional view of an implementation of a semiconductor package; [0029]
FIG. 2 is a cross sectional view of another implementation of a semiconductor package; [0030]
FIG. 3 is a cross sectional view of an implementation of a semiconductor package; [0031]
FIG. 4 is a top perspective view of an implementation of a semiconductor package having two die; [0032]
FIG. 5 is a top view of an implementation of a semiconductor package; [0033]
FIG. 6 is a perspective view of an implementation of a semiconductor package having one die; [0034]
FIG. 7 is a perspective view of an implementation of a semiconductor package; [0035]
FIG. 8 is a perspective view of an implementation of a substrate having vias extending from a first side of the substrate to the second side of the substrate; …
FIG. 9 is a perspective view of an implementation of a panel of substrates having traces; [0037]
FIG. 10 is a perspective view of an implementation of a substrate having die attach material on the traces; [0038]
FIG. 11 is a perspective view of an implementation of die coupled to a substrate; [0039]
FIG. 12 is a perspective view of an implementation of adhesive on die; [0040]
FIG. 13 is a perspective view of an implementation of clips coupled to the die and the substrate; [0041]
FIG. 14 is a perspective view of an implementation of a components on a substrate coupled through wire bonds; [0042]
FIG. 15 is a perspective view of an implementation of two substrates after singulation; [0043]
FIG. 16 is a side view of substrate coupled to a mounting tape; [0044]
FIG. 17 is a perspective view of an implementation of a first side semiconductor after encapsulation; [0045]
FIG. 18 is a perspective view of an implementation of a second side of an encapsulated semiconductor package; [0046]
FIG. 19 is a top view of an implementation of a first side of a semiconductor package; [0047]
FIG. 20 is a top view of an implementation of a second side of a semiconductor package; [0048]
FIG. 21 is a side view of an implementation of a power module; and [0049]
FIG. 22 is a perspective view of an implementation of a semiconductor module.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A semiconductor package comprising: a substrate comprising one or more traces on a first side and one or more traces on a second side of the substrate opposite the first side of the substrate, wherein the substrate is rigid; at least one die mechanically and electrically coupled to the first side of the substrate, wherein the die is a high voltage die; one or more traces extending fully across one or more external edges of the substrate, the one or more traces extending across a full thickness of the substrate located between the first side and the second side; and a molding compound covering at least the first side of the substrate and directly coupled to and covering the one or more traces that extend fully across the one or more external edges of the substrate; wherein the one or more traces that extend fully across the one or more edges of the substrate across the full thickness physically and electrically connect the one or more traces on the first side of the substrate with the one or more traces on the second side of the substrate. Currently amended
The semiconductor package of claim 1, wherein the substrate is ceramic and comprises one of aluminum nitride, aluminum oxide, or any combination thereof. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the substrate is a direct bonded copper substrate. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the die comprises gallium nitride (GaN). Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, further comprising one of a clip or two or more wirebonds electrically coupling the one or more die to the substrate. Currently amended
(Withdrawn-Currently Amended) The semiconductor package of claim 1, further comprising one or more copper pillars coupled to one of the first side or the second side of the substrate. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the substrate is ceramic and comprises one of aluminum nitride, aluminum oxide, or any combination thereof. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 1, wherein the substrate is a direct bonded copper substrate. Currently amended
The semiconductor package of claim 1, wherein the molding compound is an insulative molding compound. New
A semiconductor package comprising: a ceramic substrate comprising one or more traces on a first side and one or more traces on a second side of the ceramic substrate opposite the first side of the ceramic substrate, wherein the ceramic substrate is rigid and electrically insulative; at least one high voltage die mechanically and electrically coupled to the first side of the ceramic substrate; one or more traces extending from the first side to the second side of the ceramic substrate across a full thickness of the ceramic substrate and completely across an external surface of the ceramic substrate located across the full thickness; and a molding compound encapsulating at least the first side and fully encapsulating the one or more traces that extend completely across the external surface of the ceramic substrate; wherein the molding compound is directly coupled to the one or more traces that extend completely across the external surface of the ceramic substrate; and wherein the one or more traces that extend completely across the external surface of the ceramic substrate provide electrical connectivity between the one or more traces on the first side of the ceramic substrate and the one or more traces on the second side of the ceramic substrate. Currently amended
(Cu rr ently Amended) The semiconductor package of claim 8, wherein the ceramic substrate omprises one of aluminum nitride, aluminum oxide, or any combination thereof. Currently amended
The semiconductor package of claim 8, wherein the die comprises gallium nitride (GaN). Currently amended
(Cu rr ently Amended) The semiconductor package of claim 8, further comprising one of a clip of two or more wirebonds electrically coupling the one or more die to the ceramic substrate. Currently amended
(Withdrawn-Currently Amended) The semiconductor package of claim 8, further comprising one or more copper pillars coupled to one of the first side or the second side of the ceramic substrate. Currently amended
14-20.. Canceled
Canceled
A substrate for a semiconductor package, the substrate comprising: one or more traces on a first side of a substrate and one or more traces on a second side of the substrate, the first side opposite the second side; one or more traces extending across one or more external edges of the substrate, the one or more traces extending across a full thickness of the substrate located between the first side and second side; and an insulative molding compound directly coupled to and encapsulating the one or more traces extending across the full thickness of the substrate; wherein the one or more traces that extend along the one or more external edges of the substrate across the full thickness physically and electrically connect the one or more traces on the first side of the substrate with the one or more traces on the second side of the substrate. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor package with rigid substrate and edge traces
semiconductor package with ceramic substrate and edge traces
Materials described outside the worked examples.
aluminum nitride
AlN
aluminum oxide
Al₂O₃
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 200 V | — |
Related documents with shared materials, methods, properties, or citations.
substrate for semiconductor package with edge traces and insulative molding compound
direct bonded copper substrate
gallium nitride
GaN
copper pillars
ceramic substrate
molding compound
copper traces
substrate for semiconductor package with edge traces and insulative molding compound
direct bonded copper substrate
gallium nitride
GaN
copper pillars
ceramic substrate
molding compound
copper traces
substrate for semiconductor package with edge traces and insulative molding compound
direct bonded copper substrate
gallium nitride
GaN
copper pillars
ceramic substrate
molding compound
copper traces
substrate for semiconductor package with edge traces and insulative molding compound
direct bonded copper substrate
gallium nitride
GaN
copper pillars
ceramic substrate
molding compound
copper traces