Patent
US 9,437,716SEMICONDUCTOR DEVICE COMPRISING A GRAPHENE WIRE
Makoto WADA
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,437,716Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view showing the schematic structure of a semiconductor device according to a first embodiment.
FIG. 2 is a schematic view showing the six-member 20 ring structure of graphene sheets.
FIG. 3 is a schematic view showing the six-member ring structure of graphene sheets in which an impurity is doped.
FIG. 4 is a birds-eye view showing the graphene 25 wiring structures used in the semiconductor device of
FIGS. 5A to 5 D are cross-sectional views showing -3-the manufacturing steps of the semiconductor device of
FIGS. 6A and 6B are cross-sectional views each showing the schematic structure of a semiconductor 5 device according to a second embodiment.
FIG. 7 is a cross-sectional view showing the schematic structure of a semiconductor device according to a third embodiment.
FIGS. 8A to 8C are cross-sectional views showing 10 the manufacturing steps of the semiconductor device of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a metal layer provided above a substrate comprising a semiconductor element, the metal layer extending in a first longitudinal direction and having a convex cross- sectional surface in a plane perpendicular to the first longitudinal direction; and a graphene layer provided on the metal layer to surround a side surface and an upper surface of a convex portion of the metal layer, the graphene layer having a curved cross-sectional surface and extending in the first longitudinal direction, wherein the metal layer comprises a first portion which is flat and a second portion which is convex, and wherein the second portion has a tapered shape whose widths of upper and lower surfaces are different, and has surface (111) alignment.
The semiconductor device of claim 1, wherein the first portion is an underlying layer, and the second portion is a catalyst layer.
The semiconductor device of claim 1, wherein an end portion of the graphene layer contacts at least one of an upper surface of the first portion and a side surface of the second portion. Response to Final Office Action Page 3 Serial Number: 14/803,751
SVG 14803751.04-25-2016.INGKR₅I₄PXXIFW3.CLM.2.3.299.218.2250.258.svg 0.133 6.503 Chemistry Black and white 5. The semiconductor device of claim 1, wherein a facet is provided on a side surface of the second portion, and an end portion of the graphene layer contacts the facet.
The semiconductor device of claim 1, wherein the upper surface of the second portion is narrower than the lower surface of the second portion.
The semiconductor device of claim 1, wherein the graphene layer is formed in a roll shape.
canceled
canceled
A semiconductor device comprising: a metal layer provided above a substrate comprising a semiconductor element, the metal layer extending in a first longitudinal direction; and a graphene layer provided on the metal layer to surround a side surface and an upper surface of the metal layer, the graphene layer extending in the first longitudinal Response to Final Office Action Page 4 Serial Number: 14/803,751 SVG 14803751.04-25-2016.INGKR₅I₄PXXIFW3.CLM.3.3.299.218.2250.258.svg 0.133 6.503 Chemistry Black and white direction and having a curved convex cross-sectional surface with respect to the metal layer in a plane perpendicular to the first longitudinal direction, wherein the metal layer comprises a first portion having a first width and including the upper surface, and a second portion which is provided on the first portion and which has a second width smaller than the first width, the second portion havin g a tapered shape whose widths of upper and lower surfaces are different, and wherein the graphene layer comprises a plurality of graphene sheets which are stacked, and a portion of end portions of the graphene sheets is in contact with the upper surface of the first portion of the metal layer.
The semiconductor device of claim 10, wherein the first portion is an underlying layer, and the second portion is a catalyst layer.
The semiconductor device of claim 10, wherein a facet is provided on a side surface of the second portion, and another portion of end portions of the graphene sheets is in contact with the facet.
The semiconductor device of claim 10, wherein the second portion has a tapered shape whose widths of upper and lower surfaces are different, and has surface (111) alignment.
SVG 14803751.04-25-2016.INGKR₅I₄PXXIFW3.CLM.4.3.299.218.2250.258.svg 0.133 6.503 Chemistry Black and white 15. The semiconductor device of claim 10, wherein the graphene layer is formed in a roll shape.
Layer stacks claimed or described, ordered top of device to substrate.
graphene wiring structure (claim 1 embodiment)
Materials described outside the worked examples.
graphene layer
catalyst underlying layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene sheet interlayer distance (undoped) | 0.34 nm | graphene layer |
average free path of electrons in graphene layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,437,716Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view showing the schematic structure of a semiconductor device according to a first embodiment.
FIG. 2 is a schematic view showing the six-member 20 ring structure of graphene sheets.
FIG. 3 is a schematic view showing the six-member ring structure of graphene sheets in which an impurity is doped.
FIG. 4 is a birds-eye view showing the graphene 25 wiring structures used in the semiconductor device of
FIGS. 5A to 5 D are cross-sectional views showing -3-the manufacturing steps of the semiconductor device of
FIGS. 6A and 6B are cross-sectional views each showing the schematic structure of a semiconductor 5 device according to a second embodiment.
FIG. 7 is a cross-sectional view showing the schematic structure of a semiconductor device according to a third embodiment.
FIGS. 8A to 8C are cross-sectional views showing 10 the manufacturing steps of the semiconductor device of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a metal layer provided above a substrate comprising a semiconductor element, the metal layer extending in a first longitudinal direction and having a convex cross- sectional surface in a plane perpendicular to the first longitudinal direction; and a graphene layer provided on the metal layer to surround a side surface and an upper surface of a convex portion of the metal layer, the graphene layer having a curved cross-sectional surface and extending in the first longitudinal direction, wherein the metal layer comprises a first portion which is flat and a second portion which is convex, and wherein the second portion has a tapered shape whose widths of upper and lower surfaces are different, and has surface (111) alignment.
The semiconductor device of claim 1, wherein the first portion is an underlying layer, and the second portion is a catalyst layer.
The semiconductor device of claim 1, wherein an end portion of the graphene layer contacts at least one of an upper surface of the first portion and a side surface of the second portion. Response to Final Office Action Page 3 Serial Number: 14/803,751
SVG 14803751.04-25-2016.INGKR₅I₄PXXIFW3.CLM.2.3.299.218.2250.258.svg 0.133 6.503 Chemistry Black and white 5. The semiconductor device of claim 1, wherein a facet is provided on a side surface of the second portion, and an end portion of the graphene layer contacts the facet.
The semiconductor device of claim 1, wherein the upper surface of the second portion is narrower than the lower surface of the second portion.
The semiconductor device of claim 1, wherein the graphene layer is formed in a roll shape.
canceled
canceled
A semiconductor device comprising: a metal layer provided above a substrate comprising a semiconductor element, the metal layer extending in a first longitudinal direction; and a graphene layer provided on the metal layer to surround a side surface and an upper surface of the metal layer, the graphene layer extending in the first longitudinal Response to Final Office Action Page 4 Serial Number: 14/803,751 SVG 14803751.04-25-2016.INGKR₅I₄PXXIFW3.CLM.3.3.299.218.2250.258.svg 0.133 6.503 Chemistry Black and white direction and having a curved convex cross-sectional surface with respect to the metal layer in a plane perpendicular to the first longitudinal direction, wherein the metal layer comprises a first portion having a first width and including the upper surface, and a second portion which is provided on the first portion and which has a second width smaller than the first width, the second portion havin g a tapered shape whose widths of upper and lower surfaces are different, and wherein the graphene layer comprises a plurality of graphene sheets which are stacked, and a portion of end portions of the graphene sheets is in contact with the upper surface of the first portion of the metal layer.
The semiconductor device of claim 10, wherein the first portion is an underlying layer, and the second portion is a catalyst layer.
The semiconductor device of claim 10, wherein a facet is provided on a side surface of the second portion, and another portion of end portions of the graphene sheets is in contact with the facet.
The semiconductor device of claim 10, wherein the second portion has a tapered shape whose widths of upper and lower surfaces are different, and has surface (111) alignment.
SVG 14803751.04-25-2016.INGKR₅I₄PXXIFW3.CLM.4.3.299.218.2250.258.svg 0.133 6.503 Chemistry Black and white 15. The semiconductor device of claim 10, wherein the graphene layer is formed in a roll shape.
Layer stacks claimed or described, ordered top of device to substrate.
graphene wiring structure (claim 1 embodiment)
Materials described outside the worked examples.
graphene layer
catalyst underlying layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene sheet interlayer distance (undoped) | 0.34 nm | graphene layer |
average free path of electrons in graphene layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,437,716Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view showing the schematic structure of a semiconductor device according to a first embodiment.
FIG. 2 is a schematic view showing the six-member 20 ring structure of graphene sheets.
FIG. 3 is a schematic view showing the six-member ring structure of graphene sheets in which an impurity is doped.
FIG. 4 is a birds-eye view showing the graphene 25 wiring structures used in the semiconductor device of
FIGS. 5A to 5 D are cross-sectional views showing -3-the manufacturing steps of the semiconductor device of
FIGS. 6A and 6B are cross-sectional views each showing the schematic structure of a semiconductor 5 device according to a second embodiment.
FIG. 7 is a cross-sectional view showing the schematic structure of a semiconductor device according to a third embodiment.
FIGS. 8A to 8C are cross-sectional views showing 10 the manufacturing steps of the semiconductor device of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a metal layer provided above a substrate comprising a semiconductor element, the metal layer extending in a first longitudinal direction and having a convex cross- sectional surface in a plane perpendicular to the first longitudinal direction; and a graphene layer provided on the metal layer to surround a side surface and an upper surface of a convex portion of the metal layer, the graphene layer having a curved cross-sectional surface and extending in the first longitudinal direction, wherein the metal layer comprises a first portion which is flat and a second portion which is convex, and wherein the second portion has a tapered shape whose widths of upper and lower surfaces are different, and has surface (111) alignment.
The semiconductor device of claim 1, wherein the first portion is an underlying layer, and the second portion is a catalyst layer.
The semiconductor device of claim 1, wherein an end portion of the graphene layer contacts at least one of an upper surface of the first portion and a side surface of the second portion. Response to Final Office Action Page 3 Serial Number: 14/803,751
SVG 14803751.04-25-2016.INGKR₅I₄PXXIFW3.CLM.2.3.299.218.2250.258.svg 0.133 6.503 Chemistry Black and white 5. The semiconductor device of claim 1, wherein a facet is provided on a side surface of the second portion, and an end portion of the graphene layer contacts the facet.
The semiconductor device of claim 1, wherein the upper surface of the second portion is narrower than the lower surface of the second portion.
The semiconductor device of claim 1, wherein the graphene layer is formed in a roll shape.
canceled
canceled
A semiconductor device comprising: a metal layer provided above a substrate comprising a semiconductor element, the metal layer extending in a first longitudinal direction; and a graphene layer provided on the metal layer to surround a side surface and an upper surface of the metal layer, the graphene layer extending in the first longitudinal Response to Final Office Action Page 4 Serial Number: 14/803,751 SVG 14803751.04-25-2016.INGKR₅I₄PXXIFW3.CLM.3.3.299.218.2250.258.svg 0.133 6.503 Chemistry Black and white direction and having a curved convex cross-sectional surface with respect to the metal layer in a plane perpendicular to the first longitudinal direction, wherein the metal layer comprises a first portion having a first width and including the upper surface, and a second portion which is provided on the first portion and which has a second width smaller than the first width, the second portion havin g a tapered shape whose widths of upper and lower surfaces are different, and wherein the graphene layer comprises a plurality of graphene sheets which are stacked, and a portion of end portions of the graphene sheets is in contact with the upper surface of the first portion of the metal layer.
The semiconductor device of claim 10, wherein the first portion is an underlying layer, and the second portion is a catalyst layer.
The semiconductor device of claim 10, wherein a facet is provided on a side surface of the second portion, and another portion of end portions of the graphene sheets is in contact with the facet.
The semiconductor device of claim 10, wherein the second portion has a tapered shape whose widths of upper and lower surfaces are different, and has surface (111) alignment.
SVG 14803751.04-25-2016.INGKR₅I₄PXXIFW3.CLM.4.3.299.218.2250.258.svg 0.133 6.503 Chemistry Black and white 15. The semiconductor device of claim 10, wherein the graphene layer is formed in a roll shape.
Layer stacks claimed or described, ordered top of device to substrate.
graphene wiring structure (claim 1 embodiment)
Materials described outside the worked examples.
graphene layer
catalyst underlying layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene sheet interlayer distance (undoped) | 0.34 nm | graphene layer |
average free path of electrons in graphene layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,437,716Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view showing the schematic structure of a semiconductor device according to a first embodiment.
FIG. 2 is a schematic view showing the six-member 20 ring structure of graphene sheets.
FIG. 3 is a schematic view showing the six-member ring structure of graphene sheets in which an impurity is doped.
FIG. 4 is a birds-eye view showing the graphene 25 wiring structures used in the semiconductor device of
FIGS. 5A to 5 D are cross-sectional views showing -3-the manufacturing steps of the semiconductor device of
FIGS. 6A and 6B are cross-sectional views each showing the schematic structure of a semiconductor 5 device according to a second embodiment.
FIG. 7 is a cross-sectional view showing the schematic structure of a semiconductor device according to a third embodiment.
FIGS. 8A to 8C are cross-sectional views showing 10 the manufacturing steps of the semiconductor device of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a metal layer provided above a substrate comprising a semiconductor element, the metal layer extending in a first longitudinal direction and having a convex cross- sectional surface in a plane perpendicular to the first longitudinal direction; and a graphene layer provided on the metal layer to surround a side surface and an upper surface of a convex portion of the metal layer, the graphene layer having a curved cross-sectional surface and extending in the first longitudinal direction, wherein the metal layer comprises a first portion which is flat and a second portion which is convex, and wherein the second portion has a tapered shape whose widths of upper and lower surfaces are different, and has surface (111) alignment.
The semiconductor device of claim 1, wherein the first portion is an underlying layer, and the second portion is a catalyst layer.
The semiconductor device of claim 1, wherein an end portion of the graphene layer contacts at least one of an upper surface of the first portion and a side surface of the second portion. Response to Final Office Action Page 3 Serial Number: 14/803,751
SVG 14803751.04-25-2016.INGKR₅I₄PXXIFW3.CLM.2.3.299.218.2250.258.svg 0.133 6.503 Chemistry Black and white 5. The semiconductor device of claim 1, wherein a facet is provided on a side surface of the second portion, and an end portion of the graphene layer contacts the facet.
The semiconductor device of claim 1, wherein the upper surface of the second portion is narrower than the lower surface of the second portion.
The semiconductor device of claim 1, wherein the graphene layer is formed in a roll shape.
canceled
canceled
A semiconductor device comprising: a metal layer provided above a substrate comprising a semiconductor element, the metal layer extending in a first longitudinal direction; and a graphene layer provided on the metal layer to surround a side surface and an upper surface of the metal layer, the graphene layer extending in the first longitudinal Response to Final Office Action Page 4 Serial Number: 14/803,751 SVG 14803751.04-25-2016.INGKR₅I₄PXXIFW3.CLM.3.3.299.218.2250.258.svg 0.133 6.503 Chemistry Black and white direction and having a curved convex cross-sectional surface with respect to the metal layer in a plane perpendicular to the first longitudinal direction, wherein the metal layer comprises a first portion having a first width and including the upper surface, and a second portion which is provided on the first portion and which has a second width smaller than the first width, the second portion havin g a tapered shape whose widths of upper and lower surfaces are different, and wherein the graphene layer comprises a plurality of graphene sheets which are stacked, and a portion of end portions of the graphene sheets is in contact with the upper surface of the first portion of the metal layer.
The semiconductor device of claim 10, wherein the first portion is an underlying layer, and the second portion is a catalyst layer.
The semiconductor device of claim 10, wherein a facet is provided on a side surface of the second portion, and another portion of end portions of the graphene sheets is in contact with the facet.
The semiconductor device of claim 10, wherein the second portion has a tapered shape whose widths of upper and lower surfaces are different, and has surface (111) alignment.
SVG 14803751.04-25-2016.INGKR₅I₄PXXIFW3.CLM.4.3.299.218.2250.258.svg 0.133 6.503 Chemistry Black and white 15. The semiconductor device of claim 10, wherein the graphene layer is formed in a roll shape.
Layer stacks claimed or described, ordered top of device to substrate.
graphene wiring structure (claim 1 embodiment)
Materials described outside the worked examples.
graphene layer
catalyst underlying layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene sheet interlayer distance (undoped) | 0.34 nm | graphene layer |
average free path of electrons in graphene layer |
Related documents with shared materials, methods, properties, or citations.
catalyst metal layer
Ti
Ta
Ru
W
Ti/TiN stack
Co
Ni
Fe
Cu
SiN
SiO₂
Al
| 100–1000 nm |
graphene layer |
average free path of electrons in Cu (LSI reference) | 40 nm | Cu |
wire width below which significant edge scattering effect reduction is achieved | 30 nm | graphene layer |
Temperature | 150–600 °C | — |
Thickness | ≥ 0.5 nm | — |
catalyst metal layer
Ti
Ta
Ru
W
Ti/TiN stack
Co
Ni
Fe
Cu
SiN
SiO₂
Al
| 100–1000 nm |
graphene layer |
average free path of electrons in Cu (LSI reference) | 40 nm | Cu |
wire width below which significant edge scattering effect reduction is achieved | 30 nm | graphene layer |
Temperature | 150–600 °C | — |
Thickness | ≥ 0.5 nm | — |
catalyst metal layer
Ti
Ta
Ru
W
Ti/TiN stack
Co
Ni
Fe
Cu
SiN
SiO₂
Al
| 100–1000 nm |
graphene layer |
average free path of electrons in Cu (LSI reference) | 40 nm | Cu |
wire width below which significant edge scattering effect reduction is achieved | 30 nm | graphene layer |
Temperature | 150–600 °C | — |
Thickness | ≥ 0.5 nm | — |
catalyst metal layer
Ti
Ta
Ru
W
Ti/TiN stack
Co
Ni
Fe
Cu
SiN
SiO₂
Al
| 100–1000 nm |
graphene layer |
average free path of electrons in Cu (LSI reference) | 40 nm | Cu |
wire width below which significant edge scattering effect reduction is achieved | 30 nm | graphene layer |
Temperature | 150–600 °C | — |
Thickness | ≥ 0.5 nm | — |