PROCESS OF FABRICATING HIGH EFFICIENCY, HIGH LINEARITY N-POLAR GALLIUM-NITRIDE (GaN) TRANSISTORS

Xing Gu

Patent

Atlas literature

Patent

US 10,749,009

PROCESS OF FABRICATING HIGH EFFICIENCY, HIGH LINEARITY N-POLAR GALLIUM-NITRIDE (GaN) TRANSISTORS

Xing Gu

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

2 independent · 14 dependent

1
IndependentGaNSiCGaNmetal source contact/metal drain contactN-polar GaN HEMT (method fabrication target)
A method of fabricating a semiconductor device comprising: forming a gallium-nitride (GaN) buﬀer on a silicon-carbide (SiC) substrate; forming a ﬁrst regrowth mask comprising a source access region, a drain region, and at least one channel region on the GaN buﬀer; forming a high electron mobility transistor (HEMT) structure on the GaN buﬀer in the source access region, the drain region, and the at least one channel region; forming an undoped GaN layer over the HEMT structure in the source access region and the drain region; forming a metal source contact on the undoped GaN layer in the source access region and a metal drain contact on the drain region; and forming a self-aligned gate over the at least one channel region. Original
1. 2
  Dependent← claim 1GaNSiCAlN
  The method of claim 1, wherein forming the GaN buﬀer further comprises: forming an aluminum-nitride (A l N) nucleation layer on a carbon face of the SiC substrate; and growing the GaN buﬀer on the A l N nucleation layer. Original
2. 10
  Dependent← claim 1GaN
  The method of claim 1, wherein: forming the GaN buﬀer further comprises forming a planar surface of the GaN buﬀer having a longitudinal axis in a ﬁrst direction; and patterning the ﬁrst regrowth mask comprises: removing the ﬁrst regrowth mask in the so u rce access region to expose a ﬁrst portion of the planar surface of the GaN b u ﬀer having a ﬁrst width extending in a second direction orthogonal to the ﬁrst direction: removing the ﬁrst regrowth mask in the drain region to expose a second portion of the planar surface of the GaN buﬀer; and removing the ﬁrst regrowth mask in the at least one channel region to expose at least one third portion of the planar surface of the GaN buﬀer having a total width in the second direction less than the ﬁrst width. Original
3. 13
  Dependent← claim 1GaN
  The method of claim 1 1, wherein: the at least one third portion of the planar surface of the GaN buﬀer extends from the source access re gio n to the drain region. Original
14
IndependentGaNSiCGaNN-polar GaN HEMT transistor device (structure claim)
A transistor device, comprising: a gallium-nitride (GaN) buﬀer form ed on a Carbon-face (C-face) of a silicon-carbide (SiC) substrate: a high electron mobility transistor (H EMT) structure on a Nitrogen-face (N-face) of the GaN buﬀer, the HEMT structure comprising: a source access region having a ﬁrst width; a drain region; and a plurality of channel regions isolated from each other and each providing a controlled conduction channel extending between the source access region and the drain region; an undoped GaN layer on the HEMT structure in the source access region and the drain region; a gate extending over the plurality of channel regions to control conduction in the plurality of channel regions; a source contact coupled to the source access region; and a drain contact coupled to the drain region. Withdrawn
1. 15
  Dependent← claim 14GaNGaN:SiAlGaN:SiAlGaNAlNGaNN-polar GaN HEMT transistor device (structure claim)
  The transistor device of claim 14, wherein the HEMT structure further comprises: a doped GaN layer doped with silicon (Si) and disposed on the GaN buﬀer; a doped aluminum-gallium-nitride (AlGaN) layer doped with Si and disposed on the doped GaN layer; an undoped AlGaN layer disposed on the doped AlGaN layer; an aluminum-nitride (A l N) insert disposed on the undoped AlGaN layer; and a GaN channel layer disposed on the A l N insert. Withdrawn
2. 16
  Dependent← claim 14GaN:N+N-polar GaN HEMT transistor device (structure claim)
  The transistor device of claim 14, further comprising: an N+ doped GaN layer on the HEMT structure between the undoped GaN layer and the source contact in the source access region and between the undoped GaN layer and the drain contact in the drain region. Withdrawn

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

N-polar GaN HEMT (method fabrication target)

GaNaccess region cap

GaNchannel

AlNAlN insert

AlGaNundoped AlGaN sublayer

AlGaN:Sidoped AlGaN sublayer

GaN:Sidoped GaN sublayer

Materials

Materials described outside the worked examples.

GaN buffer

GaN

Buffer Layer

Access Region LayerChannel Layer

silicon carbide substrate

SiC

Substrate

Process steps

Additional fabrication and treatment steps described in the patent.

Selective Area Regrowth

Step 1

Process details

doping:Si intentional doping in HEMT structure to suppress leakage

gate type:self-aligned gate

regrowth face:Nitrogen-face (N-face) of GaN buffer

substrate face:Carbon-face (C-face) of SiC

nucleation layer:

Why these are connected

Related documents with shared materials, methods, properties, or citations.

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