Patent
US 10,192,971Polymer on Graphene
Jody G. Redepenning
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,192,971Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(d) is a graph showing cyclic voltammetry of poly(phenylene oxide) deposition on a graphene device. [024] FIG. l (e) show optical microscopy images of a …
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 3(a) is an atomic force microscopy image of a graphene layer covered by a layer of poly(phenylene oxide) that has holes. [032]
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIG. 5(d) is a graph showing a comparison of resistivity plots for a double- gated graphene FET measured as a function of the VTG with V BG = 0, and measured …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 7B is a graph showing a comparison of the poly(phenylene oxide) films prepared from the aqueous solution containing 50 mM phenol and 0.5 M H₂S O 4 with 180 …
FIG. 8 is a graph showing cyclic voltammetry characterization of the poly(phenylene oxide) film grown on a gold wafer before and after annealing. [057]
FIGS. 9(a) to 9(e) show optical images and transfer characteristics for 5 devices before and after poly(phenylene oxide) deposition. [058]
FIG. 10 is a graph showing a Raman spectrum of a single layer graphene on Si/Si₀ 2 wafer using chemical vapor deposition. [060]
FIG. 11 is a flow diagram of a process for fabricating a top-gated graphene field effect transistor. [061]
FIG. 12 is a flow diagram of a process for forming a layer of polymer on a two- dimensional material.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor comprising: a substrate; a layer of graphene on the substrate; a layer of dielectric polymer comprising poly(phenylene oxide) on the graphene layer; and a top gate above the polymer. Original
The transistor of claim 1 in which the graphene layer is patterned to form a channel, and the transistor further comprises drain and source electrodes that are electrically coupled to the graphene. Original
The transistor of claim 1, comprising a layer of second dielectric material on the dielectric polymer layer, the second dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer. Original
The transistor of claim 1 in which the dielectric polymer layer has a thickness that is less than 10 nm. Original
The graphene transistor of claim 1 in which the top gate comprises a conducting polymer. Previously presented
The graphene transistor of claim 1 in which the top gate comprises poly(3,4-ethylenedioxythiophene) (PEDOT). Previously presented
An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate; and a layer of polymer on the layer of two-dimensional material, the polymer comprising poly(phenylene oxide). Previously presented
The apparatus of claim 5 in which the two-dimensional material comprises graphene. Original
The apparatus of claim 5 in which the polymer layer has a thickness in a range between 500 nm to 1 pm. Original
The apparatus of claim 5 in which the polymer layer has a thickness in a range from 100 nm to 500 nm. Original
The apparatus of claim 5 in which the polymer layer has a thickness in a range from 10 nm to 100 nm. Original
The apparatus of claim 5 in which the polymer layer has a thickness less than 10 nm. Original
The apparatus of claim 5 in which the two-dimensional material comprises phosphorene. Original
The apparatus of claim 5, comprising a layer of dielectric material on the polymer layer, the dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer layer. Previously presented
An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate, in which the two-dimensional material is at least one of a conducting or a semiconducting material; and a dielectric polymer formed on the layer of two-dimensional material in which the dielectric polymer comprises poly(phenylene oxide). Previously presented
The apparatus of claim 17 in which the two-dimensional material comprises graphene. Previously presented
The apparatus of claim 17 in which the two-dimensional material comprises phosphorene. Previously presented
The apparatus of claim 17, comprising a layer of dielectric material on the polymer layer, the dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer layer. Previously presented
Canceled
An organic flexible electronic device comprising: a substrate; First Named Inventor Jody G. Redepenning Attorney Docket: 24742-0079002/2162-03 (US) a layer of graphene on the substrate; a layer of dielectric polymer comprising poly(phenylene oxide) on the graphene layer; a layer of second dielectric material on the layer of dielectric polymer, the second dielectric materials having a dielectric constant that is higher than the dielectric constant of the polymer; and a top gate above the layer of second dielectric material, in which the top gate comprises a conducting polymer. Previously presented
The organic flexible electronic device of claim 25 in which the top gate comprises poly(3,4-ethylenedioxythiophene) (PEDOT). Previously presented
The apparatus of claim 25 in which the layer of graphene comprises a monolayer of graphene. Previously presented
Canceled
Canceled
An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate, in which the two-dimensional material is at least one of a conducting or a semiconducting material, and in which the two- dimensional material comprises phosphorene; and a dielectric polymer formed on the layer of two-dimensional material by applying an electrochemical deposition process to deposit the dielectric polymer on the two-dimensional material, in which a rate of deposition of the dielectric polymer at a given location of the two- dimensional material decreases as a thickness of the dielectric polymer layer increases. Currently amended
The apparatus of claim 30 in which the dielectric polymer comprises poly(phenylene oxide). Previously presented
The apparatus of claim 30 in which the two-dimensional material comprises graphene. Previously presented
The apparatus of claim 30, comprising a layer of dielectric material on the polymer layer, the dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer layer. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
top-gated graphene field-effect transistor
two-dimensional material apparatus with dielectric polymer
Materials described outside the worked examples.
graphene
poly(phenylene oxide)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(d) is a graph showing cyclic voltammetry of poly(phenylene oxide) deposition on a graphene device. [024] FIG. l (e) show optical microscopy images of a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0.1–0.9 V | — |
Voltage |
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Patent
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US 10,192,971Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(d) is a graph showing cyclic voltammetry of poly(phenylene oxide) deposition on a graphene device. [024] FIG. l (e) show optical microscopy images of a …
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 3(a) is an atomic force microscopy image of a graphene layer covered by a layer of poly(phenylene oxide) that has holes. [032]
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIG. 5(d) is a graph showing a comparison of resistivity plots for a double- gated graphene FET measured as a function of the VTG with V BG = 0, and measured …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 7B is a graph showing a comparison of the poly(phenylene oxide) films prepared from the aqueous solution containing 50 mM phenol and 0.5 M H₂S O 4 with 180 …
FIG. 8 is a graph showing cyclic voltammetry characterization of the poly(phenylene oxide) film grown on a gold wafer before and after annealing. [057]
FIGS. 9(a) to 9(e) show optical images and transfer characteristics for 5 devices before and after poly(phenylene oxide) deposition. [058]
FIG. 10 is a graph showing a Raman spectrum of a single layer graphene on Si/Si₀ 2 wafer using chemical vapor deposition. [060]
FIG. 11 is a flow diagram of a process for fabricating a top-gated graphene field effect transistor. [061]
FIG. 12 is a flow diagram of a process for forming a layer of polymer on a two- dimensional material.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor comprising: a substrate; a layer of graphene on the substrate; a layer of dielectric polymer comprising poly(phenylene oxide) on the graphene layer; and a top gate above the polymer. Original
The transistor of claim 1 in which the graphene layer is patterned to form a channel, and the transistor further comprises drain and source electrodes that are electrically coupled to the graphene. Original
The transistor of claim 1, comprising a layer of second dielectric material on the dielectric polymer layer, the second dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer. Original
The transistor of claim 1 in which the dielectric polymer layer has a thickness that is less than 10 nm. Original
The graphene transistor of claim 1 in which the top gate comprises a conducting polymer. Previously presented
The graphene transistor of claim 1 in which the top gate comprises poly(3,4-ethylenedioxythiophene) (PEDOT). Previously presented
An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate; and a layer of polymer on the layer of two-dimensional material, the polymer comprising poly(phenylene oxide). Previously presented
The apparatus of claim 5 in which the two-dimensional material comprises graphene. Original
The apparatus of claim 5 in which the polymer layer has a thickness in a range between 500 nm to 1 pm. Original
The apparatus of claim 5 in which the polymer layer has a thickness in a range from 100 nm to 500 nm. Original
The apparatus of claim 5 in which the polymer layer has a thickness in a range from 10 nm to 100 nm. Original
The apparatus of claim 5 in which the polymer layer has a thickness less than 10 nm. Original
The apparatus of claim 5 in which the two-dimensional material comprises phosphorene. Original
The apparatus of claim 5, comprising a layer of dielectric material on the polymer layer, the dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer layer. Previously presented
An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate, in which the two-dimensional material is at least one of a conducting or a semiconducting material; and a dielectric polymer formed on the layer of two-dimensional material in which the dielectric polymer comprises poly(phenylene oxide). Previously presented
The apparatus of claim 17 in which the two-dimensional material comprises graphene. Previously presented
The apparatus of claim 17 in which the two-dimensional material comprises phosphorene. Previously presented
The apparatus of claim 17, comprising a layer of dielectric material on the polymer layer, the dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer layer. Previously presented
Canceled
An organic flexible electronic device comprising: a substrate; First Named Inventor Jody G. Redepenning Attorney Docket: 24742-0079002/2162-03 (US) a layer of graphene on the substrate; a layer of dielectric polymer comprising poly(phenylene oxide) on the graphene layer; a layer of second dielectric material on the layer of dielectric polymer, the second dielectric materials having a dielectric constant that is higher than the dielectric constant of the polymer; and a top gate above the layer of second dielectric material, in which the top gate comprises a conducting polymer. Previously presented
The organic flexible electronic device of claim 25 in which the top gate comprises poly(3,4-ethylenedioxythiophene) (PEDOT). Previously presented
The apparatus of claim 25 in which the layer of graphene comprises a monolayer of graphene. Previously presented
Canceled
Canceled
An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate, in which the two-dimensional material is at least one of a conducting or a semiconducting material, and in which the two- dimensional material comprises phosphorene; and a dielectric polymer formed on the layer of two-dimensional material by applying an electrochemical deposition process to deposit the dielectric polymer on the two-dimensional material, in which a rate of deposition of the dielectric polymer at a given location of the two- dimensional material decreases as a thickness of the dielectric polymer layer increases. Currently amended
The apparatus of claim 30 in which the dielectric polymer comprises poly(phenylene oxide). Previously presented
The apparatus of claim 30 in which the two-dimensional material comprises graphene. Previously presented
The apparatus of claim 30, comprising a layer of dielectric material on the polymer layer, the dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer layer. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
top-gated graphene field-effect transistor
two-dimensional material apparatus with dielectric polymer
Materials described outside the worked examples.
graphene
poly(phenylene oxide)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(d) is a graph showing cyclic voltammetry of poly(phenylene oxide) deposition on a graphene device. [024] FIG. l (e) show optical microscopy images of a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0.1–0.9 V | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 10,192,971Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(d) is a graph showing cyclic voltammetry of poly(phenylene oxide) deposition on a graphene device. [024] FIG. l (e) show optical microscopy images of a …
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 3(a) is an atomic force microscopy image of a graphene layer covered by a layer of poly(phenylene oxide) that has holes. [032]
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIG. 5(d) is a graph showing a comparison of resistivity plots for a double- gated graphene FET measured as a function of the VTG with V BG = 0, and measured …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 7B is a graph showing a comparison of the poly(phenylene oxide) films prepared from the aqueous solution containing 50 mM phenol and 0.5 M H₂S O 4 with 180 …
FIG. 8 is a graph showing cyclic voltammetry characterization of the poly(phenylene oxide) film grown on a gold wafer before and after annealing. [057]
FIGS. 9(a) to 9(e) show optical images and transfer characteristics for 5 devices before and after poly(phenylene oxide) deposition. [058]
FIG. 10 is a graph showing a Raman spectrum of a single layer graphene on Si/Si₀ 2 wafer using chemical vapor deposition. [060]
FIG. 11 is a flow diagram of a process for fabricating a top-gated graphene field effect transistor. [061]
FIG. 12 is a flow diagram of a process for forming a layer of polymer on a two- dimensional material.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor comprising: a substrate; a layer of graphene on the substrate; a layer of dielectric polymer comprising poly(phenylene oxide) on the graphene layer; and a top gate above the polymer. Original
The transistor of claim 1 in which the graphene layer is patterned to form a channel, and the transistor further comprises drain and source electrodes that are electrically coupled to the graphene. Original
The transistor of claim 1, comprising a layer of second dielectric material on the dielectric polymer layer, the second dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer. Original
The transistor of claim 1 in which the dielectric polymer layer has a thickness that is less than 10 nm. Original
The graphene transistor of claim 1 in which the top gate comprises a conducting polymer. Previously presented
The graphene transistor of claim 1 in which the top gate comprises poly(3,4-ethylenedioxythiophene) (PEDOT). Previously presented
An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate; and a layer of polymer on the layer of two-dimensional material, the polymer comprising poly(phenylene oxide). Previously presented
The apparatus of claim 5 in which the two-dimensional material comprises graphene. Original
The apparatus of claim 5 in which the polymer layer has a thickness in a range between 500 nm to 1 pm. Original
The apparatus of claim 5 in which the polymer layer has a thickness in a range from 100 nm to 500 nm. Original
The apparatus of claim 5 in which the polymer layer has a thickness in a range from 10 nm to 100 nm. Original
The apparatus of claim 5 in which the polymer layer has a thickness less than 10 nm. Original
The apparatus of claim 5 in which the two-dimensional material comprises phosphorene. Original
The apparatus of claim 5, comprising a layer of dielectric material on the polymer layer, the dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer layer. Previously presented
An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate, in which the two-dimensional material is at least one of a conducting or a semiconducting material; and a dielectric polymer formed on the layer of two-dimensional material in which the dielectric polymer comprises poly(phenylene oxide). Previously presented
The apparatus of claim 17 in which the two-dimensional material comprises graphene. Previously presented
The apparatus of claim 17 in which the two-dimensional material comprises phosphorene. Previously presented
The apparatus of claim 17, comprising a layer of dielectric material on the polymer layer, the dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer layer. Previously presented
Canceled
An organic flexible electronic device comprising: a substrate; First Named Inventor Jody G. Redepenning Attorney Docket: 24742-0079002/2162-03 (US) a layer of graphene on the substrate; a layer of dielectric polymer comprising poly(phenylene oxide) on the graphene layer; a layer of second dielectric material on the layer of dielectric polymer, the second dielectric materials having a dielectric constant that is higher than the dielectric constant of the polymer; and a top gate above the layer of second dielectric material, in which the top gate comprises a conducting polymer. Previously presented
The organic flexible electronic device of claim 25 in which the top gate comprises poly(3,4-ethylenedioxythiophene) (PEDOT). Previously presented
The apparatus of claim 25 in which the layer of graphene comprises a monolayer of graphene. Previously presented
Canceled
Canceled
An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate, in which the two-dimensional material is at least one of a conducting or a semiconducting material, and in which the two- dimensional material comprises phosphorene; and a dielectric polymer formed on the layer of two-dimensional material by applying an electrochemical deposition process to deposit the dielectric polymer on the two-dimensional material, in which a rate of deposition of the dielectric polymer at a given location of the two- dimensional material decreases as a thickness of the dielectric polymer layer increases. Currently amended
The apparatus of claim 30 in which the dielectric polymer comprises poly(phenylene oxide). Previously presented
The apparatus of claim 30 in which the two-dimensional material comprises graphene. Previously presented
The apparatus of claim 30, comprising a layer of dielectric material on the polymer layer, the dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer layer. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
top-gated graphene field-effect transistor
two-dimensional material apparatus with dielectric polymer
Materials described outside the worked examples.
graphene
poly(phenylene oxide)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(d) is a graph showing cyclic voltammetry of poly(phenylene oxide) deposition on a graphene device. [024] FIG. l (e) show optical microscopy images of a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0.1–0.9 V | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,192,971Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1(d) is a graph showing cyclic voltammetry of poly(phenylene oxide) deposition on a graphene device. [024] FIG. l (e) show optical microscopy images of a …
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 3(a) is an atomic force microscopy image of a graphene layer covered by a layer of poly(phenylene oxide) that has holes. [032]
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIG. 5(d) is a graph showing a comparison of resistivity plots for a double- gated graphene FET measured as a function of the VTG with V BG = 0, and measured …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 7B is a graph showing a comparison of the poly(phenylene oxide) films prepared from the aqueous solution containing 50 mM phenol and 0.5 M H₂S O 4 with 180 …
FIG. 8 is a graph showing cyclic voltammetry characterization of the poly(phenylene oxide) film grown on a gold wafer before and after annealing. [057]
FIGS. 9(a) to 9(e) show optical images and transfer characteristics for 5 devices before and after poly(phenylene oxide) deposition. [058]
FIG. 10 is a graph showing a Raman spectrum of a single layer graphene on Si/Si₀ 2 wafer using chemical vapor deposition. [060]
FIG. 11 is a flow diagram of a process for fabricating a top-gated graphene field effect transistor. [061]
FIG. 12 is a flow diagram of a process for forming a layer of polymer on a two- dimensional material.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene transistor comprising: a substrate; a layer of graphene on the substrate; a layer of dielectric polymer comprising poly(phenylene oxide) on the graphene layer; and a top gate above the polymer. Original
The transistor of claim 1 in which the graphene layer is patterned to form a channel, and the transistor further comprises drain and source electrodes that are electrically coupled to the graphene. Original
The transistor of claim 1, comprising a layer of second dielectric material on the dielectric polymer layer, the second dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer. Original
The transistor of claim 1 in which the dielectric polymer layer has a thickness that is less than 10 nm. Original
The graphene transistor of claim 1 in which the top gate comprises a conducting polymer. Previously presented
The graphene transistor of claim 1 in which the top gate comprises poly(3,4-ethylenedioxythiophene) (PEDOT). Previously presented
An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate; and a layer of polymer on the layer of two-dimensional material, the polymer comprising poly(phenylene oxide). Previously presented
The apparatus of claim 5 in which the two-dimensional material comprises graphene. Original
The apparatus of claim 5 in which the polymer layer has a thickness in a range between 500 nm to 1 pm. Original
The apparatus of claim 5 in which the polymer layer has a thickness in a range from 100 nm to 500 nm. Original
The apparatus of claim 5 in which the polymer layer has a thickness in a range from 10 nm to 100 nm. Original
The apparatus of claim 5 in which the polymer layer has a thickness less than 10 nm. Original
The apparatus of claim 5 in which the two-dimensional material comprises phosphorene. Original
The apparatus of claim 5, comprising a layer of dielectric material on the polymer layer, the dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer layer. Previously presented
An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate, in which the two-dimensional material is at least one of a conducting or a semiconducting material; and a dielectric polymer formed on the layer of two-dimensional material in which the dielectric polymer comprises poly(phenylene oxide). Previously presented
The apparatus of claim 17 in which the two-dimensional material comprises graphene. Previously presented
The apparatus of claim 17 in which the two-dimensional material comprises phosphorene. Previously presented
The apparatus of claim 17, comprising a layer of dielectric material on the polymer layer, the dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer layer. Previously presented
Canceled
An organic flexible electronic device comprising: a substrate; First Named Inventor Jody G. Redepenning Attorney Docket: 24742-0079002/2162-03 (US) a layer of graphene on the substrate; a layer of dielectric polymer comprising poly(phenylene oxide) on the graphene layer; a layer of second dielectric material on the layer of dielectric polymer, the second dielectric materials having a dielectric constant that is higher than the dielectric constant of the polymer; and a top gate above the layer of second dielectric material, in which the top gate comprises a conducting polymer. Previously presented
The organic flexible electronic device of claim 25 in which the top gate comprises poly(3,4-ethylenedioxythiophene) (PEDOT). Previously presented
The apparatus of claim 25 in which the layer of graphene comprises a monolayer of graphene. Previously presented
Canceled
Canceled
An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate, in which the two-dimensional material is at least one of a conducting or a semiconducting material, and in which the two- dimensional material comprises phosphorene; and a dielectric polymer formed on the layer of two-dimensional material by applying an electrochemical deposition process to deposit the dielectric polymer on the two-dimensional material, in which a rate of deposition of the dielectric polymer at a given location of the two- dimensional material decreases as a thickness of the dielectric polymer layer increases. Currently amended
The apparatus of claim 30 in which the dielectric polymer comprises poly(phenylene oxide). Previously presented
The apparatus of claim 30 in which the two-dimensional material comprises graphene. Previously presented
The apparatus of claim 30, comprising a layer of dielectric material on the polymer layer, the dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer layer. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
top-gated graphene field-effect transistor
two-dimensional material apparatus with dielectric polymer
Materials described outside the worked examples.
graphene
poly(phenylene oxide)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1(d) is a graph showing cyclic voltammetry of poly(phenylene oxide) deposition on a graphene device. [024] FIG. l (e) show optical microscopy images of a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0.1–0.9 V | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
organic flexible electronic device
high-k dielectric material
two-dimensional material
phosphorene
conducting polymer
poly(3,4-ethylenedioxythiophene)
phenol
C₆H₅OH
sulfuric acid
H₂SO₄
FIG. 1(d) is a graph showing cyclic voltammetry of poly(phenylene oxide) deposition on a graphene device. [024] FIG. l (e) show optical microscopy images of a …
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 3(a) is an atomic force microscopy image of a graphene layer covered by a layer of poly(phenylene oxide) that has holes. [032]
FIG. 3(a) is an atomic force microscopy image of a graphene layer covered by a layer of poly(phenylene oxide) that has holes. [032]
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIG. 5(d) is a graph showing a comparison of resistivity plots for a double- gated graphene FET measured as a function of the VTG with V BG = 0, and measured …
FIG. 5(d) is a graph showing a comparison of resistivity plots for a double- gated graphene FET measured as a function of the VTG with V BG = 0, and measured …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 7B is a graph showing a comparison of the poly(phenylene oxide) films prepared from the aqueous solution containing 50 mM phenol and 0.5 M H₂S O 4 with 180 …
FIG. 8 is a graph showing cyclic voltammetry characterization of the poly(phenylene oxide) film grown on a gold wafer before and after annealing. [057]
FIGS. 9(a) to 9(e) show optical images and transfer characteristics for 5 devices before and after poly(phenylene oxide) deposition. [058]
FIGS. 9(a) to 9(e) show optical images and transfer characteristics for 5 devices before and after poly(phenylene oxide) deposition. [058]
FIG. 10 is a graph showing a Raman spectrum of a single layer graphene on Si/Si₀ 2 wafer using chemical vapor deposition. [060]
FIG. 10 is a graph showing a Raman spectrum of a single layer graphene on Si/Si₀ 2 wafer using chemical vapor deposition. [060]
FIG. 11 is a flow diagram of a process for fabricating a top-gated graphene field effect transistor. [061]
| 0–1 V |
| — |
Voltage | 0–1.1 V | — |
Voltage | 0–1.2 V | — |
Voltage | 0.5–1.2 V | — |
Voltage | 0.9–1 V | — |
Temperature | 2–7 k | — |
Voltage | 50–50 V | — |
Voltage | 0.15–0.2 V | — |
Voltage | 10–50 V | — |
Pressure | 0.000001 torr | — |
Thickness | ≤ 10 nm | — |
Pressure | ≤ 20 mTorr | — |
Voltage | ≤ 0.5 V | — |
Thickness | ≤ 4 nm | — |
Thickness | 100–500 nm | — |
Thickness | 10–100 nm | — |
Voltage | 0.5–1.5 V | — |
Voltage | 0–0.5 V | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 3 nm | — |
organic flexible electronic device
high-k dielectric material
two-dimensional material
phosphorene
conducting polymer
poly(3,4-ethylenedioxythiophene)
phenol
C₆H₅OH
sulfuric acid
H₂SO₄
FIG. 1(d) is a graph showing cyclic voltammetry of poly(phenylene oxide) deposition on a graphene device. [024] FIG. l (e) show optical microscopy images of a …
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 3(a) is an atomic force microscopy image of a graphene layer covered by a layer of poly(phenylene oxide) that has holes. [032]
FIG. 3(a) is an atomic force microscopy image of a graphene layer covered by a layer of poly(phenylene oxide) that has holes. [032]
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIG. 5(d) is a graph showing a comparison of resistivity plots for a double- gated graphene FET measured as a function of the VTG with V BG = 0, and measured …
FIG. 5(d) is a graph showing a comparison of resistivity plots for a double- gated graphene FET measured as a function of the VTG with V BG = 0, and measured …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 7B is a graph showing a comparison of the poly(phenylene oxide) films prepared from the aqueous solution containing 50 mM phenol and 0.5 M H₂S O 4 with 180 …
FIG. 8 is a graph showing cyclic voltammetry characterization of the poly(phenylene oxide) film grown on a gold wafer before and after annealing. [057]
FIGS. 9(a) to 9(e) show optical images and transfer characteristics for 5 devices before and after poly(phenylene oxide) deposition. [058]
FIGS. 9(a) to 9(e) show optical images and transfer characteristics for 5 devices before and after poly(phenylene oxide) deposition. [058]
FIG. 10 is a graph showing a Raman spectrum of a single layer graphene on Si/Si₀ 2 wafer using chemical vapor deposition. [060]
FIG. 10 is a graph showing a Raman spectrum of a single layer graphene on Si/Si₀ 2 wafer using chemical vapor deposition. [060]
FIG. 11 is a flow diagram of a process for fabricating a top-gated graphene field effect transistor. [061]
| 0–1 V |
| — |
Voltage | 0–1.1 V | — |
Voltage | 0–1.2 V | — |
Voltage | 0.5–1.2 V | — |
Voltage | 0.9–1 V | — |
Temperature | 2–7 k | — |
Voltage | 50–50 V | — |
Voltage | 0.15–0.2 V | — |
Voltage | 10–50 V | — |
Pressure | 0.000001 torr | — |
Thickness | ≤ 10 nm | — |
Pressure | ≤ 20 mTorr | — |
Voltage | ≤ 0.5 V | — |
Thickness | ≤ 4 nm | — |
Thickness | 100–500 nm | — |
Thickness | 10–100 nm | — |
Voltage | 0.5–1.5 V | — |
Voltage | 0–0.5 V | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 3 nm | — |
organic flexible electronic device
high-k dielectric material
two-dimensional material
phosphorene
conducting polymer
poly(3,4-ethylenedioxythiophene)
phenol
C₆H₅OH
sulfuric acid
H₂SO₄
FIG. 1(d) is a graph showing cyclic voltammetry of poly(phenylene oxide) deposition on a graphene device. [024] FIG. l (e) show optical microscopy images of a …
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 3(a) is an atomic force microscopy image of a graphene layer covered by a layer of poly(phenylene oxide) that has holes. [032]
FIG. 3(a) is an atomic force microscopy image of a graphene layer covered by a layer of poly(phenylene oxide) that has holes. [032]
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIG. 5(d) is a graph showing a comparison of resistivity plots for a double- gated graphene FET measured as a function of the VTG with V BG = 0, and measured …
FIG. 5(d) is a graph showing a comparison of resistivity plots for a double- gated graphene FET measured as a function of the VTG with V BG = 0, and measured …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 7B is a graph showing a comparison of the poly(phenylene oxide) films prepared from the aqueous solution containing 50 mM phenol and 0.5 M H₂S O 4 with 180 …
FIG. 8 is a graph showing cyclic voltammetry characterization of the poly(phenylene oxide) film grown on a gold wafer before and after annealing. [057]
FIGS. 9(a) to 9(e) show optical images and transfer characteristics for 5 devices before and after poly(phenylene oxide) deposition. [058]
FIGS. 9(a) to 9(e) show optical images and transfer characteristics for 5 devices before and after poly(phenylene oxide) deposition. [058]
FIG. 10 is a graph showing a Raman spectrum of a single layer graphene on Si/Si₀ 2 wafer using chemical vapor deposition. [060]
FIG. 10 is a graph showing a Raman spectrum of a single layer graphene on Si/Si₀ 2 wafer using chemical vapor deposition. [060]
FIG. 11 is a flow diagram of a process for fabricating a top-gated graphene field effect transistor. [061]
| 0–1 V |
| — |
Voltage | 0–1.1 V | — |
Voltage | 0–1.2 V | — |
Voltage | 0.5–1.2 V | — |
Voltage | 0.9–1 V | — |
Temperature | 2–7 k | — |
Voltage | 50–50 V | — |
Voltage | 0.15–0.2 V | — |
Voltage | 10–50 V | — |
Pressure | 0.000001 torr | — |
Thickness | ≤ 10 nm | — |
Pressure | ≤ 20 mTorr | — |
Voltage | ≤ 0.5 V | — |
Thickness | ≤ 4 nm | — |
Thickness | 100–500 nm | — |
Thickness | 10–100 nm | — |
Voltage | 0.5–1.5 V | — |
Voltage | 0–0.5 V | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 3 nm | — |
organic flexible electronic device
high-k dielectric material
two-dimensional material
phosphorene
conducting polymer
poly(3,4-ethylenedioxythiophene)
phenol
C₆H₅OH
sulfuric acid
H₂SO₄
FIG. 1(d) is a graph showing cyclic voltammetry of poly(phenylene oxide) deposition on a graphene device. [024] FIG. l (e) show optical microscopy images of a …
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 2(a) is an atomic force microscopy image of a graphene field effect transistor device after fabrication of source and drain electrodes. [027]
FIG. 3(a) is an atomic force microscopy image of a graphene layer covered by a layer of poly(phenylene oxide) that has holes. [032]
FIG. 3(a) is an atomic force microscopy image of a graphene layer covered by a layer of poly(phenylene oxide) that has holes. [032]
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIGS. 4(e) and 4(f) are atomic force microscopy images of the device channel and the isolated graphene patch before and after, respectively, poly(phenylene …
FIG. 5(d) is a graph showing a comparison of resistivity plots for a double- gated graphene FET measured as a function of the VTG with V BG = 0, and measured …
FIG. 5(d) is a graph showing a comparison of resistivity plots for a double- gated graphene FET measured as a function of the VTG with V BG = 0, and measured …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 6(g) is a graph showing a comparison of transfer characteristics for one double-gated graphene FET in the array measured when only one gate voltage (top …
FIG. 7B is a graph showing a comparison of the poly(phenylene oxide) films prepared from the aqueous solution containing 50 mM phenol and 0.5 M H₂S O 4 with 180 …
FIG. 8 is a graph showing cyclic voltammetry characterization of the poly(phenylene oxide) film grown on a gold wafer before and after annealing. [057]
FIGS. 9(a) to 9(e) show optical images and transfer characteristics for 5 devices before and after poly(phenylene oxide) deposition. [058]
FIGS. 9(a) to 9(e) show optical images and transfer characteristics for 5 devices before and after poly(phenylene oxide) deposition. [058]
FIG. 10 is a graph showing a Raman spectrum of a single layer graphene on Si/Si₀ 2 wafer using chemical vapor deposition. [060]
FIG. 10 is a graph showing a Raman spectrum of a single layer graphene on Si/Si₀ 2 wafer using chemical vapor deposition. [060]
FIG. 11 is a flow diagram of a process for fabricating a top-gated graphene field effect transistor. [061]
| 0–1 V |
| — |
Voltage | 0–1.1 V | — |
Voltage | 0–1.2 V | — |
Voltage | 0.5–1.2 V | — |
Voltage | 0.9–1 V | — |
Temperature | 2–7 k | — |
Voltage | 50–50 V | — |
Voltage | 0.15–0.2 V | — |
Voltage | 10–50 V | — |
Pressure | 0.000001 torr | — |
Thickness | ≤ 10 nm | — |
Pressure | ≤ 20 mTorr | — |
Voltage | ≤ 0.5 V | — |
Thickness | ≤ 4 nm | — |
Thickness | 100–500 nm | — |
Thickness | 10–100 nm | — |
Voltage | 0.5–1.5 V | — |
Voltage | 0–0.5 V | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 3 nm | — |