Patent
US 10,720,506METHOD OF MANUFACTURING GATE STRUCTURE FOR GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR
Chu-Kuang Liu
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
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US 10,720,506Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A, a channel layer 102, a barrier layer 104, a doped gallium nitride layer 106, and an undoped gallium nitride layer 108 are formed orderly on a …
FIG. 2 B, after the remaining photoresist 118 is removed, an entire gate metal layer 120 is formed on the substrate 100, covering the insulating layer 11 4a, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing a gate structure for a gallium nitride high electron mobility transistor (HEMT), comprising: forming a channel layer, a barrier layer, a doped gallium nitride layer, and an undoped gallium nitride layer sequentially on a substrate; forming an insulating layer on the undoped gallium nitride layer; removing a portion of the insulating layer to form a trench; forming a gate metal layer on the substrate to cover the insulating layer and the trench; forming a mask layer aligned with the trench on the gate metal layer, and the mask layer partially overlaps the insulating layer; removing the exposed gate metal layer and the underlying insulating layer, the undoped gallium nitride layer, and the doped gallium nitride layer by using the mask layer as an etching mask; and removing the mask layer.
The manufacturing method according to claim 1, wherein an overlapping area of the mask layer and the insulating layer accounts for 50% or less of an area of the mask layer.
The manufacturing method according to claim 1, further comprising removing the exposed undoped gallium nitride layer to deepen the trench and expose the doped gallium nitride layer after removing the portion of the insulating layer.
The manufacturing method according to claim 1, wherein the method of forming the channel layer, the barrier layer, the doped gallium nitride layer, and the undoped gallium nitride layer comprises metal organic chemical vapor deposition.
The manufacturing method according to claim 1, wherein the method of forming the insulating layer comprises metal organic chemical vapor deposition or low pressure chemical vapor deposition.
The manufacturing method according to claim 1, before forming the channel layer further comprising: forming a first buffer layer on the substrate; and forming a second buffer layer on the first buffer layer, wherein a lattice of the second buffer layer is more matching with the channel layer than a lattice of the first buffer layer.
The manufacturing method according to claim 1, further comprising forming a passivation layer completely covering the gate metal layer, the insulating layer, the undoped gallium nitride layer, the doped gallium nitride layer, and the barrier layer after removing the mask layer.
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride high electron mobility transistor (GaN HEMT) gate structure
Materials described outside the worked examples.
gallium nitride channel layer
GaN
barrier layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 200 Å | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,720,506Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A, a channel layer 102, a barrier layer 104, a doped gallium nitride layer 106, and an undoped gallium nitride layer 108 are formed orderly on a …
FIG. 2 B, after the remaining photoresist 118 is removed, an entire gate metal layer 120 is formed on the substrate 100, covering the insulating layer 11 4a, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing a gate structure for a gallium nitride high electron mobility transistor (HEMT), comprising: forming a channel layer, a barrier layer, a doped gallium nitride layer, and an undoped gallium nitride layer sequentially on a substrate; forming an insulating layer on the undoped gallium nitride layer; removing a portion of the insulating layer to form a trench; forming a gate metal layer on the substrate to cover the insulating layer and the trench; forming a mask layer aligned with the trench on the gate metal layer, and the mask layer partially overlaps the insulating layer; removing the exposed gate metal layer and the underlying insulating layer, the undoped gallium nitride layer, and the doped gallium nitride layer by using the mask layer as an etching mask; and removing the mask layer.
The manufacturing method according to claim 1, wherein an overlapping area of the mask layer and the insulating layer accounts for 50% or less of an area of the mask layer.
The manufacturing method according to claim 1, further comprising removing the exposed undoped gallium nitride layer to deepen the trench and expose the doped gallium nitride layer after removing the portion of the insulating layer.
The manufacturing method according to claim 1, wherein the method of forming the channel layer, the barrier layer, the doped gallium nitride layer, and the undoped gallium nitride layer comprises metal organic chemical vapor deposition.
The manufacturing method according to claim 1, wherein the method of forming the insulating layer comprises metal organic chemical vapor deposition or low pressure chemical vapor deposition.
The manufacturing method according to claim 1, before forming the channel layer further comprising: forming a first buffer layer on the substrate; and forming a second buffer layer on the first buffer layer, wherein a lattice of the second buffer layer is more matching with the channel layer than a lattice of the first buffer layer.
The manufacturing method according to claim 1, further comprising forming a passivation layer completely covering the gate metal layer, the insulating layer, the undoped gallium nitride layer, the doped gallium nitride layer, and the barrier layer after removing the mask layer.
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride high electron mobility transistor (GaN HEMT) gate structure
Materials described outside the worked examples.
gallium nitride channel layer
GaN
barrier layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 200 Å | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,720,506Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A, a channel layer 102, a barrier layer 104, a doped gallium nitride layer 106, and an undoped gallium nitride layer 108 are formed orderly on a …
FIG. 2 B, after the remaining photoresist 118 is removed, an entire gate metal layer 120 is formed on the substrate 100, covering the insulating layer 11 4a, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing a gate structure for a gallium nitride high electron mobility transistor (HEMT), comprising: forming a channel layer, a barrier layer, a doped gallium nitride layer, and an undoped gallium nitride layer sequentially on a substrate; forming an insulating layer on the undoped gallium nitride layer; removing a portion of the insulating layer to form a trench; forming a gate metal layer on the substrate to cover the insulating layer and the trench; forming a mask layer aligned with the trench on the gate metal layer, and the mask layer partially overlaps the insulating layer; removing the exposed gate metal layer and the underlying insulating layer, the undoped gallium nitride layer, and the doped gallium nitride layer by using the mask layer as an etching mask; and removing the mask layer.
The manufacturing method according to claim 1, wherein an overlapping area of the mask layer and the insulating layer accounts for 50% or less of an area of the mask layer.
The manufacturing method according to claim 1, further comprising removing the exposed undoped gallium nitride layer to deepen the trench and expose the doped gallium nitride layer after removing the portion of the insulating layer.
The manufacturing method according to claim 1, wherein the method of forming the channel layer, the barrier layer, the doped gallium nitride layer, and the undoped gallium nitride layer comprises metal organic chemical vapor deposition.
The manufacturing method according to claim 1, wherein the method of forming the insulating layer comprises metal organic chemical vapor deposition or low pressure chemical vapor deposition.
The manufacturing method according to claim 1, before forming the channel layer further comprising: forming a first buffer layer on the substrate; and forming a second buffer layer on the first buffer layer, wherein a lattice of the second buffer layer is more matching with the channel layer than a lattice of the first buffer layer.
The manufacturing method according to claim 1, further comprising forming a passivation layer completely covering the gate metal layer, the insulating layer, the undoped gallium nitride layer, the doped gallium nitride layer, and the barrier layer after removing the mask layer.
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride high electron mobility transistor (GaN HEMT) gate structure
Materials described outside the worked examples.
gallium nitride channel layer
GaN
barrier layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 200 Å | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,720,506Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A, a channel layer 102, a barrier layer 104, a doped gallium nitride layer 106, and an undoped gallium nitride layer 108 are formed orderly on a …
FIG. 2 B, after the remaining photoresist 118 is removed, an entire gate metal layer 120 is formed on the substrate 100, covering the insulating layer 11 4a, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing a gate structure for a gallium nitride high electron mobility transistor (HEMT), comprising: forming a channel layer, a barrier layer, a doped gallium nitride layer, and an undoped gallium nitride layer sequentially on a substrate; forming an insulating layer on the undoped gallium nitride layer; removing a portion of the insulating layer to form a trench; forming a gate metal layer on the substrate to cover the insulating layer and the trench; forming a mask layer aligned with the trench on the gate metal layer, and the mask layer partially overlaps the insulating layer; removing the exposed gate metal layer and the underlying insulating layer, the undoped gallium nitride layer, and the doped gallium nitride layer by using the mask layer as an etching mask; and removing the mask layer.
The manufacturing method according to claim 1, wherein an overlapping area of the mask layer and the insulating layer accounts for 50% or less of an area of the mask layer.
The manufacturing method according to claim 1, further comprising removing the exposed undoped gallium nitride layer to deepen the trench and expose the doped gallium nitride layer after removing the portion of the insulating layer.
The manufacturing method according to claim 1, wherein the method of forming the channel layer, the barrier layer, the doped gallium nitride layer, and the undoped gallium nitride layer comprises metal organic chemical vapor deposition.
The manufacturing method according to claim 1, wherein the method of forming the insulating layer comprises metal organic chemical vapor deposition or low pressure chemical vapor deposition.
The manufacturing method according to claim 1, before forming the channel layer further comprising: forming a first buffer layer on the substrate; and forming a second buffer layer on the first buffer layer, wherein a lattice of the second buffer layer is more matching with the channel layer than a lattice of the first buffer layer.
The manufacturing method according to claim 1, further comprising forming a passivation layer completely covering the gate metal layer, the insulating layer, the undoped gallium nitride layer, the doped gallium nitride layer, and the barrier layer after removing the mask layer.
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride high electron mobility transistor (GaN HEMT) gate structure
Materials described outside the worked examples.
gallium nitride channel layer
GaN
barrier layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 200 Å | — |
Related documents with shared materials, methods, properties, or citations.
gate metal layer
insulating layer
first buffer layer (aluminum nitride)
AlN
second buffer layer (AlGaN/GaN multistack)
aluminum gallium nitride
AlxGa₁-xN
passivation layer
silicon nitride insulating layer
Si₃N₄
aluminum oxide insulating layer
Al₂O₃
silicon oxide insulating layer
SiO₂
boron nitride insulating layer
BN
gate metal layer
insulating layer
first buffer layer (aluminum nitride)
AlN
second buffer layer (AlGaN/GaN multistack)
aluminum gallium nitride
AlxGa₁-xN
passivation layer
silicon nitride insulating layer
Si₃N₄
aluminum oxide insulating layer
Al₂O₃
silicon oxide insulating layer
SiO₂
boron nitride insulating layer
BN
gate metal layer
insulating layer
first buffer layer (aluminum nitride)
AlN
second buffer layer (AlGaN/GaN multistack)
aluminum gallium nitride
AlxGa₁-xN
passivation layer
silicon nitride insulating layer
Si₃N₄
aluminum oxide insulating layer
Al₂O₃
silicon oxide insulating layer
SiO₂
boron nitride insulating layer
BN
gate metal layer
insulating layer
first buffer layer (aluminum nitride)
AlN
second buffer layer (AlGaN/GaN multistack)
aluminum gallium nitride
AlxGa₁-xN
passivation layer
silicon nitride insulating layer
Si₃N₄
aluminum oxide insulating layer
Al₂O₃
silicon oxide insulating layer
SiO₂
boron nitride insulating layer
BN