Patent
Atlas literature
Patent
US 12,112,983 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example electrode structure for a device according to various embodiments described herein.
FIG. 2 illustrates an example method of forming the electrode structure shown in
FIG. 3 illustrates an example substrate and insulating dielectric layer according to various embodiments described herein.
FIG. 4 illustrates an example opening in the insulating dielectric layer shown in
FIG. 5 illustrates an example barrier metal layer formed over the insulating dielectric layer and the surface region of the substrate according to various …
FIG. 6 illustrates an example conducting metal layer formed over the barrier metal layer according to various embodiments described herein.
FIG. 7 illustrates an example cap metal layer formed over the conducting metal layer according to various embodi- ments described herein.
FIG. 8 illustrates an mask layer formed over the cap metal layer according to various embodiments described herein.
FIG. 9 illustrates an example electrode structure formed by etching the barrier layer, the conducting layer, and the cap metal layer around the mask layer …
FIG. 10 illustrates an example electrode structure formed after removing the mask layer according to various embodi- ments described herein.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing an electrode structure for a device, comprising: forming an insulating layer over a surface of a substrate; forming an opening in the insulating layer to expose a semiconductor material surface region of the substrate through the opening; depositing a barrier metal layer over the insulating layer and onto the semiconductor material surface region of the substrate through the opening in the insulating layer using atomic layer deposition; depositing a conducting metal layer over the barrier metal layer; depositing a cap metal layer over the conducting metal layer using sputtering; forming a cap etch photoresist layer over a region of the cap metal layer; and etching the cap metal layer, the conducting metal layer, and the barrier metal layer down to the insulating layer over an area outside of the cap etch photoresist layer.
The method according to claim 1, wherein depositing the barrier metal layer comprises depositing the barrier metal layer onto the insulating layer and onto the semicon-ductor material surface region of the substrate using atomic layer deposition.
The method according to claim 1, wherein the barrier metal layer comprises tungsten nitride.
The method according to claim 1, wherein depositing the conductive metal layer comprises sputtering the conduc-tive metal layer over the barrier metal layer.
The method according to claim 1, wherein the con-ducting metal layer comprises aluminum.
The method according to claim 1, wherein the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride.
The method according to claim 1, further comprising removing the cap etch photoresist layer.
The method according to claim 1, wherein: the substrate comprises a gallium nitride material layer; forming the opening in the insulating layer comprises exposing a surface region of the gallium nitride mate-rial layer; and depositing the barrier metal layer comprises depositing the barrier metal layer onto the surface region of the gallium nitride material layer.
A method of manufacturing an electrode structure for a device, comprising: providing a substrate comprising a gallium nitride mate-rial layer; forming an insulating layer over a surface of the gallium nitride material layer; forming an opening in the insulating layer to expose a surface region of the gallium nitride material layer through the opening; depositing a barrier metal layer over the insulating layer and onto the surface region of the gallium nitride material layer through the opening in the insulating layer using atomic layer deposition; depositing a conducting metal layer over the barrier metal layer; and depositing a cap metal layer of at least one of titanium nitride, tungsten, and tungsten nitride over the conduct-ing metal layer using sputtering.
The method according to claim 9, wherein the barrier metal layer comprises tungsten nitride.
The method according to claim 9, wherein depositing the conductive metal layer comprises sputtering the conduc-tive metal layer over the barrier metal layer.
The method according to claim 9, wherein the con-ducting metal layer comprises aluminum.
A method of manufacturing an electrode structure for a device, comprising: forming an opening in an insulating layer to expose a semiconductor material surface region of a substrate through the opening; depositing a barrier metal layer over the insulating layer and onto the semiconductor material surface region of the substrate through the opening using atomic layer deposition; depositing a conducting metal layer over the barrier metal layer using sputtering; depositing a cap metal layer over the conducting metal layer using sputtering; and etching the cap metal layer, the conducting metal layer, and the barrier metal layer down to the insulating layer over an area.
The method according to claim 13, wherein: the substrate comprises a gallium nitride material layer; forming the opening in the insulating layer comprises exposing a surface region of the gallium nitride mate-rial layer; and depositing the barrier metal layer comprises depositing the barrier metal layer onto the surface region of the gallium nitride material layer.
The method according to claim 13, wherein the conducting metal layer comprises aluminum.
The method according to claim 13, wherein the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride. 11 12
The method according to claim 13, wherein the barrier metal layer comprises tungsten nitride.
The method according to claim 13, wherein: the barrier metal layer comprises tungsten nitride; the conducting metal layer comprises aluminum; and the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride.
The method according to claim 13, wherein depositing the barrier metal layer comprises depositing the barrier metal layer onto the insulating layer and onto the semicon-ductor material surface region of the substrate using atomic layer deposition. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
electrode structure for GaN material device
Materials described outside the worked examples.
barrier metal layer
conducting metal layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 900–1025 Å | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 21
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,112,983 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example electrode structure for a device according to various embodiments described herein.
FIG. 2 illustrates an example method of forming the electrode structure shown in
FIG. 3 illustrates an example substrate and insulating dielectric layer according to various embodiments described herein.
FIG. 4 illustrates an example opening in the insulating dielectric layer shown in
FIG. 5 illustrates an example barrier metal layer formed over the insulating dielectric layer and the surface region of the substrate according to various …
FIG. 6 illustrates an example conducting metal layer formed over the barrier metal layer according to various embodiments described herein.
FIG. 7 illustrates an example cap metal layer formed over the conducting metal layer according to various embodi- ments described herein.
FIG. 8 illustrates an mask layer formed over the cap metal layer according to various embodiments described herein.
FIG. 9 illustrates an example electrode structure formed by etching the barrier layer, the conducting layer, and the cap metal layer around the mask layer …
FIG. 10 illustrates an example electrode structure formed after removing the mask layer according to various embodi- ments described herein.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing an electrode structure for a device, comprising: forming an insulating layer over a surface of a substrate; forming an opening in the insulating layer to expose a semiconductor material surface region of the substrate through the opening; depositing a barrier metal layer over the insulating layer and onto the semiconductor material surface region of the substrate through the opening in the insulating layer using atomic layer deposition; depositing a conducting metal layer over the barrier metal layer; depositing a cap metal layer over the conducting metal layer using sputtering; forming a cap etch photoresist layer over a region of the cap metal layer; and etching the cap metal layer, the conducting metal layer, and the barrier metal layer down to the insulating layer over an area outside of the cap etch photoresist layer.
The method according to claim 1, wherein depositing the barrier metal layer comprises depositing the barrier metal layer onto the insulating layer and onto the semicon-ductor material surface region of the substrate using atomic layer deposition.
The method according to claim 1, wherein the barrier metal layer comprises tungsten nitride.
The method according to claim 1, wherein depositing the conductive metal layer comprises sputtering the conduc-tive metal layer over the barrier metal layer.
The method according to claim 1, wherein the con-ducting metal layer comprises aluminum.
The method according to claim 1, wherein the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride.
The method according to claim 1, further comprising removing the cap etch photoresist layer.
The method according to claim 1, wherein: the substrate comprises a gallium nitride material layer; forming the opening in the insulating layer comprises exposing a surface region of the gallium nitride mate-rial layer; and depositing the barrier metal layer comprises depositing the barrier metal layer onto the surface region of the gallium nitride material layer.
A method of manufacturing an electrode structure for a device, comprising: providing a substrate comprising a gallium nitride mate-rial layer; forming an insulating layer over a surface of the gallium nitride material layer; forming an opening in the insulating layer to expose a surface region of the gallium nitride material layer through the opening; depositing a barrier metal layer over the insulating layer and onto the surface region of the gallium nitride material layer through the opening in the insulating layer using atomic layer deposition; depositing a conducting metal layer over the barrier metal layer; and depositing a cap metal layer of at least one of titanium nitride, tungsten, and tungsten nitride over the conduct-ing metal layer using sputtering.
The method according to claim 9, wherein the barrier metal layer comprises tungsten nitride.
The method according to claim 9, wherein depositing the conductive metal layer comprises sputtering the conduc-tive metal layer over the barrier metal layer.
The method according to claim 9, wherein the con-ducting metal layer comprises aluminum.
A method of manufacturing an electrode structure for a device, comprising: forming an opening in an insulating layer to expose a semiconductor material surface region of a substrate through the opening; depositing a barrier metal layer over the insulating layer and onto the semiconductor material surface region of the substrate through the opening using atomic layer deposition; depositing a conducting metal layer over the barrier metal layer using sputtering; depositing a cap metal layer over the conducting metal layer using sputtering; and etching the cap metal layer, the conducting metal layer, and the barrier metal layer down to the insulating layer over an area.
The method according to claim 13, wherein: the substrate comprises a gallium nitride material layer; forming the opening in the insulating layer comprises exposing a surface region of the gallium nitride mate-rial layer; and depositing the barrier metal layer comprises depositing the barrier metal layer onto the surface region of the gallium nitride material layer.
The method according to claim 13, wherein the conducting metal layer comprises aluminum.
The method according to claim 13, wherein the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride. 11 12
The method according to claim 13, wherein the barrier metal layer comprises tungsten nitride.
The method according to claim 13, wherein: the barrier metal layer comprises tungsten nitride; the conducting metal layer comprises aluminum; and the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride.
The method according to claim 13, wherein depositing the barrier metal layer comprises depositing the barrier metal layer onto the insulating layer and onto the semicon-ductor material surface region of the substrate using atomic layer deposition. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
electrode structure for GaN material device
Materials described outside the worked examples.
barrier metal layer
conducting metal layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 900–1025 Å | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 21
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,112,983 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example electrode structure for a device according to various embodiments described herein.
FIG. 2 illustrates an example method of forming the electrode structure shown in
FIG. 3 illustrates an example substrate and insulating dielectric layer according to various embodiments described herein.
FIG. 4 illustrates an example opening in the insulating dielectric layer shown in
FIG. 5 illustrates an example barrier metal layer formed over the insulating dielectric layer and the surface region of the substrate according to various …
FIG. 6 illustrates an example conducting metal layer formed over the barrier metal layer according to various embodiments described herein.
FIG. 7 illustrates an example cap metal layer formed over the conducting metal layer according to various embodi- ments described herein.
FIG. 8 illustrates an mask layer formed over the cap metal layer according to various embodiments described herein.
FIG. 9 illustrates an example electrode structure formed by etching the barrier layer, the conducting layer, and the cap metal layer around the mask layer …
FIG. 10 illustrates an example electrode structure formed after removing the mask layer according to various embodi- ments described herein.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing an electrode structure for a device, comprising: forming an insulating layer over a surface of a substrate; forming an opening in the insulating layer to expose a semiconductor material surface region of the substrate through the opening; depositing a barrier metal layer over the insulating layer and onto the semiconductor material surface region of the substrate through the opening in the insulating layer using atomic layer deposition; depositing a conducting metal layer over the barrier metal layer; depositing a cap metal layer over the conducting metal layer using sputtering; forming a cap etch photoresist layer over a region of the cap metal layer; and etching the cap metal layer, the conducting metal layer, and the barrier metal layer down to the insulating layer over an area outside of the cap etch photoresist layer.
The method according to claim 1, wherein depositing the barrier metal layer comprises depositing the barrier metal layer onto the insulating layer and onto the semicon-ductor material surface region of the substrate using atomic layer deposition.
The method according to claim 1, wherein the barrier metal layer comprises tungsten nitride.
The method according to claim 1, wherein depositing the conductive metal layer comprises sputtering the conduc-tive metal layer over the barrier metal layer.
The method according to claim 1, wherein the con-ducting metal layer comprises aluminum.
The method according to claim 1, wherein the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride.
The method according to claim 1, further comprising removing the cap etch photoresist layer.
The method according to claim 1, wherein: the substrate comprises a gallium nitride material layer; forming the opening in the insulating layer comprises exposing a surface region of the gallium nitride mate-rial layer; and depositing the barrier metal layer comprises depositing the barrier metal layer onto the surface region of the gallium nitride material layer.
A method of manufacturing an electrode structure for a device, comprising: providing a substrate comprising a gallium nitride mate-rial layer; forming an insulating layer over a surface of the gallium nitride material layer; forming an opening in the insulating layer to expose a surface region of the gallium nitride material layer through the opening; depositing a barrier metal layer over the insulating layer and onto the surface region of the gallium nitride material layer through the opening in the insulating layer using atomic layer deposition; depositing a conducting metal layer over the barrier metal layer; and depositing a cap metal layer of at least one of titanium nitride, tungsten, and tungsten nitride over the conduct-ing metal layer using sputtering.
The method according to claim 9, wherein the barrier metal layer comprises tungsten nitride.
The method according to claim 9, wherein depositing the conductive metal layer comprises sputtering the conduc-tive metal layer over the barrier metal layer.
The method according to claim 9, wherein the con-ducting metal layer comprises aluminum.
A method of manufacturing an electrode structure for a device, comprising: forming an opening in an insulating layer to expose a semiconductor material surface region of a substrate through the opening; depositing a barrier metal layer over the insulating layer and onto the semiconductor material surface region of the substrate through the opening using atomic layer deposition; depositing a conducting metal layer over the barrier metal layer using sputtering; depositing a cap metal layer over the conducting metal layer using sputtering; and etching the cap metal layer, the conducting metal layer, and the barrier metal layer down to the insulating layer over an area.
The method according to claim 13, wherein: the substrate comprises a gallium nitride material layer; forming the opening in the insulating layer comprises exposing a surface region of the gallium nitride mate-rial layer; and depositing the barrier metal layer comprises depositing the barrier metal layer onto the surface region of the gallium nitride material layer.
The method according to claim 13, wherein the conducting metal layer comprises aluminum.
The method according to claim 13, wherein the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride. 11 12
The method according to claim 13, wherein the barrier metal layer comprises tungsten nitride.
The method according to claim 13, wherein: the barrier metal layer comprises tungsten nitride; the conducting metal layer comprises aluminum; and the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride.
The method according to claim 13, wherein depositing the barrier metal layer comprises depositing the barrier metal layer onto the insulating layer and onto the semicon-ductor material surface region of the substrate using atomic layer deposition. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
electrode structure for GaN material device
Materials described outside the worked examples.
barrier metal layer
conducting metal layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 900–1025 Å | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 21
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,112,983 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an example electrode structure for a device according to various embodiments described herein.
FIG. 2 illustrates an example method of forming the electrode structure shown in
FIG. 3 illustrates an example substrate and insulating dielectric layer according to various embodiments described herein.
FIG. 4 illustrates an example opening in the insulating dielectric layer shown in
FIG. 5 illustrates an example barrier metal layer formed over the insulating dielectric layer and the surface region of the substrate according to various …
FIG. 6 illustrates an example conducting metal layer formed over the barrier metal layer according to various embodiments described herein.
FIG. 7 illustrates an example cap metal layer formed over the conducting metal layer according to various embodi- ments described herein.
FIG. 8 illustrates an mask layer formed over the cap metal layer according to various embodiments described herein.
FIG. 9 illustrates an example electrode structure formed by etching the barrier layer, the conducting layer, and the cap metal layer around the mask layer …
FIG. 10 illustrates an example electrode structure formed after removing the mask layer according to various embodi- ments described herein.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing an electrode structure for a device, comprising: forming an insulating layer over a surface of a substrate; forming an opening in the insulating layer to expose a semiconductor material surface region of the substrate through the opening; depositing a barrier metal layer over the insulating layer and onto the semiconductor material surface region of the substrate through the opening in the insulating layer using atomic layer deposition; depositing a conducting metal layer over the barrier metal layer; depositing a cap metal layer over the conducting metal layer using sputtering; forming a cap etch photoresist layer over a region of the cap metal layer; and etching the cap metal layer, the conducting metal layer, and the barrier metal layer down to the insulating layer over an area outside of the cap etch photoresist layer.
The method according to claim 1, wherein depositing the barrier metal layer comprises depositing the barrier metal layer onto the insulating layer and onto the semicon-ductor material surface region of the substrate using atomic layer deposition.
The method according to claim 1, wherein the barrier metal layer comprises tungsten nitride.
The method according to claim 1, wherein depositing the conductive metal layer comprises sputtering the conduc-tive metal layer over the barrier metal layer.
The method according to claim 1, wherein the con-ducting metal layer comprises aluminum.
The method according to claim 1, wherein the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride.
The method according to claim 1, further comprising removing the cap etch photoresist layer.
The method according to claim 1, wherein: the substrate comprises a gallium nitride material layer; forming the opening in the insulating layer comprises exposing a surface region of the gallium nitride mate-rial layer; and depositing the barrier metal layer comprises depositing the barrier metal layer onto the surface region of the gallium nitride material layer.
A method of manufacturing an electrode structure for a device, comprising: providing a substrate comprising a gallium nitride mate-rial layer; forming an insulating layer over a surface of the gallium nitride material layer; forming an opening in the insulating layer to expose a surface region of the gallium nitride material layer through the opening; depositing a barrier metal layer over the insulating layer and onto the surface region of the gallium nitride material layer through the opening in the insulating layer using atomic layer deposition; depositing a conducting metal layer over the barrier metal layer; and depositing a cap metal layer of at least one of titanium nitride, tungsten, and tungsten nitride over the conduct-ing metal layer using sputtering.
The method according to claim 9, wherein the barrier metal layer comprises tungsten nitride.
The method according to claim 9, wherein depositing the conductive metal layer comprises sputtering the conduc-tive metal layer over the barrier metal layer.
The method according to claim 9, wherein the con-ducting metal layer comprises aluminum.
A method of manufacturing an electrode structure for a device, comprising: forming an opening in an insulating layer to expose a semiconductor material surface region of a substrate through the opening; depositing a barrier metal layer over the insulating layer and onto the semiconductor material surface region of the substrate through the opening using atomic layer deposition; depositing a conducting metal layer over the barrier metal layer using sputtering; depositing a cap metal layer over the conducting metal layer using sputtering; and etching the cap metal layer, the conducting metal layer, and the barrier metal layer down to the insulating layer over an area.
The method according to claim 13, wherein: the substrate comprises a gallium nitride material layer; forming the opening in the insulating layer comprises exposing a surface region of the gallium nitride mate-rial layer; and depositing the barrier metal layer comprises depositing the barrier metal layer onto the surface region of the gallium nitride material layer.
The method according to claim 13, wherein the conducting metal layer comprises aluminum.
The method according to claim 13, wherein the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride. 11 12
The method according to claim 13, wherein the barrier metal layer comprises tungsten nitride.
The method according to claim 13, wherein: the barrier metal layer comprises tungsten nitride; the conducting metal layer comprises aluminum; and the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride.
The method according to claim 13, wherein depositing the barrier metal layer comprises depositing the barrier metal layer onto the insulating layer and onto the semicon-ductor material surface region of the substrate using atomic layer deposition. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
electrode structure for GaN material device
Materials described outside the worked examples.
barrier metal layer
conducting metal layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 900–1025 Å | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 21
Related documents with shared materials, methods, properties, or citations.
cap metal layer
insulating layer
tungsten nitride
WN
aluminum
Al
titanium nitride
TiN
tungsten
W
gallium nitride material layer
GaN
silicon nitride
SiN
silicon dioxide
SiO₂
aluminum oxide
Al₂O₃
hafnium dioxide
HfO₂
aluminum gallium nitride
AlGaN
| — |
Thickness | 5800–6200 Å | — |
Thickness | 80–120 Å | — |
Thickness | 300–500 Å | — |
Cited non-patent literature · 2
cap metal layer
insulating layer
tungsten nitride
WN
aluminum
Al
titanium nitride
TiN
tungsten
W
gallium nitride material layer
GaN
silicon nitride
SiN
silicon dioxide
SiO₂
aluminum oxide
Al₂O₃
hafnium dioxide
HfO₂
aluminum gallium nitride
AlGaN
| — |
Thickness | 5800–6200 Å | — |
Thickness | 80–120 Å | — |
Thickness | 300–500 Å | — |
Cited non-patent literature · 2
cap metal layer
insulating layer
tungsten nitride
WN
aluminum
Al
titanium nitride
TiN
tungsten
W
gallium nitride material layer
GaN
silicon nitride
SiN
silicon dioxide
SiO₂
aluminum oxide
Al₂O₃
hafnium dioxide
HfO₂
aluminum gallium nitride
AlGaN
| — |
Thickness | 5800–6200 Å | — |
Thickness | 80–120 Å | — |
Thickness | 300–500 Å | — |
Cited non-patent literature · 2
cap metal layer
insulating layer
tungsten nitride
WN
aluminum
Al
titanium nitride
TiN
tungsten
W
gallium nitride material layer
GaN
silicon nitride
SiN
silicon dioxide
SiO₂
aluminum oxide
Al₂O₃
hafnium dioxide
HfO₂
aluminum gallium nitride
AlGaN
| — |
Thickness | 5800–6200 Å | — |
Thickness | 80–120 Å | — |
Thickness | 300–500 Å | — |
Cited non-patent literature · 2
