Patent
US 10,553,762LIGHT EMITTING DIODE CHIP AND PREPARATION METHOD THEREOF
Peng XIE
US
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Patent
Atlas literature
Patent
US 10,553,762Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Referring to
FIG. 2 is a schematic view of a light emitting diode chip according to an embodiment of the invention; and [0035]
FIG. 3 is a top view of a light emitting diode chip according to an embodiment of the invention. DETAILED DESCRIPTION OF THE EMBODIMENTS [0036] The objects, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-9. Canceled
Canceled
A light emitting diode chip, comprising: a substrate; an n-type semiconductor layer, an active layer and a p-type semiconductor layer laminated on the substrate sequentially in that order; a step formed in the n-type semiconductor layer, the active layer and the p-type semiconductor layer, the step comprising an upper horizontal end surface, a lower horizontal end surface, and a step surface connecting the upper horizontal end surface and the lower horizontal end surface, the lower horizontal end surface comprising an N electrode formed thereon, the upper horizontal end surface being covered with a transparent conductive layer with an etching hole formed in a middle of the transparent conductive layer, and the etching hole comprising a P electrode formed therein; wherein the light emitting diode chip further comprises a metal catalyst layer covering areas other than central areas of top surfaces of the N electrode and the P electrode and other than the step surface, and a fluorinated graphene protective layer covering the metal catalyst layer. Currently amended
The light emitting diode chip of claim 10, wherein the metal catalyst layer is made of Nickel (N i), Indium (In), Titanium (Ti), Rhodium (Rh) or Zin c (Zn); or the metal catalyst layer is made of an alloy comprising at least two of Nickle (N i), Indium (In), Titanium (Ti), Rhodium (Rh) or Zin c (Zn); or the metal catalyst layer is formed by a metal organic source which comprises Nickel (N i), Indium (In), Titanium (Ti), Rhodium (Rh) or Zinc (Zn). Currently amended
The li g ht emittin g diode chip of claim 10, wherein the metal catalyst layer has a thickness of 1-1 5 nm. Currently amended
The light emitting diode chip of claim 10, wherein a thickness of the fluorinated graphene protective layer is equal to a thickness of 1- 10 layers of monatomic fluorinated graphene. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
light emitting diode chip
Materials described outside the worked examples.
ITO transparent conductive layer
metal catalyst layer
fluorinated graphene protective layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
metal catalyst layer thickness | 1–15 | metal catalyst layer |
fluorinated graphene protective layer thickness | 1–10 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,553,762Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Referring to
FIG. 2 is a schematic view of a light emitting diode chip according to an embodiment of the invention; and [0035]
FIG. 3 is a top view of a light emitting diode chip according to an embodiment of the invention. DETAILED DESCRIPTION OF THE EMBODIMENTS [0036] The objects, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-9. Canceled
Canceled
A light emitting diode chip, comprising: a substrate; an n-type semiconductor layer, an active layer and a p-type semiconductor layer laminated on the substrate sequentially in that order; a step formed in the n-type semiconductor layer, the active layer and the p-type semiconductor layer, the step comprising an upper horizontal end surface, a lower horizontal end surface, and a step surface connecting the upper horizontal end surface and the lower horizontal end surface, the lower horizontal end surface comprising an N electrode formed thereon, the upper horizontal end surface being covered with a transparent conductive layer with an etching hole formed in a middle of the transparent conductive layer, and the etching hole comprising a P electrode formed therein; wherein the light emitting diode chip further comprises a metal catalyst layer covering areas other than central areas of top surfaces of the N electrode and the P electrode and other than the step surface, and a fluorinated graphene protective layer covering the metal catalyst layer. Currently amended
The light emitting diode chip of claim 10, wherein the metal catalyst layer is made of Nickel (N i), Indium (In), Titanium (Ti), Rhodium (Rh) or Zin c (Zn); or the metal catalyst layer is made of an alloy comprising at least two of Nickle (N i), Indium (In), Titanium (Ti), Rhodium (Rh) or Zin c (Zn); or the metal catalyst layer is formed by a metal organic source which comprises Nickel (N i), Indium (In), Titanium (Ti), Rhodium (Rh) or Zinc (Zn). Currently amended
The li g ht emittin g diode chip of claim 10, wherein the metal catalyst layer has a thickness of 1-1 5 nm. Currently amended
The light emitting diode chip of claim 10, wherein a thickness of the fluorinated graphene protective layer is equal to a thickness of 1- 10 layers of monatomic fluorinated graphene. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
light emitting diode chip
Materials described outside the worked examples.
ITO transparent conductive layer
metal catalyst layer
fluorinated graphene protective layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
metal catalyst layer thickness | 1–15 | metal catalyst layer |
fluorinated graphene protective layer thickness | 1–10 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,553,762Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Referring to
FIG. 2 is a schematic view of a light emitting diode chip according to an embodiment of the invention; and [0035]
FIG. 3 is a top view of a light emitting diode chip according to an embodiment of the invention. DETAILED DESCRIPTION OF THE EMBODIMENTS [0036] The objects, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-9. Canceled
Canceled
A light emitting diode chip, comprising: a substrate; an n-type semiconductor layer, an active layer and a p-type semiconductor layer laminated on the substrate sequentially in that order; a step formed in the n-type semiconductor layer, the active layer and the p-type semiconductor layer, the step comprising an upper horizontal end surface, a lower horizontal end surface, and a step surface connecting the upper horizontal end surface and the lower horizontal end surface, the lower horizontal end surface comprising an N electrode formed thereon, the upper horizontal end surface being covered with a transparent conductive layer with an etching hole formed in a middle of the transparent conductive layer, and the etching hole comprising a P electrode formed therein; wherein the light emitting diode chip further comprises a metal catalyst layer covering areas other than central areas of top surfaces of the N electrode and the P electrode and other than the step surface, and a fluorinated graphene protective layer covering the metal catalyst layer. Currently amended
The light emitting diode chip of claim 10, wherein the metal catalyst layer is made of Nickel (N i), Indium (In), Titanium (Ti), Rhodium (Rh) or Zin c (Zn); or the metal catalyst layer is made of an alloy comprising at least two of Nickle (N i), Indium (In), Titanium (Ti), Rhodium (Rh) or Zin c (Zn); or the metal catalyst layer is formed by a metal organic source which comprises Nickel (N i), Indium (In), Titanium (Ti), Rhodium (Rh) or Zinc (Zn). Currently amended
The li g ht emittin g diode chip of claim 10, wherein the metal catalyst layer has a thickness of 1-1 5 nm. Currently amended
The light emitting diode chip of claim 10, wherein a thickness of the fluorinated graphene protective layer is equal to a thickness of 1- 10 layers of monatomic fluorinated graphene. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
light emitting diode chip
Materials described outside the worked examples.
ITO transparent conductive layer
metal catalyst layer
fluorinated graphene protective layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
metal catalyst layer thickness | 1–15 | metal catalyst layer |
fluorinated graphene protective layer thickness | 1–10 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,553,762Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Referring to
FIG. 2 is a schematic view of a light emitting diode chip according to an embodiment of the invention; and [0035]
FIG. 3 is a top view of a light emitting diode chip according to an embodiment of the invention. DETAILED DESCRIPTION OF THE EMBODIMENTS [0036] The objects, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1-9. Canceled
Canceled
A light emitting diode chip, comprising: a substrate; an n-type semiconductor layer, an active layer and a p-type semiconductor layer laminated on the substrate sequentially in that order; a step formed in the n-type semiconductor layer, the active layer and the p-type semiconductor layer, the step comprising an upper horizontal end surface, a lower horizontal end surface, and a step surface connecting the upper horizontal end surface and the lower horizontal end surface, the lower horizontal end surface comprising an N electrode formed thereon, the upper horizontal end surface being covered with a transparent conductive layer with an etching hole formed in a middle of the transparent conductive layer, and the etching hole comprising a P electrode formed therein; wherein the light emitting diode chip further comprises a metal catalyst layer covering areas other than central areas of top surfaces of the N electrode and the P electrode and other than the step surface, and a fluorinated graphene protective layer covering the metal catalyst layer. Currently amended
The light emitting diode chip of claim 10, wherein the metal catalyst layer is made of Nickel (N i), Indium (In), Titanium (Ti), Rhodium (Rh) or Zin c (Zn); or the metal catalyst layer is made of an alloy comprising at least two of Nickle (N i), Indium (In), Titanium (Ti), Rhodium (Rh) or Zin c (Zn); or the metal catalyst layer is formed by a metal organic source which comprises Nickel (N i), Indium (In), Titanium (Ti), Rhodium (Rh) or Zinc (Zn). Currently amended
The li g ht emittin g diode chip of claim 10, wherein the metal catalyst layer has a thickness of 1-1 5 nm. Currently amended
The light emitting diode chip of claim 10, wherein a thickness of the fluorinated graphene protective layer is equal to a thickness of 1- 10 layers of monatomic fluorinated graphene. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
light emitting diode chip
Materials described outside the worked examples.
ITO transparent conductive layer
metal catalyst layer
fluorinated graphene protective layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
metal catalyst layer thickness | 1–15 | metal catalyst layer |
fluorinated graphene protective layer thickness | 1–10 |
Related documents with shared materials, methods, properties, or citations.
n-type semiconductor layer
p-type semiconductor layer
active layer
Thickness | 1–15 nm | — |
Temperature | 500–750 °C | — |
Pressure | 300–600 Pa | — |
Pressure | ≤ 1 Pa | — |
n-type semiconductor layer
p-type semiconductor layer
active layer
Thickness | 1–15 nm | — |
Temperature | 500–750 °C | — |
Pressure | 300–600 Pa | — |
Pressure | ≤ 1 Pa | — |
n-type semiconductor layer
p-type semiconductor layer
active layer
Thickness | 1–15 nm | — |
Temperature | 500–750 °C | — |
Pressure | 300–600 Pa | — |
Pressure | ≤ 1 Pa | — |
n-type semiconductor layer
p-type semiconductor layer
active layer
Thickness | 1–15 nm | — |
Temperature | 500–750 °C | — |
Pressure | 300–600 Pa | — |
Pressure | ≤ 1 Pa | — |