Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-section of a GaN device in accordance with one preferred embodiment of the present invention; and
FIG. 2 to
FIG. 3. After the passivation layer 108 is formed, a photolithography process is then performed to form recesses 122 in the passivation layer 108 at two sides …
FIG. 4. After the recess 122 is formed, a source 110a and a drain 110b are formed on the surfaces of recesses 122. In the embodiment of present invention, the …
FIG. 5. After the source 110a and drain 110b are formed, a first ILD layer 112 is formed on the surfaces of passivation layer 108, source 110a and drain 110b. …
FIG. 6. After the first ILD layer 112 is formed, a stop layer 114 and a second ILD layer 116 are formed sequentially on the first ILD layer. The material of stop …
FIG. 7. After the stop layer 114 and second ILD layer 116 are formed, a dual-damascene process is then performed to form dual-damascene recesses 124 in the …
FIG. 8 are schematic cross-sections illustrating a process flow of manufacturing the GaN device in accor- dance with one preferred embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride device with field plate structure, comprising: a substrate; a gate on said substrate; a passivation layer covering on said gate; a source and a drain on said substrate and said passivation layer; a stop layer on said source, said drain and said passivation layer; and dual-damascene interconnects connecting respectively with said source and said drain, wherein said dual-damascene interconnect is provided with a via portion under said stop layer and a trench portion on said stop layer, and said via portion is connected with said source or said drain, and said trench portion of one of said dual-damascene interconnects extends horizontally toward said drain and overlaps said gate in vertical direction, thereby functioning as a field plate structure for said gallium nitride device; wherein a first interlayer dielectric (ILD) layer and a second ILD layer is provided respectively above and below said stop layer, and said via portion of said dual-damascene interconnect is in said first ILD layer, and said trench portion of said dual-damascene interconnect is in said second ILD layer, and said via portion and said trench portion is demarcated by said stop layer.
The gallium nitride device with field plate structure of claim 1, wherein said passivation layer is provided with a recess exposing said substrate below, and said source and said drain extend conformally along a surface of said recess and directly contact said substrate.
The gallium nitride device with field plate structure of claim 1, wherein said substrate comprises a silicon layer, a buffer layer and a channel layer.
The gallium nitride device with field plate structure of claim 1, wherein a material of said buffer layer is gallium nitride (GaN), and a material of said channel layer is aluminum gallium nitride (AlGaN).
The gallium nitride device with field plate structure of claim 1, wherein said source is provided with a field plate portion extending toward said drain along a surface of said passivation layer and overlapping said gate in vertical direc-tion, and said field plate portion is between said passivation layer and said stop layer, and said filed plate portion overlaps said trench portion of said dual-damascene structure that extends onto said gate in vertical direction.
The gallium nitride device with field plate structure of claim 1, further comprising an etch stop layer on said dual-damascene interconnects and said second ILD layer.
The gallium nitride device with field plate structure of claim 1, wherein a material of said first ILD layer and said second ILD layer is silicon oxide, and a material of said stop layer is silicon nitride.
The gallium nitride device with field plate structure of claim 1, wherein a material of said source and said drain comprises titanium (Ti), aluminum (Al), nickel (Ni), gold (Au) or a multilayer structure thereof, or a silicide thereof.
The gallium nitride device with field plate structure of claim 1, wherein a material of said gate is p-type doped gallium nitride (p-GaN).
The gallium nitride device with field plate structure of claim 1, wherein a material of said dual-damascene interconnect is copper (Cu). ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride field-effect transistor with dual-damascene field plate structure
Materials described outside the worked examples.
passivation layer
stop layer
dual-damascene interconnect
silicon layer
Si
gallium nitride buffer layer
GaN
aluminum gallium nitride channel layer
AlGaN
silicon nitride etch stop layer
Si₃N₄
silicon carbon nitride etch stop layer
SiCN
silicon oxide ILD
SiO₂
source/drain metal
p-type doped gallium nitride gate
p-GaN
copper dual-damascene interconnect
Cu
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 24
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-section of a GaN device in accordance with one preferred embodiment of the present invention; and
FIG. 2 to
FIG. 3. After the passivation layer 108 is formed, a photolithography process is then performed to form recesses 122 in the passivation layer 108 at two sides …
FIG. 4. After the recess 122 is formed, a source 110a and a drain 110b are formed on the surfaces of recesses 122. In the embodiment of present invention, the …
FIG. 5. After the source 110a and drain 110b are formed, a first ILD layer 112 is formed on the surfaces of passivation layer 108, source 110a and drain 110b. …
FIG. 6. After the first ILD layer 112 is formed, a stop layer 114 and a second ILD layer 116 are formed sequentially on the first ILD layer. The material of stop …
FIG. 7. After the stop layer 114 and second ILD layer 116 are formed, a dual-damascene process is then performed to form dual-damascene recesses 124 in the …
FIG. 8 are schematic cross-sections illustrating a process flow of manufacturing the GaN device in accor- dance with one preferred embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride device with field plate structure, comprising: a substrate; a gate on said substrate; a passivation layer covering on said gate; a source and a drain on said substrate and said passivation layer; a stop layer on said source, said drain and said passivation layer; and dual-damascene interconnects connecting respectively with said source and said drain, wherein said dual-damascene interconnect is provided with a via portion under said stop layer and a trench portion on said stop layer, and said via portion is connected with said source or said drain, and said trench portion of one of said dual-damascene interconnects extends horizontally toward said drain and overlaps said gate in vertical direction, thereby functioning as a field plate structure for said gallium nitride device; wherein a first interlayer dielectric (ILD) layer and a second ILD layer is provided respectively above and below said stop layer, and said via portion of said dual-damascene interconnect is in said first ILD layer, and said trench portion of said dual-damascene interconnect is in said second ILD layer, and said via portion and said trench portion is demarcated by said stop layer.
The gallium nitride device with field plate structure of claim 1, wherein said passivation layer is provided with a recess exposing said substrate below, and said source and said drain extend conformally along a surface of said recess and directly contact said substrate.
The gallium nitride device with field plate structure of claim 1, wherein said substrate comprises a silicon layer, a buffer layer and a channel layer.
The gallium nitride device with field plate structure of claim 1, wherein a material of said buffer layer is gallium nitride (GaN), and a material of said channel layer is aluminum gallium nitride (AlGaN).
The gallium nitride device with field plate structure of claim 1, wherein said source is provided with a field plate portion extending toward said drain along a surface of said passivation layer and overlapping said gate in vertical direc-tion, and said field plate portion is between said passivation layer and said stop layer, and said filed plate portion overlaps said trench portion of said dual-damascene structure that extends onto said gate in vertical direction.
The gallium nitride device with field plate structure of claim 1, further comprising an etch stop layer on said dual-damascene interconnects and said second ILD layer.
The gallium nitride device with field plate structure of claim 1, wherein a material of said first ILD layer and said second ILD layer is silicon oxide, and a material of said stop layer is silicon nitride.
The gallium nitride device with field plate structure of claim 1, wherein a material of said source and said drain comprises titanium (Ti), aluminum (Al), nickel (Ni), gold (Au) or a multilayer structure thereof, or a silicide thereof.
The gallium nitride device with field plate structure of claim 1, wherein a material of said gate is p-type doped gallium nitride (p-GaN).
The gallium nitride device with field plate structure of claim 1, wherein a material of said dual-damascene interconnect is copper (Cu). ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride field-effect transistor with dual-damascene field plate structure
Materials described outside the worked examples.
passivation layer
stop layer
dual-damascene interconnect
silicon layer
Si
gallium nitride buffer layer
GaN
aluminum gallium nitride channel layer
AlGaN
silicon nitride etch stop layer
Si₃N₄
silicon carbon nitride etch stop layer
SiCN
silicon oxide ILD
SiO₂
source/drain metal
p-type doped gallium nitride gate
p-GaN
copper dual-damascene interconnect
Cu
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 24
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-section of a GaN device in accordance with one preferred embodiment of the present invention; and
FIG. 2 to
FIG. 3. After the passivation layer 108 is formed, a photolithography process is then performed to form recesses 122 in the passivation layer 108 at two sides …
FIG. 4. After the recess 122 is formed, a source 110a and a drain 110b are formed on the surfaces of recesses 122. In the embodiment of present invention, the …
FIG. 5. After the source 110a and drain 110b are formed, a first ILD layer 112 is formed on the surfaces of passivation layer 108, source 110a and drain 110b. …
FIG. 6. After the first ILD layer 112 is formed, a stop layer 114 and a second ILD layer 116 are formed sequentially on the first ILD layer. The material of stop …
FIG. 7. After the stop layer 114 and second ILD layer 116 are formed, a dual-damascene process is then performed to form dual-damascene recesses 124 in the …
FIG. 8 are schematic cross-sections illustrating a process flow of manufacturing the GaN device in accor- dance with one preferred embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride device with field plate structure, comprising: a substrate; a gate on said substrate; a passivation layer covering on said gate; a source and a drain on said substrate and said passivation layer; a stop layer on said source, said drain and said passivation layer; and dual-damascene interconnects connecting respectively with said source and said drain, wherein said dual-damascene interconnect is provided with a via portion under said stop layer and a trench portion on said stop layer, and said via portion is connected with said source or said drain, and said trench portion of one of said dual-damascene interconnects extends horizontally toward said drain and overlaps said gate in vertical direction, thereby functioning as a field plate structure for said gallium nitride device; wherein a first interlayer dielectric (ILD) layer and a second ILD layer is provided respectively above and below said stop layer, and said via portion of said dual-damascene interconnect is in said first ILD layer, and said trench portion of said dual-damascene interconnect is in said second ILD layer, and said via portion and said trench portion is demarcated by said stop layer.
The gallium nitride device with field plate structure of claim 1, wherein said passivation layer is provided with a recess exposing said substrate below, and said source and said drain extend conformally along a surface of said recess and directly contact said substrate.
The gallium nitride device with field plate structure of claim 1, wherein said substrate comprises a silicon layer, a buffer layer and a channel layer.
The gallium nitride device with field plate structure of claim 1, wherein a material of said buffer layer is gallium nitride (GaN), and a material of said channel layer is aluminum gallium nitride (AlGaN).
The gallium nitride device with field plate structure of claim 1, wherein said source is provided with a field plate portion extending toward said drain along a surface of said passivation layer and overlapping said gate in vertical direc-tion, and said field plate portion is between said passivation layer and said stop layer, and said filed plate portion overlaps said trench portion of said dual-damascene structure that extends onto said gate in vertical direction.
The gallium nitride device with field plate structure of claim 1, further comprising an etch stop layer on said dual-damascene interconnects and said second ILD layer.
The gallium nitride device with field plate structure of claim 1, wherein a material of said first ILD layer and said second ILD layer is silicon oxide, and a material of said stop layer is silicon nitride.
The gallium nitride device with field plate structure of claim 1, wherein a material of said source and said drain comprises titanium (Ti), aluminum (Al), nickel (Ni), gold (Au) or a multilayer structure thereof, or a silicide thereof.
The gallium nitride device with field plate structure of claim 1, wherein a material of said gate is p-type doped gallium nitride (p-GaN).
The gallium nitride device with field plate structure of claim 1, wherein a material of said dual-damascene interconnect is copper (Cu). ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride field-effect transistor with dual-damascene field plate structure
Materials described outside the worked examples.
passivation layer
stop layer
dual-damascene interconnect
silicon layer
Si
gallium nitride buffer layer
GaN
aluminum gallium nitride channel layer
AlGaN
silicon nitride etch stop layer
Si₃N₄
silicon carbon nitride etch stop layer
SiCN
silicon oxide ILD
SiO₂
source/drain metal
p-type doped gallium nitride gate
p-GaN
copper dual-damascene interconnect
Cu
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 24
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-section of a GaN device in accordance with one preferred embodiment of the present invention; and
FIG. 2 to
FIG. 3. After the passivation layer 108 is formed, a photolithography process is then performed to form recesses 122 in the passivation layer 108 at two sides …
FIG. 4. After the recess 122 is formed, a source 110a and a drain 110b are formed on the surfaces of recesses 122. In the embodiment of present invention, the …
FIG. 5. After the source 110a and drain 110b are formed, a first ILD layer 112 is formed on the surfaces of passivation layer 108, source 110a and drain 110b. …
FIG. 6. After the first ILD layer 112 is formed, a stop layer 114 and a second ILD layer 116 are formed sequentially on the first ILD layer. The material of stop …
FIG. 7. After the stop layer 114 and second ILD layer 116 are formed, a dual-damascene process is then performed to form dual-damascene recesses 124 in the …
FIG. 8 are schematic cross-sections illustrating a process flow of manufacturing the GaN device in accor- dance with one preferred embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride device with field plate structure, comprising: a substrate; a gate on said substrate; a passivation layer covering on said gate; a source and a drain on said substrate and said passivation layer; a stop layer on said source, said drain and said passivation layer; and dual-damascene interconnects connecting respectively with said source and said drain, wherein said dual-damascene interconnect is provided with a via portion under said stop layer and a trench portion on said stop layer, and said via portion is connected with said source or said drain, and said trench portion of one of said dual-damascene interconnects extends horizontally toward said drain and overlaps said gate in vertical direction, thereby functioning as a field plate structure for said gallium nitride device; wherein a first interlayer dielectric (ILD) layer and a second ILD layer is provided respectively above and below said stop layer, and said via portion of said dual-damascene interconnect is in said first ILD layer, and said trench portion of said dual-damascene interconnect is in said second ILD layer, and said via portion and said trench portion is demarcated by said stop layer.
The gallium nitride device with field plate structure of claim 1, wherein said passivation layer is provided with a recess exposing said substrate below, and said source and said drain extend conformally along a surface of said recess and directly contact said substrate.
The gallium nitride device with field plate structure of claim 1, wherein said substrate comprises a silicon layer, a buffer layer and a channel layer.
The gallium nitride device with field plate structure of claim 1, wherein a material of said buffer layer is gallium nitride (GaN), and a material of said channel layer is aluminum gallium nitride (AlGaN).
The gallium nitride device with field plate structure of claim 1, wherein said source is provided with a field plate portion extending toward said drain along a surface of said passivation layer and overlapping said gate in vertical direc-tion, and said field plate portion is between said passivation layer and said stop layer, and said filed plate portion overlaps said trench portion of said dual-damascene structure that extends onto said gate in vertical direction.
The gallium nitride device with field plate structure of claim 1, further comprising an etch stop layer on said dual-damascene interconnects and said second ILD layer.
The gallium nitride device with field plate structure of claim 1, wherein a material of said first ILD layer and said second ILD layer is silicon oxide, and a material of said stop layer is silicon nitride.
The gallium nitride device with field plate structure of claim 1, wherein a material of said source and said drain comprises titanium (Ti), aluminum (Al), nickel (Ni), gold (Au) or a multilayer structure thereof, or a silicide thereof.
The gallium nitride device with field plate structure of claim 1, wherein a material of said gate is p-type doped gallium nitride (p-GaN).
The gallium nitride device with field plate structure of claim 1, wherein a material of said dual-damascene interconnect is copper (Cu). ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride field-effect transistor with dual-damascene field plate structure
Materials described outside the worked examples.
passivation layer
stop layer
dual-damascene interconnect
silicon layer
Si
gallium nitride buffer layer
GaN
aluminum gallium nitride channel layer
AlGaN
silicon nitride etch stop layer
Si₃N₄
silicon carbon nitride etch stop layer
SiCN
silicon oxide ILD
SiO₂
source/drain metal
p-type doped gallium nitride gate
p-GaN
copper dual-damascene interconnect
Cu
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 24
