Patent
Atlas literature
Patent
US 11,955,960 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1C are some functional block diagram according to some embodiments of the invention.
FIG. 2B are two schematic diagrams accord- ing to some embodiments of the invention respectively.
FIG. 3F present the features of the proposed invention and the differences from some conventional technologies according to some embodiments of the invention.
FIG. 4B are circuit diagram and timing 40 diagram according to some embodiments respectively.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A depletion mode GaN transistor control circuit, com-prising: a current detecting module formed on a silicon wafer and configured to detect a leakage current of a depletion mode GaN transistor formed on a depletion mode GaN wafer; and 20 a gate voltage adjusting module formed on the silicon wafer and configured to adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current; wherein the gate voltage adjusting module comprises both 25 a voltage source configured to provide a fixed voltage to the gate of the depletion mode GaN transistor and a negative voltage converter configured to provide a negative voltage according to the detected current to the gate of the depletion mode GaN transistor, wherein the gate voltage of the depletion mode GaN transistor is modified by the combination of the fixed voltage and the negative voltage.
The control circuit according to claim 1, further com-prising at least one of the following: the gate voltage adjusting module is configured to make the gate voltage more negative when the detected leakage current is larger than zero; the gate voltage adjusting module is configured to make the gate voltage more positive when the detected leak-age current is zero; and the gate voltage adjusting module is configured to make the gate voltage to be a threshold voltage such that the transistor has just right a zero leakage current.
The control circuit according to claim 1, further com-prising a gate voltage tracking module formed on the silicon wafer and configured to track the gate voltage of the depletion mode GaN transistor, wherein the gate voltage adjusting module is configured to adjust the gate voltage of the depletion mode GaN transistor according to both the detected leakage current and the tracked gate voltage.
The control circuit according to claim 1, wherein the gate voltage adjusting module comprises a negative voltage converter configured to provide a negative voltage less than the tracked gate voltage to the gate of the depletion mode GaN transistor so as to update the gate voltage of the depletion mode GaN transistor.
The control circuit according to claim 1, wherein the leakage current detecting module comprises an adjustable current mirror for duplicating and enlarging the leakage current such that the gate voltage adjusting module is configured to adjust the gate voltage of the depletion mode GaN transistor according to directly an enlarged detected leakage current.
The control circuit according to claim 1, further com-prising a controlling module formed on the silicon wafer and configured to operate both the current detecting module and B₂ the gate voltage adjusting module in one or more of the following situations: the depletion mode GaN transistor is operated first time, the depletion mode GaN transistor has been operated a certain number of times, the depletion mode GaN transistor has been operated for a certain period of time, the depletion mode GaN transistor has been operated under an extreme working condition, and an external Vth calibration command is received.
A depletion mode GaN product, comprising: one or more depletion mode GaN transistors formed on a depletion mode GaN wafer; and one or more control circuits formed on a silicon wafer; wherein the control circuits and the depletion mode GaN transistors are paired one-to-one with each other; wherein each control circuit detects leakage current of a paired depletion mode GaN transistor and then adjusts gate voltage of the paired depletion mode GaN tran-sistor accordingly; wherein each control circuit comprises a current detecting module configured to detect the leakage current of a paired depletion mode GaN transistor and a gate volt-age adjusting module configured to adjust the gate voltage of the paired depletion mode GaN transistor according to the detected leakage current; wherein the gate voltage adjusting module comprises both a voltage source configured to provide a fixed voltage to the gate of the paired depletion mode GaN transistor and a negative voltage converter configured to provide a negative voltage according to the detected current to the gate of the paired depletion mode GaN transistor, wherein the gate voltage of the paired depletion mode GaN transistor is modified by the combination of the fixed voltage of the negative voltage.
The GaN product according to claim 7, wherein each control circuit comprises a controlling module configured to operate both the current detecting module and the gate voltage adjusting module in one or more of the following situations: the paired GaN transistors are operated first time, the paired depletion mode GaN transistors have been oper-ated a certain number of times, the paired depletion mode GaN transistors have been operated for a certain period of time, the paired depletion mode GaN transistors have been operated under an extreme working condition, and an exter-nal Vth calibration command is received.
The GaN product according to claim 7, each control circuit further comprising at least one of the following: the gate voltage adjusting module is configured to make the gate voltage more negative when the detected leakage current is larger than zero; the gate voltage adjusting module is configured to make the gate voltage more positive when the detected leak-age current is zero; and the gate voltage adjusting module is configured to make the gate voltage to be a threshold voltage such that the paired depletion mode GaN transistor has right a zero leakage current.
The GaN product according to claim 7, wherein each control circuit comprises a gate voltage tracking module and configured to track the gate voltage of the paired depletion mode GaN transistor, wherein the gate voltage adjusting module is configured to adjust the gate voltage of the paired depletion mode GaN transistor according to both the detected leakage current and the tracked gate voltage.
The GaN product according to claim 7, wherein the gate voltage adjusting module comprises a negative voltage converter configured to provide a negative voltage less than the tracked gate voltage to the gate of the paired depletion 15 16 mode GaN transistor so as to update the gate voltage of the depletion mode GaN transistor.
The GaN product according to claim 7, wherein the leakage current detecting module comprises an adjustable current mirror for duplicating and enlarging the leakage current such that the gate voltage adjusting module is configured to adjust the gate voltage of the paired depletion mode GaN transistor according to directly an enlarged detected leakage current. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
depletion mode GaN transistor control circuit
depletion mode GaN product
Materials described outside the worked examples.
GaN (depletion mode wafer)
GaN
silicon wafer
Si
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,955,960 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1C are some functional block diagram according to some embodiments of the invention.
FIG. 2B are two schematic diagrams accord- ing to some embodiments of the invention respectively.
FIG. 3F present the features of the proposed invention and the differences from some conventional technologies according to some embodiments of the invention.
FIG. 4B are circuit diagram and timing 40 diagram according to some embodiments respectively.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A depletion mode GaN transistor control circuit, com-prising: a current detecting module formed on a silicon wafer and configured to detect a leakage current of a depletion mode GaN transistor formed on a depletion mode GaN wafer; and 20 a gate voltage adjusting module formed on the silicon wafer and configured to adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current; wherein the gate voltage adjusting module comprises both 25 a voltage source configured to provide a fixed voltage to the gate of the depletion mode GaN transistor and a negative voltage converter configured to provide a negative voltage according to the detected current to the gate of the depletion mode GaN transistor, wherein the gate voltage of the depletion mode GaN transistor is modified by the combination of the fixed voltage and the negative voltage.
The control circuit according to claim 1, further com-prising at least one of the following: the gate voltage adjusting module is configured to make the gate voltage more negative when the detected leakage current is larger than zero; the gate voltage adjusting module is configured to make the gate voltage more positive when the detected leak-age current is zero; and the gate voltage adjusting module is configured to make the gate voltage to be a threshold voltage such that the transistor has just right a zero leakage current.
The control circuit according to claim 1, further com-prising a gate voltage tracking module formed on the silicon wafer and configured to track the gate voltage of the depletion mode GaN transistor, wherein the gate voltage adjusting module is configured to adjust the gate voltage of the depletion mode GaN transistor according to both the detected leakage current and the tracked gate voltage.
The control circuit according to claim 1, wherein the gate voltage adjusting module comprises a negative voltage converter configured to provide a negative voltage less than the tracked gate voltage to the gate of the depletion mode GaN transistor so as to update the gate voltage of the depletion mode GaN transistor.
The control circuit according to claim 1, wherein the leakage current detecting module comprises an adjustable current mirror for duplicating and enlarging the leakage current such that the gate voltage adjusting module is configured to adjust the gate voltage of the depletion mode GaN transistor according to directly an enlarged detected leakage current.
The control circuit according to claim 1, further com-prising a controlling module formed on the silicon wafer and configured to operate both the current detecting module and B₂ the gate voltage adjusting module in one or more of the following situations: the depletion mode GaN transistor is operated first time, the depletion mode GaN transistor has been operated a certain number of times, the depletion mode GaN transistor has been operated for a certain period of time, the depletion mode GaN transistor has been operated under an extreme working condition, and an external Vth calibration command is received.
A depletion mode GaN product, comprising: one or more depletion mode GaN transistors formed on a depletion mode GaN wafer; and one or more control circuits formed on a silicon wafer; wherein the control circuits and the depletion mode GaN transistors are paired one-to-one with each other; wherein each control circuit detects leakage current of a paired depletion mode GaN transistor and then adjusts gate voltage of the paired depletion mode GaN tran-sistor accordingly; wherein each control circuit comprises a current detecting module configured to detect the leakage current of a paired depletion mode GaN transistor and a gate volt-age adjusting module configured to adjust the gate voltage of the paired depletion mode GaN transistor according to the detected leakage current; wherein the gate voltage adjusting module comprises both a voltage source configured to provide a fixed voltage to the gate of the paired depletion mode GaN transistor and a negative voltage converter configured to provide a negative voltage according to the detected current to the gate of the paired depletion mode GaN transistor, wherein the gate voltage of the paired depletion mode GaN transistor is modified by the combination of the fixed voltage of the negative voltage.
The GaN product according to claim 7, wherein each control circuit comprises a controlling module configured to operate both the current detecting module and the gate voltage adjusting module in one or more of the following situations: the paired GaN transistors are operated first time, the paired depletion mode GaN transistors have been oper-ated a certain number of times, the paired depletion mode GaN transistors have been operated for a certain period of time, the paired depletion mode GaN transistors have been operated under an extreme working condition, and an exter-nal Vth calibration command is received.
The GaN product according to claim 7, each control circuit further comprising at least one of the following: the gate voltage adjusting module is configured to make the gate voltage more negative when the detected leakage current is larger than zero; the gate voltage adjusting module is configured to make the gate voltage more positive when the detected leak-age current is zero; and the gate voltage adjusting module is configured to make the gate voltage to be a threshold voltage such that the paired depletion mode GaN transistor has right a zero leakage current.
The GaN product according to claim 7, wherein each control circuit comprises a gate voltage tracking module and configured to track the gate voltage of the paired depletion mode GaN transistor, wherein the gate voltage adjusting module is configured to adjust the gate voltage of the paired depletion mode GaN transistor according to both the detected leakage current and the tracked gate voltage.
The GaN product according to claim 7, wherein the gate voltage adjusting module comprises a negative voltage converter configured to provide a negative voltage less than the tracked gate voltage to the gate of the paired depletion 15 16 mode GaN transistor so as to update the gate voltage of the depletion mode GaN transistor.
The GaN product according to claim 7, wherein the leakage current detecting module comprises an adjustable current mirror for duplicating and enlarging the leakage current such that the gate voltage adjusting module is configured to adjust the gate voltage of the paired depletion mode GaN transistor according to directly an enlarged detected leakage current. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
depletion mode GaN transistor control circuit
depletion mode GaN product
Materials described outside the worked examples.
GaN (depletion mode wafer)
GaN
silicon wafer
Si
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,955,960 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1C are some functional block diagram according to some embodiments of the invention.
FIG. 2B are two schematic diagrams accord- ing to some embodiments of the invention respectively.
FIG. 3F present the features of the proposed invention and the differences from some conventional technologies according to some embodiments of the invention.
FIG. 4B are circuit diagram and timing 40 diagram according to some embodiments respectively.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A depletion mode GaN transistor control circuit, com-prising: a current detecting module formed on a silicon wafer and configured to detect a leakage current of a depletion mode GaN transistor formed on a depletion mode GaN wafer; and 20 a gate voltage adjusting module formed on the silicon wafer and configured to adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current; wherein the gate voltage adjusting module comprises both 25 a voltage source configured to provide a fixed voltage to the gate of the depletion mode GaN transistor and a negative voltage converter configured to provide a negative voltage according to the detected current to the gate of the depletion mode GaN transistor, wherein the gate voltage of the depletion mode GaN transistor is modified by the combination of the fixed voltage and the negative voltage.
The control circuit according to claim 1, further com-prising at least one of the following: the gate voltage adjusting module is configured to make the gate voltage more negative when the detected leakage current is larger than zero; the gate voltage adjusting module is configured to make the gate voltage more positive when the detected leak-age current is zero; and the gate voltage adjusting module is configured to make the gate voltage to be a threshold voltage such that the transistor has just right a zero leakage current.
The control circuit according to claim 1, further com-prising a gate voltage tracking module formed on the silicon wafer and configured to track the gate voltage of the depletion mode GaN transistor, wherein the gate voltage adjusting module is configured to adjust the gate voltage of the depletion mode GaN transistor according to both the detected leakage current and the tracked gate voltage.
The control circuit according to claim 1, wherein the gate voltage adjusting module comprises a negative voltage converter configured to provide a negative voltage less than the tracked gate voltage to the gate of the depletion mode GaN transistor so as to update the gate voltage of the depletion mode GaN transistor.
The control circuit according to claim 1, wherein the leakage current detecting module comprises an adjustable current mirror for duplicating and enlarging the leakage current such that the gate voltage adjusting module is configured to adjust the gate voltage of the depletion mode GaN transistor according to directly an enlarged detected leakage current.
The control circuit according to claim 1, further com-prising a controlling module formed on the silicon wafer and configured to operate both the current detecting module and B₂ the gate voltage adjusting module in one or more of the following situations: the depletion mode GaN transistor is operated first time, the depletion mode GaN transistor has been operated a certain number of times, the depletion mode GaN transistor has been operated for a certain period of time, the depletion mode GaN transistor has been operated under an extreme working condition, and an external Vth calibration command is received.
A depletion mode GaN product, comprising: one or more depletion mode GaN transistors formed on a depletion mode GaN wafer; and one or more control circuits formed on a silicon wafer; wherein the control circuits and the depletion mode GaN transistors are paired one-to-one with each other; wherein each control circuit detects leakage current of a paired depletion mode GaN transistor and then adjusts gate voltage of the paired depletion mode GaN tran-sistor accordingly; wherein each control circuit comprises a current detecting module configured to detect the leakage current of a paired depletion mode GaN transistor and a gate volt-age adjusting module configured to adjust the gate voltage of the paired depletion mode GaN transistor according to the detected leakage current; wherein the gate voltage adjusting module comprises both a voltage source configured to provide a fixed voltage to the gate of the paired depletion mode GaN transistor and a negative voltage converter configured to provide a negative voltage according to the detected current to the gate of the paired depletion mode GaN transistor, wherein the gate voltage of the paired depletion mode GaN transistor is modified by the combination of the fixed voltage of the negative voltage.
The GaN product according to claim 7, wherein each control circuit comprises a controlling module configured to operate both the current detecting module and the gate voltage adjusting module in one or more of the following situations: the paired GaN transistors are operated first time, the paired depletion mode GaN transistors have been oper-ated a certain number of times, the paired depletion mode GaN transistors have been operated for a certain period of time, the paired depletion mode GaN transistors have been operated under an extreme working condition, and an exter-nal Vth calibration command is received.
The GaN product according to claim 7, each control circuit further comprising at least one of the following: the gate voltage adjusting module is configured to make the gate voltage more negative when the detected leakage current is larger than zero; the gate voltage adjusting module is configured to make the gate voltage more positive when the detected leak-age current is zero; and the gate voltage adjusting module is configured to make the gate voltage to be a threshold voltage such that the paired depletion mode GaN transistor has right a zero leakage current.
The GaN product according to claim 7, wherein each control circuit comprises a gate voltage tracking module and configured to track the gate voltage of the paired depletion mode GaN transistor, wherein the gate voltage adjusting module is configured to adjust the gate voltage of the paired depletion mode GaN transistor according to both the detected leakage current and the tracked gate voltage.
The GaN product according to claim 7, wherein the gate voltage adjusting module comprises a negative voltage converter configured to provide a negative voltage less than the tracked gate voltage to the gate of the paired depletion 15 16 mode GaN transistor so as to update the gate voltage of the depletion mode GaN transistor.
The GaN product according to claim 7, wherein the leakage current detecting module comprises an adjustable current mirror for duplicating and enlarging the leakage current such that the gate voltage adjusting module is configured to adjust the gate voltage of the paired depletion mode GaN transistor according to directly an enlarged detected leakage current. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
depletion mode GaN transistor control circuit
depletion mode GaN product
Materials described outside the worked examples.
GaN (depletion mode wafer)
GaN
silicon wafer
Si
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,955,960 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1C are some functional block diagram according to some embodiments of the invention.
FIG. 2B are two schematic diagrams accord- ing to some embodiments of the invention respectively.
FIG. 3F present the features of the proposed invention and the differences from some conventional technologies according to some embodiments of the invention.
FIG. 4B are circuit diagram and timing 40 diagram according to some embodiments respectively.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A depletion mode GaN transistor control circuit, com-prising: a current detecting module formed on a silicon wafer and configured to detect a leakage current of a depletion mode GaN transistor formed on a depletion mode GaN wafer; and 20 a gate voltage adjusting module formed on the silicon wafer and configured to adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current; wherein the gate voltage adjusting module comprises both 25 a voltage source configured to provide a fixed voltage to the gate of the depletion mode GaN transistor and a negative voltage converter configured to provide a negative voltage according to the detected current to the gate of the depletion mode GaN transistor, wherein the gate voltage of the depletion mode GaN transistor is modified by the combination of the fixed voltage and the negative voltage.
The control circuit according to claim 1, further com-prising at least one of the following: the gate voltage adjusting module is configured to make the gate voltage more negative when the detected leakage current is larger than zero; the gate voltage adjusting module is configured to make the gate voltage more positive when the detected leak-age current is zero; and the gate voltage adjusting module is configured to make the gate voltage to be a threshold voltage such that the transistor has just right a zero leakage current.
The control circuit according to claim 1, further com-prising a gate voltage tracking module formed on the silicon wafer and configured to track the gate voltage of the depletion mode GaN transistor, wherein the gate voltage adjusting module is configured to adjust the gate voltage of the depletion mode GaN transistor according to both the detected leakage current and the tracked gate voltage.
The control circuit according to claim 1, wherein the gate voltage adjusting module comprises a negative voltage converter configured to provide a negative voltage less than the tracked gate voltage to the gate of the depletion mode GaN transistor so as to update the gate voltage of the depletion mode GaN transistor.
The control circuit according to claim 1, wherein the leakage current detecting module comprises an adjustable current mirror for duplicating and enlarging the leakage current such that the gate voltage adjusting module is configured to adjust the gate voltage of the depletion mode GaN transistor according to directly an enlarged detected leakage current.
The control circuit according to claim 1, further com-prising a controlling module formed on the silicon wafer and configured to operate both the current detecting module and B₂ the gate voltage adjusting module in one or more of the following situations: the depletion mode GaN transistor is operated first time, the depletion mode GaN transistor has been operated a certain number of times, the depletion mode GaN transistor has been operated for a certain period of time, the depletion mode GaN transistor has been operated under an extreme working condition, and an external Vth calibration command is received.
A depletion mode GaN product, comprising: one or more depletion mode GaN transistors formed on a depletion mode GaN wafer; and one or more control circuits formed on a silicon wafer; wherein the control circuits and the depletion mode GaN transistors are paired one-to-one with each other; wherein each control circuit detects leakage current of a paired depletion mode GaN transistor and then adjusts gate voltage of the paired depletion mode GaN tran-sistor accordingly; wherein each control circuit comprises a current detecting module configured to detect the leakage current of a paired depletion mode GaN transistor and a gate volt-age adjusting module configured to adjust the gate voltage of the paired depletion mode GaN transistor according to the detected leakage current; wherein the gate voltage adjusting module comprises both a voltage source configured to provide a fixed voltage to the gate of the paired depletion mode GaN transistor and a negative voltage converter configured to provide a negative voltage according to the detected current to the gate of the paired depletion mode GaN transistor, wherein the gate voltage of the paired depletion mode GaN transistor is modified by the combination of the fixed voltage of the negative voltage.
The GaN product according to claim 7, wherein each control circuit comprises a controlling module configured to operate both the current detecting module and the gate voltage adjusting module in one or more of the following situations: the paired GaN transistors are operated first time, the paired depletion mode GaN transistors have been oper-ated a certain number of times, the paired depletion mode GaN transistors have been operated for a certain period of time, the paired depletion mode GaN transistors have been operated under an extreme working condition, and an exter-nal Vth calibration command is received.
The GaN product according to claim 7, each control circuit further comprising at least one of the following: the gate voltage adjusting module is configured to make the gate voltage more negative when the detected leakage current is larger than zero; the gate voltage adjusting module is configured to make the gate voltage more positive when the detected leak-age current is zero; and the gate voltage adjusting module is configured to make the gate voltage to be a threshold voltage such that the paired depletion mode GaN transistor has right a zero leakage current.
The GaN product according to claim 7, wherein each control circuit comprises a gate voltage tracking module and configured to track the gate voltage of the paired depletion mode GaN transistor, wherein the gate voltage adjusting module is configured to adjust the gate voltage of the paired depletion mode GaN transistor according to both the detected leakage current and the tracked gate voltage.
The GaN product according to claim 7, wherein the gate voltage adjusting module comprises a negative voltage converter configured to provide a negative voltage less than the tracked gate voltage to the gate of the paired depletion 15 16 mode GaN transistor so as to update the gate voltage of the depletion mode GaN transistor.
The GaN product according to claim 7, wherein the leakage current detecting module comprises an adjustable current mirror for duplicating and enlarging the leakage current such that the gate voltage adjusting module is configured to adjust the gate voltage of the paired depletion mode GaN transistor according to directly an enlarged detected leakage current. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
depletion mode GaN transistor control circuit
depletion mode GaN product
Materials described outside the worked examples.
GaN (depletion mode wafer)
GaN
silicon wafer
Si
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
