(C urrently Amended) A high elect r on m obility transistor..._E;MT) comprising: a high resistivity semiconductor layer on a substrate; t barri er semico nduc tor l ay er on and distinct r om sad high resistivity semiconductor layer opposite said substrate, said barrier semiconductor layer comprising awider bndg. p t an said high resistivity semiconductor layer; semicond uc tor layer and said high resistivity semiconductor layer; respective source and drain contacts contacting said barrier setimiconduictor _aye; an insulating region (on said brir emcdutr layer opposite said hig resistiviy semiconductor layer, saicd insulating region comprising. bottom spacer.ayer and a top insulating layer on and distinct from said bottom spacer layer, whe 'i:re° in _. sid, top.4ins..u l.at1 _ing layer comprises a. first material comprising silicon, an...'d w'"heN rein saiy nontom spacer layer comprises a second material without silicon, wherein said betwiee and in con tct wih ad ouc cntc and said dnuaiarao ri contact; and SVG 12554803.10-03-2018.JMTSH₉MLRXEAPX5.CLM.2.svg 0.15 1.16 Black and white 2, i A₁₂/5, i 4 0 3 a gate contact o n said insulating region, said insulating region for m ing a b arrier to a cate leakage. current, wherein said ins u lat in g region cove rs and c ontacts the surface of said barrier layer b etween said source and drain conta cts, Currently amended

. The HEMT of clai mn 1, wherein said om spacer layer comprises aluminum d...........e (IN) and said t op inulat",ing -aye comprises silicon nitride (SiN), silicon d iox ide ia), or multipl e layers t h ereo r

5, (P rev iously Presented) The HEMT of.a.imi, wnerein sa op insulating layer comprise a layer of silicon nitride. Previously presented

The HEM T of c laim. i, wherein said t op insulating l aye r co mp rises a lay er o f si.l1icon nitride and said bottom space r layer com prises a lay er of aluminum nitride. Previously presented

8, A high electron mobility transistor (HEMT), comprising: a GaN semiconductor layer; Page 3 of 1 7 Ap No..U/554 J₈C₃ Rescpne t.' 'ina Off ic e A L'ion 10 May 4, 2 an Alt SaN semiconductor b arrier laver on said GaN semiconductor layer; a two dim ens ional elect ron (gas bt. w e.en ai " iAN semiconductor barrier layer and said GaN semiconductor layer; source and drain contacts contacting said A ' "N semiconduct or barrier layer; a gate contact in el ect rostatic C mwith said barrier layer, wherein f-:aid--gate contact is not directly on said barrier layer; a first insulating portion adjacent said AlGaN semiconductor barrier layer and between said suc and d rai n contacts; and Second insulating portion on and distinct from said fi s facing said source and drain contacts, _ wherein _ said _{_} AlGaN csemicodut r barrier Ae d sultin \ortion and sai scon isultia orton are between and in contact with said source contact and said drain co ntact. Currently amended

(Currently A mended) A transistor, comprising: a high resistivity semiconductor l ay er; a barrier semiconductor la y er on and distinct fro m said high resist ivit y layer; a two dimensional electron ga s between said barrier semiconductor layer and said hi g h resistivity sem i conductor l ayer; source and drain contacts contacting said barrier semiconductor l ayer; an insulating region on said barrier semi conducto r layer between said source and drain contacts com p rising a fi rst portion an d a second portion, said first p ortion being d i stinct from said second po rtion, wherein said barrier semiconductor le ver and s aid i nsu las tin c re g ion are bet ween and in conta c t with said source cont act and said drain contact; and a gate c ont act on said first portion, said first p ortion f orm i ng a barrier to gate leakage current; wherein said second portion is on said first p ortion a nd contacts portions of said gate contact facin g said source an d drain contacts, said g ate contact within an aperture i n said second p ortion, Currently amended

(C urre ntly Am ended) A high electron mobility transistor (H EMT), comprising: a high resistivity semiconductor layer; a b arr i er semiconduc tor layer on said hi g h resist ivity layer t h rough thermal decomposition,_ said barri er la yer dis tinct f rom s aid hig h resistivit y semiconductor la v er; a mu lti-layer insulating layer comprisi ng a bottom material without si l icon and a top material comprising silicon, said bottom material being distinct from said top mater ial, s aid bottom and top materials grown on said barrier semicon ductor layer, said bottom materia l b etween said top materi al and said b arr i er semiconductor l ayer; respective source and drain contacts contacting sa id barrie r semi c onductor layer, wherein said barrier s e miconductor layer and said mui-tilaver insuiatinc la y er are between said. source contact and said drain contact; and a gate contact on said top layer of said multi -layer i nsulat i ng layer, said multi-layer insulating layer forming a barrier to gate leaka g e current, w herein said insul ating region cove r s and contacts t h e surface of said barrier layer between said source and drain contacts, Currently amended

27- 33. (Can celed) Canceled

Canceled

37, (Previous ly Pr esented) The transistor of ca 8, wnerain said source and drain contacts are in direct contact with said AlGaN l.ayer and said G aN la yar Previously presented

The transistor of cla im 12, w h ere in said source and drain contacts are in drect contact with said barrier layer and said hi gh- rns istivity layer, SVG 12554803.10-03-2018.JMTSH₉MLRXEAPX5.CLM.4.svg 0.16 1.3 Black and white App, No, 12/55-', EM R na iceAction c f May 4, 20I Previously presented

Canceled) Canceled

(Pr evi ously Presented) The HEMT of cla im A, w herein sa id bottom spacer layer se p arates said top insulatin g layer f rom said barrier sem i conductor layer. Previously presented

The HEM T of clai m 40, wherein at least one of said bottom spacer sayer and said top insulating layer extends from said source contact to said drain contact. Previously presented

The HEMT of clai ma 1, wherein at least one of said bottom spacer layer a ndc said top insulating layer extends f rom said source contact to sa id drain contact, Previously presented

43. Canceled

The transistor of clai ma 12, wherein said first portion separates said second portion from said barrier layer, Previously presented

Page 8 o f 17 Recspcon se Dat ed:c. 'beI..01 Canceled

(Previous ly Presented) T he HE MT of cl aim 22, wherein said bottom mate ria. sepa rate s said to p material an d said barrier semiconductor layer. Previously presented

T h~e HETo cam22 hrena least o ne of said bottom material and s aid t op ma ter ial extends f rom sai d source contact t o sai d d rain cont act. Previously presented

(C urrently Amended) A high elect r on m obility transistor..._E;MT) comprising: a high resistivity semiconductor layer on a substrate; t barri er semico nduc tor l ay er on and distinct r om sad high resistivity semiconductor layer opposite said substrate, said barrier semiconductor layer comprising awider bndg. p t an said high resistivity semiconductor layer; semicond uc tor layer and said high resistivity semiconductor layer; respective source and drain contacts contacting said barrier setimiconduictor _aye; an insulating region (on said brir emcdutr layer opposite said hig resistiviy semiconductor layer, saicd insulating region comprising. bottom spacer.ayer and a top insulating layer on and distinct from said bottom spacer layer, whe 'i:re° in _. sid, top.4ins..u l.at1 _ing layer comprises a. first material comprising silicon, an...'d w'"heN rein saiy nontom spacer layer comprises a second material without silicon, wherein said betwiee and in con tct wih ad ouc cntc and said dnuaiarao ri contact; and SVG 12554803.10-03-2018.JMTSH₉MLRXEAPX5.CLM.2.svg 0.15 1.16 Black and white 2, i A₁₂/5, i 4 0 3 a gate contact o n said insulating region, said insulating region for m ing a b arrier to a cate leakage. current, wherein said ins u lat in g region cove rs and c ontacts the surface of said barrier layer b etween said source and drain conta cts, Currently amended

. The HEMT of clai mn 1, wherein said om spacer layer comprises aluminum d...........e (IN) and said t op inulat",ing -aye comprises silicon nitride (SiN), silicon d iox ide ia), or multipl e layers t h ereo r

5, (P rev iously Presented) The HEMT of.a.imi, wnerein sa op insulating layer comprise a layer of silicon nitride. Previously presented

The HEM T of c laim. i, wherein said t op insulating l aye r co mp rises a lay er o f si.l1icon nitride and said bottom space r layer com prises a lay er of aluminum nitride. Previously presented

8, A high electron mobility transistor (HEMT), comprising: a GaN semiconductor layer; Page 3 of 1 7 Ap No..U/554 J₈C₃ Rescpne t.' 'ina Off ic e A L'ion 10 May 4, 2 an Alt SaN semiconductor b arrier laver on said GaN semiconductor layer; a two dim ens ional elect ron (gas bt. w e.en ai " iAN semiconductor barrier layer and said GaN semiconductor layer; source and drain contacts contacting said A ' "N semiconduct or barrier layer; a gate contact in el ect rostatic C mwith said barrier layer, wherein f-:aid--gate contact is not directly on said barrier layer; a first insulating portion adjacent said AlGaN semiconductor barrier layer and between said suc and d rai n contacts; and Second insulating portion on and distinct from said fi s facing said source and drain contacts, _ wherein _ said _{_} AlGaN csemicodut r barrier Ae d sultin \ortion and sai scon isultia orton are between and in contact with said source contact and said drain co ntact. Currently amended

(Currently A mended) A transistor, comprising: a high resistivity semiconductor l ay er; a barrier semiconductor la y er on and distinct fro m said high resist ivit y layer; a two dimensional electron ga s between said barrier semiconductor layer and said hi g h resistivity sem i conductor l ayer; source and drain contacts contacting said barrier semiconductor l ayer; an insulating region on said barrier semi conducto r layer between said source and drain contacts com p rising a fi rst portion an d a second portion, said first p ortion being d i stinct from said second po rtion, wherein said barrier semiconductor le ver and s aid i nsu las tin c re g ion are bet ween and in conta c t with said source cont act and said drain contact; and a gate c ont act on said first portion, said first p ortion f orm i ng a barrier to gate leakage current; wherein said second portion is on said first p ortion a nd contacts portions of said gate contact facin g said source an d drain contacts, said g ate contact within an aperture i n said second p ortion, Currently amended

(C urre ntly Am ended) A high electron mobility transistor (H EMT), comprising: a high resistivity semiconductor layer; a b arr i er semiconduc tor layer on said hi g h resist ivity layer t h rough thermal decomposition,_ said barri er la yer dis tinct f rom s aid hig h resistivit y semiconductor la v er; a mu lti-layer insulating layer comprisi ng a bottom material without si l icon and a top material comprising silicon, said bottom material being distinct from said top mater ial, s aid bottom and top materials grown on said barrier semicon ductor layer, said bottom materia l b etween said top materi al and said b arr i er semiconductor l ayer; respective source and drain contacts contacting sa id barrie r semi c onductor layer, wherein said barrier s e miconductor layer and said mui-tilaver insuiatinc la y er are between said. source contact and said drain contact; and a gate contact on said top layer of said multi -layer i nsulat i ng layer, said multi-layer insulating layer forming a barrier to gate leaka g e current, w herein said insul ating region cove r s and contacts t h e surface of said barrier layer between said source and drain contacts, Currently amended

27- 33. (Can celed) Canceled

Canceled

37, (Previous ly Pr esented) The transistor of ca 8, wnerain said source and drain contacts are in direct contact with said AlGaN l.ayer and said G aN la yar Previously presented

The transistor of cla im 12, w h ere in said source and drain contacts are in drect contact with said barrier layer and said hi gh- rns istivity layer, SVG 12554803.10-03-2018.JMTSH₉MLRXEAPX5.CLM.4.svg 0.16 1.3 Black and white App, No, 12/55-', EM R na iceAction c f May 4, 20I Previously presented

Canceled) Canceled

(Pr evi ously Presented) The HEMT of cla im A, w herein sa id bottom spacer layer se p arates said top insulatin g layer f rom said barrier sem i conductor layer. Previously presented

The HEM T of clai m 40, wherein at least one of said bottom spacer sayer and said top insulating layer extends from said source contact to said drain contact. Previously presented

The HEMT of clai ma 1, wherein at least one of said bottom spacer layer a ndc said top insulating layer extends f rom said source contact to sa id drain contact, Previously presented

43. Canceled

The transistor of clai ma 12, wherein said first portion separates said second portion from said barrier layer, Previously presented

Page 8 o f 17 Recspcon se Dat ed:c. 'beI..01 Canceled

(Previous ly Presented) T he HE MT of cl aim 22, wherein said bottom mate ria. sepa rate s said to p material an d said barrier semiconductor layer. Previously presented

T h~e HETo cam22 hrena least o ne of said bottom material and s aid t op ma ter ial extends f rom sai d source contact t o sai d d rain cont act. Previously presented

(C urrently Amended) A high elect r on m obility transistor..._E;MT) comprising: a high resistivity semiconductor layer on a substrate; t barri er semico nduc tor l ay er on and distinct r om sad high resistivity semiconductor layer opposite said substrate, said barrier semiconductor layer comprising awider bndg. p t an said high resistivity semiconductor layer; semicond uc tor layer and said high resistivity semiconductor layer; respective source and drain contacts contacting said barrier setimiconduictor _aye; an insulating region (on said brir emcdutr layer opposite said hig resistiviy semiconductor layer, saicd insulating region comprising. bottom spacer.ayer and a top insulating layer on and distinct from said bottom spacer layer, whe 'i:re° in _. sid, top.4ins..u l.at1 _ing layer comprises a. first material comprising silicon, an...'d w'"heN rein saiy nontom spacer layer comprises a second material without silicon, wherein said betwiee and in con tct wih ad ouc cntc and said dnuaiarao ri contact; and SVG 12554803.10-03-2018.JMTSH₉MLRXEAPX5.CLM.2.svg 0.15 1.16 Black and white 2, i A₁₂/5, i 4 0 3 a gate contact o n said insulating region, said insulating region for m ing a b arrier to a cate leakage. current, wherein said ins u lat in g region cove rs and c ontacts the surface of said barrier layer b etween said source and drain conta cts, Currently amended

. The HEMT of clai mn 1, wherein said om spacer layer comprises aluminum d...........e (IN) and said t op inulat",ing -aye comprises silicon nitride (SiN), silicon d iox ide ia), or multipl e layers t h ereo r

5, (P rev iously Presented) The HEMT of.a.imi, wnerein sa op insulating layer comprise a layer of silicon nitride. Previously presented

The HEM T of c laim. i, wherein said t op insulating l aye r co mp rises a lay er o f si.l1icon nitride and said bottom space r layer com prises a lay er of aluminum nitride. Previously presented

8, A high electron mobility transistor (HEMT), comprising: a GaN semiconductor layer; Page 3 of 1 7 Ap No..U/554 J₈C₃ Rescpne t.' 'ina Off ic e A L'ion 10 May 4, 2 an Alt SaN semiconductor b arrier laver on said GaN semiconductor layer; a two dim ens ional elect ron (gas bt. w e.en ai " iAN semiconductor barrier layer and said GaN semiconductor layer; source and drain contacts contacting said A ' "N semiconduct or barrier layer; a gate contact in el ect rostatic C mwith said barrier layer, wherein f-:aid--gate contact is not directly on said barrier layer; a first insulating portion adjacent said AlGaN semiconductor barrier layer and between said suc and d rai n contacts; and Second insulating portion on and distinct from said fi s facing said source and drain contacts, _ wherein _ said _{_} AlGaN csemicodut r barrier Ae d sultin \ortion and sai scon isultia orton are between and in contact with said source contact and said drain co ntact. Currently amended

(Currently A mended) A transistor, comprising: a high resistivity semiconductor l ay er; a barrier semiconductor la y er on and distinct fro m said high resist ivit y layer; a two dimensional electron ga s between said barrier semiconductor layer and said hi g h resistivity sem i conductor l ayer; source and drain contacts contacting said barrier semiconductor l ayer; an insulating region on said barrier semi conducto r layer between said source and drain contacts com p rising a fi rst portion an d a second portion, said first p ortion being d i stinct from said second po rtion, wherein said barrier semiconductor le ver and s aid i nsu las tin c re g ion are bet ween and in conta c t with said source cont act and said drain contact; and a gate c ont act on said first portion, said first p ortion f orm i ng a barrier to gate leakage current; wherein said second portion is on said first p ortion a nd contacts portions of said gate contact facin g said source an d drain contacts, said g ate contact within an aperture i n said second p ortion, Currently amended

(C urre ntly Am ended) A high electron mobility transistor (H EMT), comprising: a high resistivity semiconductor layer; a b arr i er semiconduc tor layer on said hi g h resist ivity layer t h rough thermal decomposition,_ said barri er la yer dis tinct f rom s aid hig h resistivit y semiconductor la v er; a mu lti-layer insulating layer comprisi ng a bottom material without si l icon and a top material comprising silicon, said bottom material being distinct from said top mater ial, s aid bottom and top materials grown on said barrier semicon ductor layer, said bottom materia l b etween said top materi al and said b arr i er semiconductor l ayer; respective source and drain contacts contacting sa id barrie r semi c onductor layer, wherein said barrier s e miconductor layer and said mui-tilaver insuiatinc la y er are between said. source contact and said drain contact; and a gate contact on said top layer of said multi -layer i nsulat i ng layer, said multi-layer insulating layer forming a barrier to gate leaka g e current, w herein said insul ating region cove r s and contacts t h e surface of said barrier layer between said source and drain contacts, Currently amended

27- 33. (Can celed) Canceled

Canceled

37, (Previous ly Pr esented) The transistor of ca 8, wnerain said source and drain contacts are in direct contact with said AlGaN l.ayer and said G aN la yar Previously presented

The transistor of cla im 12, w h ere in said source and drain contacts are in drect contact with said barrier layer and said hi gh- rns istivity layer, SVG 12554803.10-03-2018.JMTSH₉MLRXEAPX5.CLM.4.svg 0.16 1.3 Black and white App, No, 12/55-', EM R na iceAction c f May 4, 20I Previously presented

Canceled) Canceled

(Pr evi ously Presented) The HEMT of cla im A, w herein sa id bottom spacer layer se p arates said top insulatin g layer f rom said barrier sem i conductor layer. Previously presented

The HEM T of clai m 40, wherein at least one of said bottom spacer sayer and said top insulating layer extends from said source contact to said drain contact. Previously presented

The HEMT of clai ma 1, wherein at least one of said bottom spacer layer a ndc said top insulating layer extends f rom said source contact to sa id drain contact, Previously presented

43. Canceled

The transistor of clai ma 12, wherein said first portion separates said second portion from said barrier layer, Previously presented

Page 8 o f 17 Recspcon se Dat ed:c. 'beI..01 Canceled

(Previous ly Presented) T he HE MT of cl aim 22, wherein said bottom mate ria. sepa rate s said to p material an d said barrier semiconductor layer. Previously presented

T h~e HETo cam22 hrena least o ne of said bottom material and s aid t op ma ter ial extends f rom sai d source contact t o sai d d rain cont act. Previously presented

(C urrently Amended) A high elect r on m obility transistor..._E;MT) comprising: a high resistivity semiconductor layer on a substrate; t barri er semico nduc tor l ay er on and distinct r om sad high resistivity semiconductor layer opposite said substrate, said barrier semiconductor layer comprising awider bndg. p t an said high resistivity semiconductor layer; semicond uc tor layer and said high resistivity semiconductor layer; respective source and drain contacts contacting said barrier setimiconduictor _aye; an insulating region (on said brir emcdutr layer opposite said hig resistiviy semiconductor layer, saicd insulating region comprising. bottom spacer.ayer and a top insulating layer on and distinct from said bottom spacer layer, whe 'i:re° in _. sid, top.4ins..u l.at1 _ing layer comprises a. first material comprising silicon, an...'d w'"heN rein saiy nontom spacer layer comprises a second material without silicon, wherein said betwiee and in con tct wih ad ouc cntc and said dnuaiarao ri contact; and SVG 12554803.10-03-2018.JMTSH₉MLRXEAPX5.CLM.2.svg 0.15 1.16 Black and white 2, i A₁₂/5, i 4 0 3 a gate contact o n said insulating region, said insulating region for m ing a b arrier to a cate leakage. current, wherein said ins u lat in g region cove rs and c ontacts the surface of said barrier layer b etween said source and drain conta cts, Currently amended

. The HEMT of clai mn 1, wherein said om spacer layer comprises aluminum d...........e (IN) and said t op inulat",ing -aye comprises silicon nitride (SiN), silicon d iox ide ia), or multipl e layers t h ereo r

5, (P rev iously Presented) The HEMT of.a.imi, wnerein sa op insulating layer comprise a layer of silicon nitride. Previously presented

The HEM T of c laim. i, wherein said t op insulating l aye r co mp rises a lay er o f si.l1icon nitride and said bottom space r layer com prises a lay er of aluminum nitride. Previously presented

8, A high electron mobility transistor (HEMT), comprising: a GaN semiconductor layer; Page 3 of 1 7 Ap No..U/554 J₈C₃ Rescpne t.' 'ina Off ic e A L'ion 10 May 4, 2 an Alt SaN semiconductor b arrier laver on said GaN semiconductor layer; a two dim ens ional elect ron (gas bt. w e.en ai " iAN semiconductor barrier layer and said GaN semiconductor layer; source and drain contacts contacting said A ' "N semiconduct or barrier layer; a gate contact in el ect rostatic C mwith said barrier layer, wherein f-:aid--gate contact is not directly on said barrier layer; a first insulating portion adjacent said AlGaN semiconductor barrier layer and between said suc and d rai n contacts; and Second insulating portion on and distinct from said fi s facing said source and drain contacts, _ wherein _ said _{_} AlGaN csemicodut r barrier Ae d sultin \ortion and sai scon isultia orton are between and in contact with said source contact and said drain co ntact. Currently amended

(Currently A mended) A transistor, comprising: a high resistivity semiconductor l ay er; a barrier semiconductor la y er on and distinct fro m said high resist ivit y layer; a two dimensional electron ga s between said barrier semiconductor layer and said hi g h resistivity sem i conductor l ayer; source and drain contacts contacting said barrier semiconductor l ayer; an insulating region on said barrier semi conducto r layer between said source and drain contacts com p rising a fi rst portion an d a second portion, said first p ortion being d i stinct from said second po rtion, wherein said barrier semiconductor le ver and s aid i nsu las tin c re g ion are bet ween and in conta c t with said source cont act and said drain contact; and a gate c ont act on said first portion, said first p ortion f orm i ng a barrier to gate leakage current; wherein said second portion is on said first p ortion a nd contacts portions of said gate contact facin g said source an d drain contacts, said g ate contact within an aperture i n said second p ortion, Currently amended

(C urre ntly Am ended) A high electron mobility transistor (H EMT), comprising: a high resistivity semiconductor layer; a b arr i er semiconduc tor layer on said hi g h resist ivity layer t h rough thermal decomposition,_ said barri er la yer dis tinct f rom s aid hig h resistivit y semiconductor la v er; a mu lti-layer insulating layer comprisi ng a bottom material without si l icon and a top material comprising silicon, said bottom material being distinct from said top mater ial, s aid bottom and top materials grown on said barrier semicon ductor layer, said bottom materia l b etween said top materi al and said b arr i er semiconductor l ayer; respective source and drain contacts contacting sa id barrie r semi c onductor layer, wherein said barrier s e miconductor layer and said mui-tilaver insuiatinc la y er are between said. source contact and said drain contact; and a gate contact on said top layer of said multi -layer i nsulat i ng layer, said multi-layer insulating layer forming a barrier to gate leaka g e current, w herein said insul ating region cove r s and contacts t h e surface of said barrier layer between said source and drain contacts, Currently amended

27- 33. (Can celed) Canceled

Canceled

37, (Previous ly Pr esented) The transistor of ca 8, wnerain said source and drain contacts are in direct contact with said AlGaN l.ayer and said G aN la yar Previously presented

The transistor of cla im 12, w h ere in said source and drain contacts are in drect contact with said barrier layer and said hi gh- rns istivity layer, SVG 12554803.10-03-2018.JMTSH₉MLRXEAPX5.CLM.4.svg 0.16 1.3 Black and white App, No, 12/55-', EM R na iceAction c f May 4, 20I Previously presented

Canceled) Canceled

(Pr evi ously Presented) The HEMT of cla im A, w herein sa id bottom spacer layer se p arates said top insulatin g layer f rom said barrier sem i conductor layer. Previously presented

The HEM T of clai m 40, wherein at least one of said bottom spacer sayer and said top insulating layer extends from said source contact to said drain contact. Previously presented

The HEMT of clai ma 1, wherein at least one of said bottom spacer layer a ndc said top insulating layer extends f rom said source contact to sa id drain contact, Previously presented

43. Canceled

The transistor of clai ma 12, wherein said first portion separates said second portion from said barrier layer, Previously presented

Page 8 o f 17 Recspcon se Dat ed:c. 'beI..01 Canceled

(Previous ly Presented) T he HE MT of cl aim 22, wherein said bottom mate ria. sepa rate s said to p material an d said barrier semiconductor layer. Previously presented

T h~e HETo cam22 hrena least o ne of said bottom material and s aid t op ma ter ial extends f rom sai d source contact t o sai d d rain cont act. Previously presented