Patent
US 8,624,223SIDE-GATE DEFINED TUNABLE NANOCONSTRICTION IN DOUBLE-GATED GRAPHENE MULTILAYERS
Ching-tzu CHEN, Shu-Jen HAN
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a first step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a back gate dielectric layer for forming a …
FIG. 2 is a second step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating source/drain electrodes and side-gate …
FIG. 3 is a third step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating grpahense channel and spacers for forming a …
FIG. 4 is a fourth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating top gate dielectric material for forming a …
FIG. 5 is a fifth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a top gate electrode for forming a graphene …
FIG. 6 is a schematic band diagram of the device in
FIG. 7(B) is a simulation of the device in
FIGS. 8-11 are a series of schematic alternative device configurations of the device in
FIG. 9 illustrates an asymmetrical channel geometry with a leftside gate 927 similar to the leftside 827 of
FIG. 10 has symmetrical channel geometry with a leftside gate 1027 and rightside gate 1028 illustrating a more pointed shape as compared with
FIG. 11 illustrates symmetrical channel geometry with triangular top 1127 and 1128. The asymmetric variations of
FIG. 12 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A non-transitory tangible computer readable medium encoded with a program for fabricating an integrated circuit structure, the program comprising instructions for performing the steps of: forming a back-gate dielectric layer over a conductive substrate; forming a graphene layer over the back-gate dielectric layer; forming a plurality of contacts over a portion of the graphene layer including at least one source contact, at least one drain contact, and at least one side-gate contact; forming in the graphene layer [[in]] between the side-gat e at least one source contact, the seure e at least one drain contact[[,]] and the drai at least one side-gate contact, a graphene channel with graphene side gates; forming a top-gate dielectric layer over the graphene layer; and forming a top-gate electrode over the graphene channel.
The non-transitory tangible computer readable medium of claim 1, wherein the forming [[the]] a plurality of contacts includes forming a set of side-gate contacts, and wherein the forming the a graphene channel with g r aphene side gates includes forming the graphene channel with graphene side gates [[in]] between the set of side-gate contacts.
The non-transitory tangible computer readable medium of claim 1, wherein the graphene side gates ean-ale-be are formed by any conducting material material.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an AB-stacked bi-layer graphene layer.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an ABC-stacked t ri -layer graphene layer.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an-A-BCstaeked a stacked few-layer graphene layer.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an AB-stacked bi-layer, an ABC-stacked tri -layer or an ABC-stacked few layer graphene layer with stacking miso r ientation.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene channel and wit h graphene side gates are-femed includes using oxygen reactive-ion etching (R EI).
The non-transitory tangible computer readable medium of claim 1, wherein the forming [[the]] a back-gate dielectric layer over a-silieen the conductive substrate includes forming [[a]] t he back-gate dielectric layer with a thin layer of hexagonal boron nitride SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.1.svg 0.15 6.5 Black and white eemi t a combination thereof.
The non-transitory tangible computer readable medium of claim 1, SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.2.svg 0.15 6.18 Black and white itide- SiOx, SiNx, BNx, HfOx, AlOx, lead zirconate -PZT, any dielectric matea- material, or a combination thereof. SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.3.svg 0.16 6.05 Black and white
The graphene-based nanoconstriction device of claim 1, wherein the graphene-based electronic nanoconstriction device is gate tunable.
The non-transitory tangible computer readable medium of claim 1, wherein the conductive substrate includes a highly doped silicon substrate.
The non-transitory tangible computer readable medium of claim 1, wherein the integrated circuit structure is a gate tunable graphene-based electronic nanoconstriction device. 8 of 13 App l. No. 13/668,401 Docket No. Y O R₉₂₀₁₂₀₂₆₅US₂ Reply to Office Action of
, wherein the plurality of contacts includes a set of side-gate contactsand wherein the graphene channel is [[in]] between the set of side-gate contacts. SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.6.svg 0.16 6.38 Black and white
Layer stacks claimed or described, ordered top of device to substrate.
gate-tunable graphene-based electronic nanoconstriction device
Materials described outside the worked examples.
graphene
back-gate dielectric
top-gate dielectric
AB-stacked bi-layer graphene
ABC-stacked tri-layer graphene
stacked few-layer graphene
hexagonal boron nitride
h-BN
top-gate dielectric materials including SiOx, SiNx, BNx, HfOx, AlOx, lead zirconate titanate (PZT)
highly doped silicon substrate
lead zirconate titanate (PZT) back-gate dielectric
PZT
titanium contacts
Ti
gold contacts
Au
palladium contacts
Pd
platinum contacts
Pt
PMMA etch mask
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a first step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a back gate dielectric layer for forming a …
FIG. 3 is a third step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating grpahense channel and spacers for forming a …
FIG. 4 is a fourth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating top gate dielectric material for forming a …
FIG. 5 is a fifth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a top gate electrode for forming a graphene …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–200 nm | — |
Thickness | 50–100 nm | — |
LASER FORMATION OF GRAPHENE
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a first step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a back gate dielectric layer for forming a …
FIG. 2 is a second step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating source/drain electrodes and side-gate …
FIG. 3 is a third step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating grpahense channel and spacers for forming a …
FIG. 4 is a fourth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating top gate dielectric material for forming a …
FIG. 5 is a fifth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a top gate electrode for forming a graphene …
FIG. 6 is a schematic band diagram of the device in
FIG. 7(B) is a simulation of the device in
FIGS. 8-11 are a series of schematic alternative device configurations of the device in
FIG. 9 illustrates an asymmetrical channel geometry with a leftside gate 927 similar to the leftside 827 of
FIG. 10 has symmetrical channel geometry with a leftside gate 1027 and rightside gate 1028 illustrating a more pointed shape as compared with
FIG. 11 illustrates symmetrical channel geometry with triangular top 1127 and 1128. The asymmetric variations of
FIG. 12 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A non-transitory tangible computer readable medium encoded with a program for fabricating an integrated circuit structure, the program comprising instructions for performing the steps of: forming a back-gate dielectric layer over a conductive substrate; forming a graphene layer over the back-gate dielectric layer; forming a plurality of contacts over a portion of the graphene layer including at least one source contact, at least one drain contact, and at least one side-gate contact; forming in the graphene layer [[in]] between the side-gat e at least one source contact, the seure e at least one drain contact[[,]] and the drai at least one side-gate contact, a graphene channel with graphene side gates; forming a top-gate dielectric layer over the graphene layer; and forming a top-gate electrode over the graphene channel.
The non-transitory tangible computer readable medium of claim 1, wherein the forming [[the]] a plurality of contacts includes forming a set of side-gate contacts, and wherein the forming the a graphene channel with g r aphene side gates includes forming the graphene channel with graphene side gates [[in]] between the set of side-gate contacts.
The non-transitory tangible computer readable medium of claim 1, wherein the graphene side gates ean-ale-be are formed by any conducting material material.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an AB-stacked bi-layer graphene layer.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an ABC-stacked t ri -layer graphene layer.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an-A-BCstaeked a stacked few-layer graphene layer.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an AB-stacked bi-layer, an ABC-stacked tri -layer or an ABC-stacked few layer graphene layer with stacking miso r ientation.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene channel and wit h graphene side gates are-femed includes using oxygen reactive-ion etching (R EI).
The non-transitory tangible computer readable medium of claim 1, wherein the forming [[the]] a back-gate dielectric layer over a-silieen the conductive substrate includes forming [[a]] t he back-gate dielectric layer with a thin layer of hexagonal boron nitride SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.1.svg 0.15 6.5 Black and white eemi t a combination thereof.
The non-transitory tangible computer readable medium of claim 1, SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.2.svg 0.15 6.18 Black and white itide- SiOx, SiNx, BNx, HfOx, AlOx, lead zirconate -PZT, any dielectric matea- material, or a combination thereof. SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.3.svg 0.16 6.05 Black and white
The graphene-based nanoconstriction device of claim 1, wherein the graphene-based electronic nanoconstriction device is gate tunable.
The non-transitory tangible computer readable medium of claim 1, wherein the conductive substrate includes a highly doped silicon substrate.
The non-transitory tangible computer readable medium of claim 1, wherein the integrated circuit structure is a gate tunable graphene-based electronic nanoconstriction device. 8 of 13 App l. No. 13/668,401 Docket No. Y O R₉₂₀₁₂₀₂₆₅US₂ Reply to Office Action of
, wherein the plurality of contacts includes a set of side-gate contactsand wherein the graphene channel is [[in]] between the set of side-gate contacts. SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.6.svg 0.16 6.38 Black and white
Layer stacks claimed or described, ordered top of device to substrate.
gate-tunable graphene-based electronic nanoconstriction device
Materials described outside the worked examples.
graphene
back-gate dielectric
top-gate dielectric
AB-stacked bi-layer graphene
ABC-stacked tri-layer graphene
stacked few-layer graphene
hexagonal boron nitride
h-BN
top-gate dielectric materials including SiOx, SiNx, BNx, HfOx, AlOx, lead zirconate titanate (PZT)
highly doped silicon substrate
lead zirconate titanate (PZT) back-gate dielectric
PZT
titanium contacts
Ti
gold contacts
Au
palladium contacts
Pd
platinum contacts
Pt
PMMA etch mask
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a first step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a back gate dielectric layer for forming a …
FIG. 3 is a third step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating grpahense channel and spacers for forming a …
FIG. 4 is a fourth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating top gate dielectric material for forming a …
FIG. 5 is a fifth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a top gate electrode for forming a graphene …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–200 nm | — |
Thickness | 50–100 nm | — |
LASER FORMATION OF GRAPHENE
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a first step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a back gate dielectric layer for forming a …
FIG. 2 is a second step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating source/drain electrodes and side-gate …
FIG. 3 is a third step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating grpahense channel and spacers for forming a …
FIG. 4 is a fourth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating top gate dielectric material for forming a …
FIG. 5 is a fifth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a top gate electrode for forming a graphene …
FIG. 6 is a schematic band diagram of the device in
FIG. 7(B) is a simulation of the device in
FIGS. 8-11 are a series of schematic alternative device configurations of the device in
FIG. 9 illustrates an asymmetrical channel geometry with a leftside gate 927 similar to the leftside 827 of
FIG. 10 has symmetrical channel geometry with a leftside gate 1027 and rightside gate 1028 illustrating a more pointed shape as compared with
FIG. 11 illustrates symmetrical channel geometry with triangular top 1127 and 1128. The asymmetric variations of
FIG. 12 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A non-transitory tangible computer readable medium encoded with a program for fabricating an integrated circuit structure, the program comprising instructions for performing the steps of: forming a back-gate dielectric layer over a conductive substrate; forming a graphene layer over the back-gate dielectric layer; forming a plurality of contacts over a portion of the graphene layer including at least one source contact, at least one drain contact, and at least one side-gate contact; forming in the graphene layer [[in]] between the side-gat e at least one source contact, the seure e at least one drain contact[[,]] and the drai at least one side-gate contact, a graphene channel with graphene side gates; forming a top-gate dielectric layer over the graphene layer; and forming a top-gate electrode over the graphene channel.
The non-transitory tangible computer readable medium of claim 1, wherein the forming [[the]] a plurality of contacts includes forming a set of side-gate contacts, and wherein the forming the a graphene channel with g r aphene side gates includes forming the graphene channel with graphene side gates [[in]] between the set of side-gate contacts.
The non-transitory tangible computer readable medium of claim 1, wherein the graphene side gates ean-ale-be are formed by any conducting material material.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an AB-stacked bi-layer graphene layer.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an ABC-stacked t ri -layer graphene layer.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an-A-BCstaeked a stacked few-layer graphene layer.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an AB-stacked bi-layer, an ABC-stacked tri -layer or an ABC-stacked few layer graphene layer with stacking miso r ientation.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene channel and wit h graphene side gates are-femed includes using oxygen reactive-ion etching (R EI).
The non-transitory tangible computer readable medium of claim 1, wherein the forming [[the]] a back-gate dielectric layer over a-silieen the conductive substrate includes forming [[a]] t he back-gate dielectric layer with a thin layer of hexagonal boron nitride SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.1.svg 0.15 6.5 Black and white eemi t a combination thereof.
The non-transitory tangible computer readable medium of claim 1, SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.2.svg 0.15 6.18 Black and white itide- SiOx, SiNx, BNx, HfOx, AlOx, lead zirconate -PZT, any dielectric matea- material, or a combination thereof. SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.3.svg 0.16 6.05 Black and white
The graphene-based nanoconstriction device of claim 1, wherein the graphene-based electronic nanoconstriction device is gate tunable.
The non-transitory tangible computer readable medium of claim 1, wherein the conductive substrate includes a highly doped silicon substrate.
The non-transitory tangible computer readable medium of claim 1, wherein the integrated circuit structure is a gate tunable graphene-based electronic nanoconstriction device. 8 of 13 App l. No. 13/668,401 Docket No. Y O R₉₂₀₁₂₀₂₆₅US₂ Reply to Office Action of
, wherein the plurality of contacts includes a set of side-gate contactsand wherein the graphene channel is [[in]] between the set of side-gate contacts. SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.6.svg 0.16 6.38 Black and white
Layer stacks claimed or described, ordered top of device to substrate.
gate-tunable graphene-based electronic nanoconstriction device
Materials described outside the worked examples.
graphene
back-gate dielectric
top-gate dielectric
AB-stacked bi-layer graphene
ABC-stacked tri-layer graphene
stacked few-layer graphene
hexagonal boron nitride
h-BN
top-gate dielectric materials including SiOx, SiNx, BNx, HfOx, AlOx, lead zirconate titanate (PZT)
highly doped silicon substrate
lead zirconate titanate (PZT) back-gate dielectric
PZT
titanium contacts
Ti
gold contacts
Au
palladium contacts
Pd
platinum contacts
Pt
PMMA etch mask
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a first step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a back gate dielectric layer for forming a …
FIG. 3 is a third step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating grpahense channel and spacers for forming a …
FIG. 4 is a fourth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating top gate dielectric material for forming a …
FIG. 5 is a fifth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a top gate electrode for forming a graphene …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–200 nm | — |
Thickness | 50–100 nm | — |
LASER FORMATION OF GRAPHENE
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a first step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a back gate dielectric layer for forming a …
FIG. 2 is a second step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating source/drain electrodes and side-gate …
FIG. 3 is a third step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating grpahense channel and spacers for forming a …
FIG. 4 is a fourth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating top gate dielectric material for forming a …
FIG. 5 is a fifth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a top gate electrode for forming a graphene …
FIG. 6 is a schematic band diagram of the device in
FIG. 7(B) is a simulation of the device in
FIGS. 8-11 are a series of schematic alternative device configurations of the device in
FIG. 9 illustrates an asymmetrical channel geometry with a leftside gate 927 similar to the leftside 827 of
FIG. 10 has symmetrical channel geometry with a leftside gate 1027 and rightside gate 1028 illustrating a more pointed shape as compared with
FIG. 11 illustrates symmetrical channel geometry with triangular top 1127 and 1128. The asymmetric variations of
FIG. 12 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A non-transitory tangible computer readable medium encoded with a program for fabricating an integrated circuit structure, the program comprising instructions for performing the steps of: forming a back-gate dielectric layer over a conductive substrate; forming a graphene layer over the back-gate dielectric layer; forming a plurality of contacts over a portion of the graphene layer including at least one source contact, at least one drain contact, and at least one side-gate contact; forming in the graphene layer [[in]] between the side-gat e at least one source contact, the seure e at least one drain contact[[,]] and the drai at least one side-gate contact, a graphene channel with graphene side gates; forming a top-gate dielectric layer over the graphene layer; and forming a top-gate electrode over the graphene channel.
The non-transitory tangible computer readable medium of claim 1, wherein the forming [[the]] a plurality of contacts includes forming a set of side-gate contacts, and wherein the forming the a graphene channel with g r aphene side gates includes forming the graphene channel with graphene side gates [[in]] between the set of side-gate contacts.
The non-transitory tangible computer readable medium of claim 1, wherein the graphene side gates ean-ale-be are formed by any conducting material material.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an AB-stacked bi-layer graphene layer.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an ABC-stacked t ri -layer graphene layer.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an-A-BCstaeked a stacked few-layer graphene layer.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene layer includes forming an AB-stacked bi-layer, an ABC-stacked tri -layer or an ABC-stacked few layer graphene layer with stacking miso r ientation.
The non-transitory tangible computer readable medium of claim 1, wherein the forming a graphene channel and wit h graphene side gates are-femed includes using oxygen reactive-ion etching (R EI).
The non-transitory tangible computer readable medium of claim 1, wherein the forming [[the]] a back-gate dielectric layer over a-silieen the conductive substrate includes forming [[a]] t he back-gate dielectric layer with a thin layer of hexagonal boron nitride SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.1.svg 0.15 6.5 Black and white eemi t a combination thereof.
The non-transitory tangible computer readable medium of claim 1, SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.2.svg 0.15 6.18 Black and white itide- SiOx, SiNx, BNx, HfOx, AlOx, lead zirconate -PZT, any dielectric matea- material, or a combination thereof. SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.3.svg 0.16 6.05 Black and white
The graphene-based nanoconstriction device of claim 1, wherein the graphene-based electronic nanoconstriction device is gate tunable.
The non-transitory tangible computer readable medium of claim 1, wherein the conductive substrate includes a highly doped silicon substrate.
The non-transitory tangible computer readable medium of claim 1, wherein the integrated circuit structure is a gate tunable graphene-based electronic nanoconstriction device. 8 of 13 App l. No. 13/668,401 Docket No. Y O R₉₂₀₁₂₀₂₆₅US₂ Reply to Office Action of
, wherein the plurality of contacts includes a set of side-gate contactsand wherein the graphene channel is [[in]] between the set of side-gate contacts. SVG 13668401.07-15-2013.HJ₉VDWAAPXXIFW1.CLM.6.svg 0.16 6.38 Black and white
Layer stacks claimed or described, ordered top of device to substrate.
gate-tunable graphene-based electronic nanoconstriction device
Materials described outside the worked examples.
graphene
back-gate dielectric
top-gate dielectric
AB-stacked bi-layer graphene
ABC-stacked tri-layer graphene
stacked few-layer graphene
hexagonal boron nitride
h-BN
top-gate dielectric materials including SiOx, SiNx, BNx, HfOx, AlOx, lead zirconate titanate (PZT)
highly doped silicon substrate
lead zirconate titanate (PZT) back-gate dielectric
PZT
titanium contacts
Ti
gold contacts
Au
palladium contacts
Pd
platinum contacts
Pt
PMMA etch mask
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a first step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a back gate dielectric layer for forming a …
FIG. 3 is a third step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating grpahense channel and spacers for forming a …
FIG. 4 is a fourth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating top gate dielectric material for forming a …
FIG. 5 is a fifth step of a sequence of top views (A) and corresponding cross- sectional views (B) illustrating a top gate electrode for forming a graphene …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–200 nm | — |
Thickness | 50–100 nm | — |
LASER FORMATION OF GRAPHENE