Patent
US 8,257,999Method of Zinc Oxide film grown on the epitaxial lateral overgrowth Gallium Nitride template
Soo Jin Chua
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,257,999Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 lB shows the AFM of the as grown zinc oxide on c-plane gallium nitride surface. Inset show s the SEM of the same surface area of the two different …
FIG.2, a n underlying gallium nitride layer 103 is grown on a subst r ate 101. The substrat e 101 m ay include a sapphire (0001) subst r ate 10a and a low …
FIG. 3). The ELO zinc oxid e semiconductor structure 100 als o includes zinc oxide layer 11la that is grown by chemical vapor deposition and a lateral zinc …
FIG.5, the ELO gallium nitride/sapphire substrates are put into a tube furnace to grow zinc oxide filrns by chemical vapor deposition and condensation of Zn …
FIG.6, l at e ral overgrowth is allowed to continue unti l the l ateral growth fronts coalesce at interfaces L ila, to form a continuous zinc oxide layer 111. …
FIGS. 7 A and 7B show the cross-sectional scanning electron microscopy (SEM) and the top view SEM images, respectively, of the zinc ox ide/ELO gallium nitride …
FIG. 8A is a high resolution transmission electron microscopy (HRTEM) image and the corresponding SAED pattern of zinc oxide ! ELO gallium nitride interface.
FIG. 9 is the room temperature micro-PL spectra taken from.twvo different regions of the zi nc ox ide/ELO gallium nitride.
FIG. 10 is the X-ray diffraction w/20 scan of the epi-zine oxide/ELO gallium nitride/sapphire (0001) heterostructure.
FIG. 11A shows the AFM of the epi-zine oxide on the ELO gallium nitride surface.
FIG. 88, which sugg e st s that high quality zin c 17 NUS O₆-001 oxide films can be pseudomorphically grown (along the {1120} facet) on the ELO gallium n i …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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An electronic device, comprising: a first gallium nitride layer; a second gallium nitride layer contacting the first gallium nitride layer through an array of openings in a mask on the first gallium nitride layer; and an overlying zin c oxide layer on the second gallium nitride layer, wherein the overlying zin c oxide layer has a lower defect density than a defect density of the first gallium nitride layer.
The device of claim 21, wherein the overlying zin c oxide layer comprises an n-type material, and wherein the first gallium nitride layer comprises a p-type material.
The device of claim 21, wherein the overlying zin c oxide layer comprises a concentration of doping of a group III element of about 108 cm -3.
The device of claim 21, f u rther comprising: a first electrode on an exposed surface of the overlying zin c oxide layer; and a second electrode on an exposed surface of the first gallium nitride layer.
The device of claim 21, further comprising a substrate, wherein the first gallium nitride layer is disposed between the substrate and the second gallium nitride layer.
The device of claim 21, further comprising: an n-type zin c oxide layer on the overlying zin c oxide layer; a quantum well structure on the n-type zin c oxide layer; a p-type zin c oxide layer on the quantum well structure; a first electrode on an exposed surface of the n-type zin c oxide layer; and a second electrode on an exposed surface of the p-type zin c oxide layer.
The device of claim 21, wherein the electronic device comprises an optoelectronic device.
The device of claim 21, wherein the electronic device comprises a light-emitting diode device.
The device of claim 21, wherein the first gallium nitride layer has a thickness in a range of 1 m to 4 m.
The device of claim 21, wherein the first gallium nitride layer has a dislocation density in a range of 108 cm 2 to 10 cm -2
The device of claim 21, wherein the overlying zin c oxide layer has a dislocation density of about 1 0 4 cm -2
A method of fabricating an electronic device, the method comprising: providing a substrate including a first gallium nitride layer, a second gallium nitride layer overlying the first gallium nitride layer, and an overlying zin c oxide layer on the second gallium nitride layer, wherein the overlying zin c oxide layer has a lower defect density than a defect density of the first gallium nitride layer; and forming the electronic device using one or more of the overlying zin c oxide layer, the first gallium nitride layer, or the second gallium nitride layer.
The method of claim 36, wherein said forming the electronic device comprises forming an optoelectronic device with the overlying zin c oxide layer.
The method of claim 36, wherein the overlying zin c oxide layer comprises an n-type material, and wherein the first gallium nitride layer comprises a p-type material.
The method of claim 36, f u rther comprising forming: a first electrode on an exposed surface of the overlying zin c oxide layer; and forming a second electrode on an exposed surface of the second gallium nitride layer.
The method of claim 36, further comprising: forming an n-type zin c oxide layer on the overlying zin c oxide layer; forming quantum well structure on the n-type zin c oxide layer; forming a p-type zin c oxide layer on the quantum well structure; forming a first electrode on an exposed surface of the n-type zin c oxide layer; and forming a second electrode on an exposed surface of the p-type zin c oxide layer.
Layer stacks claimed or described, ordered top of device to substrate.
ELO ZnO/GaN electronic or optoelectronic device
ZnO LED/quantum well device
Materials described outside the worked examples.
first gallium nitride layer (p-type GaN, underlying GaN)
GaN
zinc oxide layer (overlying ZnO, n-type ZnO)
ZnO
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 lB shows the AFM of the as grown zinc oxide on c-plane gallium nitride surface. Inset show s the SEM of the same surface area of the two different …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
ZnO film PL peak position at room temperature | 379 nm | ZnO |
ZnO overlying layer dislocation density (claimed) |
Related documents with shared materials, methods, properties, or citations.
Indium Gallium Nitride (inGaN) Relaxed Templates Employed as a Substrate for Nitride-Based Devices and Related Methods
STACKING FAULT-FREE SEMIPOLAR AND NONPOLAR GAN GROWN ON FOREIGN SUBSTRATES BY ELIMINATING THE NITROGEN POLAR FACETS DURING THE GROWTH
Patent
Atlas literature
Patent
US 8,257,999Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 lB shows the AFM of the as grown zinc oxide on c-plane gallium nitride surface. Inset show s the SEM of the same surface area of the two different …
FIG.2, a n underlying gallium nitride layer 103 is grown on a subst r ate 101. The substrat e 101 m ay include a sapphire (0001) subst r ate 10a and a low …
FIG. 3). The ELO zinc oxid e semiconductor structure 100 als o includes zinc oxide layer 11la that is grown by chemical vapor deposition and a lateral zinc …
FIG.5, the ELO gallium nitride/sapphire substrates are put into a tube furnace to grow zinc oxide filrns by chemical vapor deposition and condensation of Zn …
FIG.6, l at e ral overgrowth is allowed to continue unti l the l ateral growth fronts coalesce at interfaces L ila, to form a continuous zinc oxide layer 111. …
FIGS. 7 A and 7B show the cross-sectional scanning electron microscopy (SEM) and the top view SEM images, respectively, of the zinc ox ide/ELO gallium nitride …
FIG. 8A is a high resolution transmission electron microscopy (HRTEM) image and the corresponding SAED pattern of zinc oxide ! ELO gallium nitride interface.
FIG. 9 is the room temperature micro-PL spectra taken from.twvo different regions of the zi nc ox ide/ELO gallium nitride.
FIG. 10 is the X-ray diffraction w/20 scan of the epi-zine oxide/ELO gallium nitride/sapphire (0001) heterostructure.
FIG. 11A shows the AFM of the epi-zine oxide on the ELO gallium nitride surface.
FIG. 88, which sugg e st s that high quality zin c 17 NUS O₆-001 oxide films can be pseudomorphically grown (along the {1120} facet) on the ELO gallium n i …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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An electronic device, comprising: a first gallium nitride layer; a second gallium nitride layer contacting the first gallium nitride layer through an array of openings in a mask on the first gallium nitride layer; and an overlying zin c oxide layer on the second gallium nitride layer, wherein the overlying zin c oxide layer has a lower defect density than a defect density of the first gallium nitride layer.
The device of claim 21, wherein the overlying zin c oxide layer comprises an n-type material, and wherein the first gallium nitride layer comprises a p-type material.
The device of claim 21, wherein the overlying zin c oxide layer comprises a concentration of doping of a group III element of about 108 cm -3.
The device of claim 21, f u rther comprising: a first electrode on an exposed surface of the overlying zin c oxide layer; and a second electrode on an exposed surface of the first gallium nitride layer.
The device of claim 21, further comprising a substrate, wherein the first gallium nitride layer is disposed between the substrate and the second gallium nitride layer.
The device of claim 21, further comprising: an n-type zin c oxide layer on the overlying zin c oxide layer; a quantum well structure on the n-type zin c oxide layer; a p-type zin c oxide layer on the quantum well structure; a first electrode on an exposed surface of the n-type zin c oxide layer; and a second electrode on an exposed surface of the p-type zin c oxide layer.
The device of claim 21, wherein the electronic device comprises an optoelectronic device.
The device of claim 21, wherein the electronic device comprises a light-emitting diode device.
The device of claim 21, wherein the first gallium nitride layer has a thickness in a range of 1 m to 4 m.
The device of claim 21, wherein the first gallium nitride layer has a dislocation density in a range of 108 cm 2 to 10 cm -2
The device of claim 21, wherein the overlying zin c oxide layer has a dislocation density of about 1 0 4 cm -2
A method of fabricating an electronic device, the method comprising: providing a substrate including a first gallium nitride layer, a second gallium nitride layer overlying the first gallium nitride layer, and an overlying zin c oxide layer on the second gallium nitride layer, wherein the overlying zin c oxide layer has a lower defect density than a defect density of the first gallium nitride layer; and forming the electronic device using one or more of the overlying zin c oxide layer, the first gallium nitride layer, or the second gallium nitride layer.
The method of claim 36, wherein said forming the electronic device comprises forming an optoelectronic device with the overlying zin c oxide layer.
The method of claim 36, wherein the overlying zin c oxide layer comprises an n-type material, and wherein the first gallium nitride layer comprises a p-type material.
The method of claim 36, f u rther comprising forming: a first electrode on an exposed surface of the overlying zin c oxide layer; and forming a second electrode on an exposed surface of the second gallium nitride layer.
The method of claim 36, further comprising: forming an n-type zin c oxide layer on the overlying zin c oxide layer; forming quantum well structure on the n-type zin c oxide layer; forming a p-type zin c oxide layer on the quantum well structure; forming a first electrode on an exposed surface of the n-type zin c oxide layer; and forming a second electrode on an exposed surface of the p-type zin c oxide layer.
Layer stacks claimed or described, ordered top of device to substrate.
ELO ZnO/GaN electronic or optoelectronic device
ZnO LED/quantum well device
Materials described outside the worked examples.
first gallium nitride layer (p-type GaN, underlying GaN)
GaN
zinc oxide layer (overlying ZnO, n-type ZnO)
ZnO
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 lB shows the AFM of the as grown zinc oxide on c-plane gallium nitride surface. Inset show s the SEM of the same surface area of the two different …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
ZnO film PL peak position at room temperature | 379 nm | ZnO |
ZnO overlying layer dislocation density (claimed) |
Related documents with shared materials, methods, properties, or citations.
Indium Gallium Nitride (inGaN) Relaxed Templates Employed as a Substrate for Nitride-Based Devices and Related Methods
STACKING FAULT-FREE SEMIPOLAR AND NONPOLAR GAN GROWN ON FOREIGN SUBSTRATES BY ELIMINATING THE NITROGEN POLAR FACETS DURING THE GROWTH
Patent
Atlas literature
Patent
US 8,257,999Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 lB shows the AFM of the as grown zinc oxide on c-plane gallium nitride surface. Inset show s the SEM of the same surface area of the two different …
FIG.2, a n underlying gallium nitride layer 103 is grown on a subst r ate 101. The substrat e 101 m ay include a sapphire (0001) subst r ate 10a and a low …
FIG. 3). The ELO zinc oxid e semiconductor structure 100 als o includes zinc oxide layer 11la that is grown by chemical vapor deposition and a lateral zinc …
FIG.5, the ELO gallium nitride/sapphire substrates are put into a tube furnace to grow zinc oxide filrns by chemical vapor deposition and condensation of Zn …
FIG.6, l at e ral overgrowth is allowed to continue unti l the l ateral growth fronts coalesce at interfaces L ila, to form a continuous zinc oxide layer 111. …
FIGS. 7 A and 7B show the cross-sectional scanning electron microscopy (SEM) and the top view SEM images, respectively, of the zinc ox ide/ELO gallium nitride …
FIG. 8A is a high resolution transmission electron microscopy (HRTEM) image and the corresponding SAED pattern of zinc oxide ! ELO gallium nitride interface.
FIG. 9 is the room temperature micro-PL spectra taken from.twvo different regions of the zi nc ox ide/ELO gallium nitride.
FIG. 10 is the X-ray diffraction w/20 scan of the epi-zine oxide/ELO gallium nitride/sapphire (0001) heterostructure.
FIG. 11A shows the AFM of the epi-zine oxide on the ELO gallium nitride surface.
FIG. 88, which sugg e st s that high quality zin c 17 NUS O₆-001 oxide films can be pseudomorphically grown (along the {1120} facet) on the ELO gallium n i …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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An electronic device, comprising: a first gallium nitride layer; a second gallium nitride layer contacting the first gallium nitride layer through an array of openings in a mask on the first gallium nitride layer; and an overlying zin c oxide layer on the second gallium nitride layer, wherein the overlying zin c oxide layer has a lower defect density than a defect density of the first gallium nitride layer.
The device of claim 21, wherein the overlying zin c oxide layer comprises an n-type material, and wherein the first gallium nitride layer comprises a p-type material.
The device of claim 21, wherein the overlying zin c oxide layer comprises a concentration of doping of a group III element of about 108 cm -3.
The device of claim 21, f u rther comprising: a first electrode on an exposed surface of the overlying zin c oxide layer; and a second electrode on an exposed surface of the first gallium nitride layer.
The device of claim 21, further comprising a substrate, wherein the first gallium nitride layer is disposed between the substrate and the second gallium nitride layer.
The device of claim 21, further comprising: an n-type zin c oxide layer on the overlying zin c oxide layer; a quantum well structure on the n-type zin c oxide layer; a p-type zin c oxide layer on the quantum well structure; a first electrode on an exposed surface of the n-type zin c oxide layer; and a second electrode on an exposed surface of the p-type zin c oxide layer.
The device of claim 21, wherein the electronic device comprises an optoelectronic device.
The device of claim 21, wherein the electronic device comprises a light-emitting diode device.
The device of claim 21, wherein the first gallium nitride layer has a thickness in a range of 1 m to 4 m.
The device of claim 21, wherein the first gallium nitride layer has a dislocation density in a range of 108 cm 2 to 10 cm -2
The device of claim 21, wherein the overlying zin c oxide layer has a dislocation density of about 1 0 4 cm -2
A method of fabricating an electronic device, the method comprising: providing a substrate including a first gallium nitride layer, a second gallium nitride layer overlying the first gallium nitride layer, and an overlying zin c oxide layer on the second gallium nitride layer, wherein the overlying zin c oxide layer has a lower defect density than a defect density of the first gallium nitride layer; and forming the electronic device using one or more of the overlying zin c oxide layer, the first gallium nitride layer, or the second gallium nitride layer.
The method of claim 36, wherein said forming the electronic device comprises forming an optoelectronic device with the overlying zin c oxide layer.
The method of claim 36, wherein the overlying zin c oxide layer comprises an n-type material, and wherein the first gallium nitride layer comprises a p-type material.
The method of claim 36, f u rther comprising forming: a first electrode on an exposed surface of the overlying zin c oxide layer; and forming a second electrode on an exposed surface of the second gallium nitride layer.
The method of claim 36, further comprising: forming an n-type zin c oxide layer on the overlying zin c oxide layer; forming quantum well structure on the n-type zin c oxide layer; forming a p-type zin c oxide layer on the quantum well structure; forming a first electrode on an exposed surface of the n-type zin c oxide layer; and forming a second electrode on an exposed surface of the p-type zin c oxide layer.
Layer stacks claimed or described, ordered top of device to substrate.
ELO ZnO/GaN electronic or optoelectronic device
ZnO LED/quantum well device
Materials described outside the worked examples.
first gallium nitride layer (p-type GaN, underlying GaN)
GaN
zinc oxide layer (overlying ZnO, n-type ZnO)
ZnO
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 lB shows the AFM of the as grown zinc oxide on c-plane gallium nitride surface. Inset show s the SEM of the same surface area of the two different …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
ZnO film PL peak position at room temperature | 379 nm | ZnO |
ZnO overlying layer dislocation density (claimed) |
Related documents with shared materials, methods, properties, or citations.
Indium Gallium Nitride (inGaN) Relaxed Templates Employed as a Substrate for Nitride-Based Devices and Related Methods
STACKING FAULT-FREE SEMIPOLAR AND NONPOLAR GAN GROWN ON FOREIGN SUBSTRATES BY ELIMINATING THE NITROGEN POLAR FACETS DURING THE GROWTH
Patent
Atlas literature
Patent
US 8,257,999Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 lB shows the AFM of the as grown zinc oxide on c-plane gallium nitride surface. Inset show s the SEM of the same surface area of the two different …
FIG.2, a n underlying gallium nitride layer 103 is grown on a subst r ate 101. The substrat e 101 m ay include a sapphire (0001) subst r ate 10a and a low …
FIG. 3). The ELO zinc oxid e semiconductor structure 100 als o includes zinc oxide layer 11la that is grown by chemical vapor deposition and a lateral zinc …
FIG.5, the ELO gallium nitride/sapphire substrates are put into a tube furnace to grow zinc oxide filrns by chemical vapor deposition and condensation of Zn …
FIG.6, l at e ral overgrowth is allowed to continue unti l the l ateral growth fronts coalesce at interfaces L ila, to form a continuous zinc oxide layer 111. …
FIGS. 7 A and 7B show the cross-sectional scanning electron microscopy (SEM) and the top view SEM images, respectively, of the zinc ox ide/ELO gallium nitride …
FIG. 8A is a high resolution transmission electron microscopy (HRTEM) image and the corresponding SAED pattern of zinc oxide ! ELO gallium nitride interface.
FIG. 9 is the room temperature micro-PL spectra taken from.twvo different regions of the zi nc ox ide/ELO gallium nitride.
FIG. 10 is the X-ray diffraction w/20 scan of the epi-zine oxide/ELO gallium nitride/sapphire (0001) heterostructure.
FIG. 11A shows the AFM of the epi-zine oxide on the ELO gallium nitride surface.
FIG. 88, which sugg e st s that high quality zin c 17 NUS O₆-001 oxide films can be pseudomorphically grown (along the {1120} facet) on the ELO gallium n i …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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An electronic device, comprising: a first gallium nitride layer; a second gallium nitride layer contacting the first gallium nitride layer through an array of openings in a mask on the first gallium nitride layer; and an overlying zin c oxide layer on the second gallium nitride layer, wherein the overlying zin c oxide layer has a lower defect density than a defect density of the first gallium nitride layer.
The device of claim 21, wherein the overlying zin c oxide layer comprises an n-type material, and wherein the first gallium nitride layer comprises a p-type material.
The device of claim 21, wherein the overlying zin c oxide layer comprises a concentration of doping of a group III element of about 108 cm -3.
The device of claim 21, f u rther comprising: a first electrode on an exposed surface of the overlying zin c oxide layer; and a second electrode on an exposed surface of the first gallium nitride layer.
The device of claim 21, further comprising a substrate, wherein the first gallium nitride layer is disposed between the substrate and the second gallium nitride layer.
The device of claim 21, further comprising: an n-type zin c oxide layer on the overlying zin c oxide layer; a quantum well structure on the n-type zin c oxide layer; a p-type zin c oxide layer on the quantum well structure; a first electrode on an exposed surface of the n-type zin c oxide layer; and a second electrode on an exposed surface of the p-type zin c oxide layer.
The device of claim 21, wherein the electronic device comprises an optoelectronic device.
The device of claim 21, wherein the electronic device comprises a light-emitting diode device.
The device of claim 21, wherein the first gallium nitride layer has a thickness in a range of 1 m to 4 m.
The device of claim 21, wherein the first gallium nitride layer has a dislocation density in a range of 108 cm 2 to 10 cm -2
The device of claim 21, wherein the overlying zin c oxide layer has a dislocation density of about 1 0 4 cm -2
A method of fabricating an electronic device, the method comprising: providing a substrate including a first gallium nitride layer, a second gallium nitride layer overlying the first gallium nitride layer, and an overlying zin c oxide layer on the second gallium nitride layer, wherein the overlying zin c oxide layer has a lower defect density than a defect density of the first gallium nitride layer; and forming the electronic device using one or more of the overlying zin c oxide layer, the first gallium nitride layer, or the second gallium nitride layer.
The method of claim 36, wherein said forming the electronic device comprises forming an optoelectronic device with the overlying zin c oxide layer.
The method of claim 36, wherein the overlying zin c oxide layer comprises an n-type material, and wherein the first gallium nitride layer comprises a p-type material.
The method of claim 36, f u rther comprising forming: a first electrode on an exposed surface of the overlying zin c oxide layer; and forming a second electrode on an exposed surface of the second gallium nitride layer.
The method of claim 36, further comprising: forming an n-type zin c oxide layer on the overlying zin c oxide layer; forming quantum well structure on the n-type zin c oxide layer; forming a p-type zin c oxide layer on the quantum well structure; forming a first electrode on an exposed surface of the n-type zin c oxide layer; and forming a second electrode on an exposed surface of the p-type zin c oxide layer.
Layer stacks claimed or described, ordered top of device to substrate.
ELO ZnO/GaN electronic or optoelectronic device
ZnO LED/quantum well device
Materials described outside the worked examples.
first gallium nitride layer (p-type GaN, underlying GaN)
GaN
zinc oxide layer (overlying ZnO, n-type ZnO)
ZnO
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 lB shows the AFM of the as grown zinc oxide on c-plane gallium nitride surface. Inset show s the SEM of the same surface area of the two different …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
ZnO film PL peak position at room temperature | 379 nm | ZnO |
ZnO overlying layer dislocation density (claimed) |
Related documents with shared materials, methods, properties, or citations.
Indium Gallium Nitride (inGaN) Relaxed Templates Employed as a Substrate for Nitride-Based Devices and Related Methods
STACKING FAULT-FREE SEMIPOLAR AND NONPOLAR GAN GROWN ON FOREIGN SUBSTRATES BY ELIMINATING THE NITROGEN POLAR FACETS DURING THE GROWTH
indium (electrode material)
In
aluminum (electrode material)
Al
nickel (electrode material)
Ni
platinum (electrode material)
Pt
palladium (electrode material)
Pd
gold (electrode material)
Au
substrate (sapphire, silicon, or silicon carbide)
SiO₂ mask
SiO₂
zinc powder precursor
Zn
FIG. 1 lB shows the AFM of the as grown zinc oxide on c-plane gallium nitride surface. Inset show s the SEM of the same surface area of the two different …
FIGS. 7 A and 7B show the cross-sectional scanning electron microscopy (SEM) and the top view SEM images, respectively, of the zinc ox ide/ELO gallium nitride …
FIG. 8A is a high resolution transmission electron microscopy (HRTEM) image and the corresponding SAED pattern of zinc oxide ! ELO gallium nitride interface.
FIG. 9 is the room temperature micro-PL spectra taken from.twvo different regions of the zi nc ox ide/ELO gallium nitride.
FIG. 11A shows the AFM of the epi-zine oxide on the ELO gallium nitride surface.
| ≤ 10000 cm⁻² |
ZnO |
GaN underlying layer dislocation density (described range) | 100000000–10000000000 cm⁻² | GaN |
Pressure | 200–500 Torr | — |
Thickness | 30–40 nm | — |
Thickness | 2–10 cm | — |
indium (electrode material)
In
aluminum (electrode material)
Al
nickel (electrode material)
Ni
platinum (electrode material)
Pt
palladium (electrode material)
Pd
gold (electrode material)
Au
substrate (sapphire, silicon, or silicon carbide)
SiO₂ mask
SiO₂
zinc powder precursor
Zn
FIG. 1 lB shows the AFM of the as grown zinc oxide on c-plane gallium nitride surface. Inset show s the SEM of the same surface area of the two different …
FIGS. 7 A and 7B show the cross-sectional scanning electron microscopy (SEM) and the top view SEM images, respectively, of the zinc ox ide/ELO gallium nitride …
FIG. 8A is a high resolution transmission electron microscopy (HRTEM) image and the corresponding SAED pattern of zinc oxide ! ELO gallium nitride interface.
FIG. 9 is the room temperature micro-PL spectra taken from.twvo different regions of the zi nc ox ide/ELO gallium nitride.
FIG. 11A shows the AFM of the epi-zine oxide on the ELO gallium nitride surface.
| ≤ 10000 cm⁻² |
ZnO |
GaN underlying layer dislocation density (described range) | 100000000–10000000000 cm⁻² | GaN |
Pressure | 200–500 Torr | — |
Thickness | 30–40 nm | — |
Thickness | 2–10 cm | — |
indium (electrode material)
In
aluminum (electrode material)
Al
nickel (electrode material)
Ni
platinum (electrode material)
Pt
palladium (electrode material)
Pd
gold (electrode material)
Au
substrate (sapphire, silicon, or silicon carbide)
SiO₂ mask
SiO₂
zinc powder precursor
Zn
FIG. 1 lB shows the AFM of the as grown zinc oxide on c-plane gallium nitride surface. Inset show s the SEM of the same surface area of the two different …
FIGS. 7 A and 7B show the cross-sectional scanning electron microscopy (SEM) and the top view SEM images, respectively, of the zinc ox ide/ELO gallium nitride …
FIG. 8A is a high resolution transmission electron microscopy (HRTEM) image and the corresponding SAED pattern of zinc oxide ! ELO gallium nitride interface.
FIG. 9 is the room temperature micro-PL spectra taken from.twvo different regions of the zi nc ox ide/ELO gallium nitride.
FIG. 11A shows the AFM of the epi-zine oxide on the ELO gallium nitride surface.
| ≤ 10000 cm⁻² |
ZnO |
GaN underlying layer dislocation density (described range) | 100000000–10000000000 cm⁻² | GaN |
Pressure | 200–500 Torr | — |
Thickness | 30–40 nm | — |
Thickness | 2–10 cm | — |
indium (electrode material)
In
aluminum (electrode material)
Al
nickel (electrode material)
Ni
platinum (electrode material)
Pt
palladium (electrode material)
Pd
gold (electrode material)
Au
substrate (sapphire, silicon, or silicon carbide)
SiO₂ mask
SiO₂
zinc powder precursor
Zn
FIG. 1 lB shows the AFM of the as grown zinc oxide on c-plane gallium nitride surface. Inset show s the SEM of the same surface area of the two different …
FIGS. 7 A and 7B show the cross-sectional scanning electron microscopy (SEM) and the top view SEM images, respectively, of the zinc ox ide/ELO gallium nitride …
FIG. 8A is a high resolution transmission electron microscopy (HRTEM) image and the corresponding SAED pattern of zinc oxide ! ELO gallium nitride interface.
FIG. 9 is the room temperature micro-PL spectra taken from.twvo different regions of the zi nc ox ide/ELO gallium nitride.
FIG. 11A shows the AFM of the epi-zine oxide on the ELO gallium nitride surface.
| ≤ 10000 cm⁻² |
ZnO |
GaN underlying layer dislocation density (described range) | 100000000–10000000000 cm⁻² | GaN |
Pressure | 200–500 Torr | — |
Thickness | 30–40 nm | — |
Thickness | 2–10 cm | — |