Patent
US 9,362,381INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF
Chih-Fang Huang
US
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A manufacturing method of an insulated gate bipolar transistor (IGBT) comprising: providing a gallium nitride (GaN) substrate with an upper surface; forming a first GaN layer with a first conductive type on the upper surface, wherein the first GaN layer has a side wall vertical to the upper surface; forming a second GaN layer with a first conductive type on the upper surface; forming a third GaN layer with a second conductive type or an intrinsic conductive type on the first GaN layer, wherein the third GaN layer and the GaN substrate are separated by the first GaN layer; and forming a gate on the GaN substrate, which has a side plate, which is directly or indirectly connected to the side wall in a lateral direction, for controlling a channel; wherein the second GaN layer is separated from the first GaN layer by the gate.
The manufacturing method of claim 5 further comprising: forming an aluminum gallium nitride (AlGaN) barrier layer on the upper surface, which overlays the side wall, wherein the gate is separated from the GaN substrate and the first GaN layer by the AlGaN barrier layer. 5 U.S.S.N. To be assigned
The manufacturing method of claim 5, wherein GaN layer, and the gate form a junction field effect second GaN layer, and the GaN substrate form a JFET and the BJT are connected in parallel.
Embodiments described in the patent, grouped by the materials and process steps they use.
4 materials1 process step
A GaN substrate (N-type or intrinsic) is provided. P-type GaN layers 22a and 22b are formed on the upper surface, with GaN layer 22a having a vertical side wall. An N-type or intrinsic GaN layer 23 is formed above GaN layer 22a, separated from the substrate by 22a. A gate 24 with a side plate directly contacting the side wall 221 laterally is formed. Conductive layers 25, 26, 27 are formed as Ohmic contacts. The resulting structure contains a JFET (GaN substrate, GaN layer 22a, GaN layer 23, gate 24) connected in parallel with a BJT (GaN layer 22a, GaN layer 22b, GaN substrate). When the JFET is ON, a 2DEG forms as the main current channel and serves as the base current of the BJT.
5 materials1 process step
A GaN substrate 31 (N-type or intrinsic) is provided. P-type GaN layers 32a and 32b are formed on the upper surface, with GaN layer 32a having a vertical side wall 321. An N-type or intrinsic GaN layer 33 is formed above GaN layer 32a, separated from the substrate by 32a. An AlGaN barrier layer 39 is formed on the upper surface overlaying the side wall 321. A gate 34 with side plate 341 is indirectly connected to the side wall via the AlGaN barrier layer. The structure forms a MOSFET (GaN substrate 31, GaN layer 32a, GaN layer 33, AlGaN barrier layer 39, gate 34) connected in parallel with a BJT (GaN layer 32a, GaN layer 32b, GaN substrate 31). When the MOSFET is ON, a 2DEG forms, improving operation speed and reducing conduction resistance.
Layer stacks claimed or described, ordered top of device to substrate.
GaN lateral IGBT with JFET-BJT parallel structure
GaN lateral IGBT with AlGaN barrier layer and MOSFET-BJT parallel structure
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,362,381Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Please cancel Claims 1-4. canceled
A manufacturing method of an insulated gate bipolar transistor (IGBT) comprising: providing a gallium nitride (GaN) substrate with an upper surface; forming a first GaN layer with a first conductive type on the upper surface, wherein the first GaN layer has a side wall vertical to the upper surface; forming a second GaN layer with a first conductive type on the upper surface; forming a third GaN layer with a second conductive type or an intrinsic conductive type on the first GaN layer, wherein the third GaN layer and the GaN substrate are separated by the first GaN layer; and forming a gate on the GaN substrate, which has a side plate, which is directly or indirectly connected to the side wall in a lateral direction, for controlling a channel; wherein the second GaN layer is separated from the first GaN layer by the gate.
The manufacturing method of claim 5 further comprising: forming an aluminum gallium nitride (AlGaN) barrier layer on the upper surface, which overlays the side wall, wherein the gate is separated from the GaN substrate and the first GaN layer by the AlGaN barrier layer. 5 U.S.S.N. To be assigned
The manufacturing method of claim 5, wherein GaN layer, and the gate form a junction field effect second GaN layer, and the GaN substrate form a JFET and the BJT are connected in parallel.
Embodiments described in the patent, grouped by the materials and process steps they use.
4 materials1 process step
A GaN substrate (N-type or intrinsic) is provided. P-type GaN layers 22a and 22b are formed on the upper surface, with GaN layer 22a having a vertical side wall. An N-type or intrinsic GaN layer 23 is formed above GaN layer 22a, separated from the substrate by 22a. A gate 24 with a side plate directly contacting the side wall 221 laterally is formed. Conductive layers 25, 26, 27 are formed as Ohmic contacts. The resulting structure contains a JFET (GaN substrate, GaN layer 22a, GaN layer 23, gate 24) connected in parallel with a BJT (GaN layer 22a, GaN layer 22b, GaN substrate). When the JFET is ON, a 2DEG forms as the main current channel and serves as the base current of the BJT.
5 materials1 process step
A GaN substrate 31 (N-type or intrinsic) is provided. P-type GaN layers 32a and 32b are formed on the upper surface, with GaN layer 32a having a vertical side wall 321. An N-type or intrinsic GaN layer 33 is formed above GaN layer 32a, separated from the substrate by 32a. An AlGaN barrier layer 39 is formed on the upper surface overlaying the side wall 321. A gate 34 with side plate 341 is indirectly connected to the side wall via the AlGaN barrier layer. The structure forms a MOSFET (GaN substrate 31, GaN layer 32a, GaN layer 33, AlGaN barrier layer 39, gate 34) connected in parallel with a BJT (GaN layer 32a, GaN layer 32b, GaN substrate 31). When the MOSFET is ON, a 2DEG forms, improving operation speed and reducing conduction resistance.
Layer stacks claimed or described, ordered top of device to substrate.
GaN lateral IGBT with JFET-BJT parallel structure
GaN lateral IGBT with AlGaN barrier layer and MOSFET-BJT parallel structure
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,362,381Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Please cancel Claims 1-4. canceled
A manufacturing method of an insulated gate bipolar transistor (IGBT) comprising: providing a gallium nitride (GaN) substrate with an upper surface; forming a first GaN layer with a first conductive type on the upper surface, wherein the first GaN layer has a side wall vertical to the upper surface; forming a second GaN layer with a first conductive type on the upper surface; forming a third GaN layer with a second conductive type or an intrinsic conductive type on the first GaN layer, wherein the third GaN layer and the GaN substrate are separated by the first GaN layer; and forming a gate on the GaN substrate, which has a side plate, which is directly or indirectly connected to the side wall in a lateral direction, for controlling a channel; wherein the second GaN layer is separated from the first GaN layer by the gate.
The manufacturing method of claim 5 further comprising: forming an aluminum gallium nitride (AlGaN) barrier layer on the upper surface, which overlays the side wall, wherein the gate is separated from the GaN substrate and the first GaN layer by the AlGaN barrier layer. 5 U.S.S.N. To be assigned
The manufacturing method of claim 5, wherein GaN layer, and the gate form a junction field effect second GaN layer, and the GaN substrate form a JFET and the BJT are connected in parallel.
Embodiments described in the patent, grouped by the materials and process steps they use.
4 materials1 process step
A GaN substrate (N-type or intrinsic) is provided. P-type GaN layers 22a and 22b are formed on the upper surface, with GaN layer 22a having a vertical side wall. An N-type or intrinsic GaN layer 23 is formed above GaN layer 22a, separated from the substrate by 22a. A gate 24 with a side plate directly contacting the side wall 221 laterally is formed. Conductive layers 25, 26, 27 are formed as Ohmic contacts. The resulting structure contains a JFET (GaN substrate, GaN layer 22a, GaN layer 23, gate 24) connected in parallel with a BJT (GaN layer 22a, GaN layer 22b, GaN substrate). When the JFET is ON, a 2DEG forms as the main current channel and serves as the base current of the BJT.
5 materials1 process step
A GaN substrate 31 (N-type or intrinsic) is provided. P-type GaN layers 32a and 32b are formed on the upper surface, with GaN layer 32a having a vertical side wall 321. An N-type or intrinsic GaN layer 33 is formed above GaN layer 32a, separated from the substrate by 32a. An AlGaN barrier layer 39 is formed on the upper surface overlaying the side wall 321. A gate 34 with side plate 341 is indirectly connected to the side wall via the AlGaN barrier layer. The structure forms a MOSFET (GaN substrate 31, GaN layer 32a, GaN layer 33, AlGaN barrier layer 39, gate 34) connected in parallel with a BJT (GaN layer 32a, GaN layer 32b, GaN substrate 31). When the MOSFET is ON, a 2DEG forms, improving operation speed and reducing conduction resistance.
Layer stacks claimed or described, ordered top of device to substrate.
GaN lateral IGBT with JFET-BJT parallel structure
GaN lateral IGBT with AlGaN barrier layer and MOSFET-BJT parallel structure
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,362,381Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Please cancel Claims 1-4. canceled
A manufacturing method of an insulated gate bipolar transistor (IGBT) comprising: providing a gallium nitride (GaN) substrate with an upper surface; forming a first GaN layer with a first conductive type on the upper surface, wherein the first GaN layer has a side wall vertical to the upper surface; forming a second GaN layer with a first conductive type on the upper surface; forming a third GaN layer with a second conductive type or an intrinsic conductive type on the first GaN layer, wherein the third GaN layer and the GaN substrate are separated by the first GaN layer; and forming a gate on the GaN substrate, which has a side plate, which is directly or indirectly connected to the side wall in a lateral direction, for controlling a channel; wherein the second GaN layer is separated from the first GaN layer by the gate.
The manufacturing method of claim 5 further comprising: forming an aluminum gallium nitride (AlGaN) barrier layer on the upper surface, which overlays the side wall, wherein the gate is separated from the GaN substrate and the first GaN layer by the AlGaN barrier layer. 5 U.S.S.N. To be assigned
The manufacturing method of claim 5, wherein GaN layer, and the gate form a junction field effect second GaN layer, and the GaN substrate form a JFET and the BJT are connected in parallel.
Embodiments described in the patent, grouped by the materials and process steps they use.
4 materials1 process step
A GaN substrate (N-type or intrinsic) is provided. P-type GaN layers 22a and 22b are formed on the upper surface, with GaN layer 22a having a vertical side wall. An N-type or intrinsic GaN layer 23 is formed above GaN layer 22a, separated from the substrate by 22a. A gate 24 with a side plate directly contacting the side wall 221 laterally is formed. Conductive layers 25, 26, 27 are formed as Ohmic contacts. The resulting structure contains a JFET (GaN substrate, GaN layer 22a, GaN layer 23, gate 24) connected in parallel with a BJT (GaN layer 22a, GaN layer 22b, GaN substrate). When the JFET is ON, a 2DEG forms as the main current channel and serves as the base current of the BJT.
5 materials1 process step
A GaN substrate 31 (N-type or intrinsic) is provided. P-type GaN layers 32a and 32b are formed on the upper surface, with GaN layer 32a having a vertical side wall 321. An N-type or intrinsic GaN layer 33 is formed above GaN layer 32a, separated from the substrate by 32a. An AlGaN barrier layer 39 is formed on the upper surface overlaying the side wall 321. A gate 34 with side plate 341 is indirectly connected to the side wall via the AlGaN barrier layer. The structure forms a MOSFET (GaN substrate 31, GaN layer 32a, GaN layer 33, AlGaN barrier layer 39, gate 34) connected in parallel with a BJT (GaN layer 32a, GaN layer 32b, GaN substrate 31). When the MOSFET is ON, a 2DEG forms, improving operation speed and reducing conduction resistance.
Layer stacks claimed or described, ordered top of device to substrate.
GaN lateral IGBT with JFET-BJT parallel structure
GaN lateral IGBT with AlGaN barrier layer and MOSFET-BJT parallel structure
Related documents with shared materials, methods, properties, or citations.