Patent
US 9,941,380GRAPHENE TRANSISTOR AND RELATED METHODS
Shang-Yi Liu
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,941,380Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0005]
FIG. 2 is a flow chart of a method of fabricating a graphene device according to one or more aspects of the present disclosure; [0006]
FIGS. 3 -6 illustrate cross sectional views of embodiments of a graphene device according to one or more aspects of the present disclosure and corresponding to …
FIG. 4, and in various embodiments, the hydrophobic layer 402 provides the hydrophobic surface 404 having a contact angle (CA) that is between about 900 and …
FIG. 5, and in an embodiment of block 208, the device 300 including the transferred graphene layer 502 (i.e., as-transferred onto the hydrophobic surface 404 …
FIG. 6 includes the flat, clean graphene layer 502 (device channel) on the hydrophobic layer 402, where the graphene layer is contacted by source/drain …
FIG. 7 is a cross-sectional view of a dual-gated graphene device according to one or more aspects of the present disclosure; [0008]
FIG. 8 is a cross-sectional view of a top-gated graphene device according to one or more aspects of the present disclosure; [0009]
FIG. 9 is a temperature profile for a method of annealing a graphene device according to one or more aspects of the present disclosure; [0010]
FIG. 10 is a cross-sectional view of a back-gated graphene photodetector according to one or more aspects of the present disclosure; [0011]
FIG. 11 illustrates conductivity versus gate voltage for various graphene devices, in accordance with one or more aspects of the present disclosure; and [0012]
FIG. 12 illustrates a table including electronic properties for various graphene devices, in accordance with one or more aspects of the present disclosure. 2 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: providing a substrate including an insulating layer; depositing an octadecyltrichlorosilane (ODTS) multila yer film [[and]]or an octyltrichlorosilane (OTS) multila y er film over the insulating layer; cleaning a surface of the deposited ODTS multilayer film or the deposited OTS multila y er film in a solution including both anhydrous toluene and ethanol; transferring a graphene layer onto the cleaned surface of the deposited ODTS multila y er film or the deposited OTS multilayer film, wherein the transferred graphene layer has a first carrier mobility; and after transferring the graphene layer, performing an annealing process, wherein the annealed graphene layer has a second carrier mobility greater than the first carrier mobility. Currently amended
The method of claim 1, further comprising: after performing the annealing process, forming source and drain electrodes in contact with the graphene layer. Original
The method of claim 1, wherein the insulating layer includes a silicon dioxide layer formed over the substrate, and wherein the substrate is used as a global back-gate. Original
The method of claim 1, wherein the substrate is an insulating substrate, and wherein the insulating layer includes the insulating substrate. Original
The method of claim 1, wherein ODTS [[and]]or OTS is provided as a solution in anhydrous toluene, and wherein the substrate including the insulating layer is immersed into the solution for about 24 hours to form the deposited ODTS multila y er film or the deposited OTS multilayer film. Currently amended
The method of claim 1, wherein the transferring the graphene layer onto the cleaned surface of the deposited ODTS multila y er film or the deposited OTS multilayer film is performed using a polymer-free transfer process. Currently amended
The method of claim 1, wherein the performing the annealing process includes performing the annealing process at an annealing temperature from about 150 ° C to about 250 °C. Original
The method of claim 1, wherein the performing the annealing process includes performing the annealing process for a duration from about 10 minutes to about 240 minutes. Original
The method of claim 1, wherein the performing the annealing process includes performing the annealing process in at least one of a nitrogen ambient and a noble gas ambient. Original
A method, comprising: providing a substrate including a dielectric layer disposed thereon; cleaning a surface of the dielectric layer to remove organic residues; forming a hydrophobic layer on the cleaned surface of the dielectric layer; after forming the hydrophobic layer, cleaning a surface of the hydrophobic layer in a solution of anhydrous toluene and ethanol; transferring a CVD-grown graphene film onto the cleaned surface of the hydrophobic layer, wherein the CVD-grown graphene film has a first electron mobility and a first hole mobility; and after transferring the CVD-grown graphene film, performing an annealing process, wherein the annealed CVD-grown graphene film has a second electron mobility greater than the first electron mobility and a second hole mobility greater than the first hole mobility. Previously presented
The method of claim 11, further comprising: after performing the annealing process, forming source and drain electrodes in contact with the CVD-grown graphene film; depositing a top-gate dielectric layer over the CVD-grown graphene film; and forming a top-gate electrode over the top-gate dielectric. Original
The method of claim 11, wherein the hydrophobic layer includes a hydrophobic material including at least one of octadecyltrichlorosilane (ODTS), octyltrichlorosilane (OTS), polytetrafluoroethylene (PTFE), polyethylene (PE), polypropylene (PP), polystyrene (PS), polyimide (P I), and wax. Original
The method of claim 11, wherein the CVD-grown graphene film includes one of monolayer graphene, bilayer graphene, and multi-layer graphene. Original
The method of claim 11, wherein performing the annealing process includes ramping up from about 25 ° C to an annealing temperature of about 200 °C at a ramp rate of about 60 ° C per minute. Original
Canceled
Canceled
A method, comprising: providing a substrate including an insulating layer; depositing an octadecyltrichlorosilane (ODTS) multilayer film [[and]]or an octyltrichlorosilane (OTS) multilayer film over the insulating layer; transferring a bilayer or multi-layer graphene film onto the deposited ODTS multilayer film or the deposited OTS multilayer film, wherein the transferred bilayer or multi-layer graphene film has a first carrier mobility; after transferring the bilayer or multi-layer graphene film, performing an annealing process, wherein the annealed bilayer or multi-layer graphene film has a second carrier mobility greater than the first carrier mobility; coating a surface of the annealed bilayer or multi-layer graphene film with at least one of CdSe/ZnS quantum dots and PbS quantum dots; and forming source and drain electrodes in contact with the annealed bilayer or multi-layer graphene film. Currently amended
The method of claim 21, further comprising: performing the annealing process at an annealing temperature of about 200 ° C for a duration of about 120 minutes. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
back-gated graphene field-effect transistor
top-gated graphene field-effect transistor
Materials described outside the worked examples.
octadecyltrichlorosilane (ODTS) multilayer film
octyltrichlorosilane (OTS) multilayer film
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0005]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
carrier mobility improvement after annealing | — | graphene layer |
Duration | 10–240 minutes |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,941,380Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0005]
FIG. 2 is a flow chart of a method of fabricating a graphene device according to one or more aspects of the present disclosure; [0006]
FIGS. 3 -6 illustrate cross sectional views of embodiments of a graphene device according to one or more aspects of the present disclosure and corresponding to …
FIG. 4, and in various embodiments, the hydrophobic layer 402 provides the hydrophobic surface 404 having a contact angle (CA) that is between about 900 and …
FIG. 5, and in an embodiment of block 208, the device 300 including the transferred graphene layer 502 (i.e., as-transferred onto the hydrophobic surface 404 …
FIG. 6 includes the flat, clean graphene layer 502 (device channel) on the hydrophobic layer 402, where the graphene layer is contacted by source/drain …
FIG. 7 is a cross-sectional view of a dual-gated graphene device according to one or more aspects of the present disclosure; [0008]
FIG. 8 is a cross-sectional view of a top-gated graphene device according to one or more aspects of the present disclosure; [0009]
FIG. 9 is a temperature profile for a method of annealing a graphene device according to one or more aspects of the present disclosure; [0010]
FIG. 10 is a cross-sectional view of a back-gated graphene photodetector according to one or more aspects of the present disclosure; [0011]
FIG. 11 illustrates conductivity versus gate voltage for various graphene devices, in accordance with one or more aspects of the present disclosure; and [0012]
FIG. 12 illustrates a table including electronic properties for various graphene devices, in accordance with one or more aspects of the present disclosure. 2 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: providing a substrate including an insulating layer; depositing an octadecyltrichlorosilane (ODTS) multila yer film [[and]]or an octyltrichlorosilane (OTS) multila y er film over the insulating layer; cleaning a surface of the deposited ODTS multilayer film or the deposited OTS multila y er film in a solution including both anhydrous toluene and ethanol; transferring a graphene layer onto the cleaned surface of the deposited ODTS multila y er film or the deposited OTS multilayer film, wherein the transferred graphene layer has a first carrier mobility; and after transferring the graphene layer, performing an annealing process, wherein the annealed graphene layer has a second carrier mobility greater than the first carrier mobility. Currently amended
The method of claim 1, further comprising: after performing the annealing process, forming source and drain electrodes in contact with the graphene layer. Original
The method of claim 1, wherein the insulating layer includes a silicon dioxide layer formed over the substrate, and wherein the substrate is used as a global back-gate. Original
The method of claim 1, wherein the substrate is an insulating substrate, and wherein the insulating layer includes the insulating substrate. Original
The method of claim 1, wherein ODTS [[and]]or OTS is provided as a solution in anhydrous toluene, and wherein the substrate including the insulating layer is immersed into the solution for about 24 hours to form the deposited ODTS multila y er film or the deposited OTS multilayer film. Currently amended
The method of claim 1, wherein the transferring the graphene layer onto the cleaned surface of the deposited ODTS multila y er film or the deposited OTS multilayer film is performed using a polymer-free transfer process. Currently amended
The method of claim 1, wherein the performing the annealing process includes performing the annealing process at an annealing temperature from about 150 ° C to about 250 °C. Original
The method of claim 1, wherein the performing the annealing process includes performing the annealing process for a duration from about 10 minutes to about 240 minutes. Original
The method of claim 1, wherein the performing the annealing process includes performing the annealing process in at least one of a nitrogen ambient and a noble gas ambient. Original
A method, comprising: providing a substrate including a dielectric layer disposed thereon; cleaning a surface of the dielectric layer to remove organic residues; forming a hydrophobic layer on the cleaned surface of the dielectric layer; after forming the hydrophobic layer, cleaning a surface of the hydrophobic layer in a solution of anhydrous toluene and ethanol; transferring a CVD-grown graphene film onto the cleaned surface of the hydrophobic layer, wherein the CVD-grown graphene film has a first electron mobility and a first hole mobility; and after transferring the CVD-grown graphene film, performing an annealing process, wherein the annealed CVD-grown graphene film has a second electron mobility greater than the first electron mobility and a second hole mobility greater than the first hole mobility. Previously presented
The method of claim 11, further comprising: after performing the annealing process, forming source and drain electrodes in contact with the CVD-grown graphene film; depositing a top-gate dielectric layer over the CVD-grown graphene film; and forming a top-gate electrode over the top-gate dielectric. Original
The method of claim 11, wherein the hydrophobic layer includes a hydrophobic material including at least one of octadecyltrichlorosilane (ODTS), octyltrichlorosilane (OTS), polytetrafluoroethylene (PTFE), polyethylene (PE), polypropylene (PP), polystyrene (PS), polyimide (P I), and wax. Original
The method of claim 11, wherein the CVD-grown graphene film includes one of monolayer graphene, bilayer graphene, and multi-layer graphene. Original
The method of claim 11, wherein performing the annealing process includes ramping up from about 25 ° C to an annealing temperature of about 200 °C at a ramp rate of about 60 ° C per minute. Original
Canceled
Canceled
A method, comprising: providing a substrate including an insulating layer; depositing an octadecyltrichlorosilane (ODTS) multilayer film [[and]]or an octyltrichlorosilane (OTS) multilayer film over the insulating layer; transferring a bilayer or multi-layer graphene film onto the deposited ODTS multilayer film or the deposited OTS multilayer film, wherein the transferred bilayer or multi-layer graphene film has a first carrier mobility; after transferring the bilayer or multi-layer graphene film, performing an annealing process, wherein the annealed bilayer or multi-layer graphene film has a second carrier mobility greater than the first carrier mobility; coating a surface of the annealed bilayer or multi-layer graphene film with at least one of CdSe/ZnS quantum dots and PbS quantum dots; and forming source and drain electrodes in contact with the annealed bilayer or multi-layer graphene film. Currently amended
The method of claim 21, further comprising: performing the annealing process at an annealing temperature of about 200 ° C for a duration of about 120 minutes. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
back-gated graphene field-effect transistor
top-gated graphene field-effect transistor
Materials described outside the worked examples.
octadecyltrichlorosilane (ODTS) multilayer film
octyltrichlorosilane (OTS) multilayer film
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0005]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
carrier mobility improvement after annealing | — | graphene layer |
Duration | 10–240 minutes |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,941,380Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0005]
FIG. 2 is a flow chart of a method of fabricating a graphene device according to one or more aspects of the present disclosure; [0006]
FIGS. 3 -6 illustrate cross sectional views of embodiments of a graphene device according to one or more aspects of the present disclosure and corresponding to …
FIG. 4, and in various embodiments, the hydrophobic layer 402 provides the hydrophobic surface 404 having a contact angle (CA) that is between about 900 and …
FIG. 5, and in an embodiment of block 208, the device 300 including the transferred graphene layer 502 (i.e., as-transferred onto the hydrophobic surface 404 …
FIG. 6 includes the flat, clean graphene layer 502 (device channel) on the hydrophobic layer 402, where the graphene layer is contacted by source/drain …
FIG. 7 is a cross-sectional view of a dual-gated graphene device according to one or more aspects of the present disclosure; [0008]
FIG. 8 is a cross-sectional view of a top-gated graphene device according to one or more aspects of the present disclosure; [0009]
FIG. 9 is a temperature profile for a method of annealing a graphene device according to one or more aspects of the present disclosure; [0010]
FIG. 10 is a cross-sectional view of a back-gated graphene photodetector according to one or more aspects of the present disclosure; [0011]
FIG. 11 illustrates conductivity versus gate voltage for various graphene devices, in accordance with one or more aspects of the present disclosure; and [0012]
FIG. 12 illustrates a table including electronic properties for various graphene devices, in accordance with one or more aspects of the present disclosure. 2 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: providing a substrate including an insulating layer; depositing an octadecyltrichlorosilane (ODTS) multila yer film [[and]]or an octyltrichlorosilane (OTS) multila y er film over the insulating layer; cleaning a surface of the deposited ODTS multilayer film or the deposited OTS multila y er film in a solution including both anhydrous toluene and ethanol; transferring a graphene layer onto the cleaned surface of the deposited ODTS multila y er film or the deposited OTS multilayer film, wherein the transferred graphene layer has a first carrier mobility; and after transferring the graphene layer, performing an annealing process, wherein the annealed graphene layer has a second carrier mobility greater than the first carrier mobility. Currently amended
The method of claim 1, further comprising: after performing the annealing process, forming source and drain electrodes in contact with the graphene layer. Original
The method of claim 1, wherein the insulating layer includes a silicon dioxide layer formed over the substrate, and wherein the substrate is used as a global back-gate. Original
The method of claim 1, wherein the substrate is an insulating substrate, and wherein the insulating layer includes the insulating substrate. Original
The method of claim 1, wherein ODTS [[and]]or OTS is provided as a solution in anhydrous toluene, and wherein the substrate including the insulating layer is immersed into the solution for about 24 hours to form the deposited ODTS multila y er film or the deposited OTS multilayer film. Currently amended
The method of claim 1, wherein the transferring the graphene layer onto the cleaned surface of the deposited ODTS multila y er film or the deposited OTS multilayer film is performed using a polymer-free transfer process. Currently amended
The method of claim 1, wherein the performing the annealing process includes performing the annealing process at an annealing temperature from about 150 ° C to about 250 °C. Original
The method of claim 1, wherein the performing the annealing process includes performing the annealing process for a duration from about 10 minutes to about 240 minutes. Original
The method of claim 1, wherein the performing the annealing process includes performing the annealing process in at least one of a nitrogen ambient and a noble gas ambient. Original
A method, comprising: providing a substrate including a dielectric layer disposed thereon; cleaning a surface of the dielectric layer to remove organic residues; forming a hydrophobic layer on the cleaned surface of the dielectric layer; after forming the hydrophobic layer, cleaning a surface of the hydrophobic layer in a solution of anhydrous toluene and ethanol; transferring a CVD-grown graphene film onto the cleaned surface of the hydrophobic layer, wherein the CVD-grown graphene film has a first electron mobility and a first hole mobility; and after transferring the CVD-grown graphene film, performing an annealing process, wherein the annealed CVD-grown graphene film has a second electron mobility greater than the first electron mobility and a second hole mobility greater than the first hole mobility. Previously presented
The method of claim 11, further comprising: after performing the annealing process, forming source and drain electrodes in contact with the CVD-grown graphene film; depositing a top-gate dielectric layer over the CVD-grown graphene film; and forming a top-gate electrode over the top-gate dielectric. Original
The method of claim 11, wherein the hydrophobic layer includes a hydrophobic material including at least one of octadecyltrichlorosilane (ODTS), octyltrichlorosilane (OTS), polytetrafluoroethylene (PTFE), polyethylene (PE), polypropylene (PP), polystyrene (PS), polyimide (P I), and wax. Original
The method of claim 11, wherein the CVD-grown graphene film includes one of monolayer graphene, bilayer graphene, and multi-layer graphene. Original
The method of claim 11, wherein performing the annealing process includes ramping up from about 25 ° C to an annealing temperature of about 200 °C at a ramp rate of about 60 ° C per minute. Original
Canceled
Canceled
A method, comprising: providing a substrate including an insulating layer; depositing an octadecyltrichlorosilane (ODTS) multilayer film [[and]]or an octyltrichlorosilane (OTS) multilayer film over the insulating layer; transferring a bilayer or multi-layer graphene film onto the deposited ODTS multilayer film or the deposited OTS multilayer film, wherein the transferred bilayer or multi-layer graphene film has a first carrier mobility; after transferring the bilayer or multi-layer graphene film, performing an annealing process, wherein the annealed bilayer or multi-layer graphene film has a second carrier mobility greater than the first carrier mobility; coating a surface of the annealed bilayer or multi-layer graphene film with at least one of CdSe/ZnS quantum dots and PbS quantum dots; and forming source and drain electrodes in contact with the annealed bilayer or multi-layer graphene film. Currently amended
The method of claim 21, further comprising: performing the annealing process at an annealing temperature of about 200 ° C for a duration of about 120 minutes. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
back-gated graphene field-effect transistor
top-gated graphene field-effect transistor
Materials described outside the worked examples.
octadecyltrichlorosilane (ODTS) multilayer film
octyltrichlorosilane (OTS) multilayer film
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0005]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
carrier mobility improvement after annealing | — | graphene layer |
Duration | 10–240 minutes |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,941,380Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0005]
FIG. 2 is a flow chart of a method of fabricating a graphene device according to one or more aspects of the present disclosure; [0006]
FIGS. 3 -6 illustrate cross sectional views of embodiments of a graphene device according to one or more aspects of the present disclosure and corresponding to …
FIG. 4, and in various embodiments, the hydrophobic layer 402 provides the hydrophobic surface 404 having a contact angle (CA) that is between about 900 and …
FIG. 5, and in an embodiment of block 208, the device 300 including the transferred graphene layer 502 (i.e., as-transferred onto the hydrophobic surface 404 …
FIG. 6 includes the flat, clean graphene layer 502 (device channel) on the hydrophobic layer 402, where the graphene layer is contacted by source/drain …
FIG. 7 is a cross-sectional view of a dual-gated graphene device according to one or more aspects of the present disclosure; [0008]
FIG. 8 is a cross-sectional view of a top-gated graphene device according to one or more aspects of the present disclosure; [0009]
FIG. 9 is a temperature profile for a method of annealing a graphene device according to one or more aspects of the present disclosure; [0010]
FIG. 10 is a cross-sectional view of a back-gated graphene photodetector according to one or more aspects of the present disclosure; [0011]
FIG. 11 illustrates conductivity versus gate voltage for various graphene devices, in accordance with one or more aspects of the present disclosure; and [0012]
FIG. 12 illustrates a table including electronic properties for various graphene devices, in accordance with one or more aspects of the present disclosure. 2 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: providing a substrate including an insulating layer; depositing an octadecyltrichlorosilane (ODTS) multila yer film [[and]]or an octyltrichlorosilane (OTS) multila y er film over the insulating layer; cleaning a surface of the deposited ODTS multilayer film or the deposited OTS multila y er film in a solution including both anhydrous toluene and ethanol; transferring a graphene layer onto the cleaned surface of the deposited ODTS multila y er film or the deposited OTS multilayer film, wherein the transferred graphene layer has a first carrier mobility; and after transferring the graphene layer, performing an annealing process, wherein the annealed graphene layer has a second carrier mobility greater than the first carrier mobility. Currently amended
The method of claim 1, further comprising: after performing the annealing process, forming source and drain electrodes in contact with the graphene layer. Original
The method of claim 1, wherein the insulating layer includes a silicon dioxide layer formed over the substrate, and wherein the substrate is used as a global back-gate. Original
The method of claim 1, wherein the substrate is an insulating substrate, and wherein the insulating layer includes the insulating substrate. Original
The method of claim 1, wherein ODTS [[and]]or OTS is provided as a solution in anhydrous toluene, and wherein the substrate including the insulating layer is immersed into the solution for about 24 hours to form the deposited ODTS multila y er film or the deposited OTS multilayer film. Currently amended
The method of claim 1, wherein the transferring the graphene layer onto the cleaned surface of the deposited ODTS multila y er film or the deposited OTS multilayer film is performed using a polymer-free transfer process. Currently amended
The method of claim 1, wherein the performing the annealing process includes performing the annealing process at an annealing temperature from about 150 ° C to about 250 °C. Original
The method of claim 1, wherein the performing the annealing process includes performing the annealing process for a duration from about 10 minutes to about 240 minutes. Original
The method of claim 1, wherein the performing the annealing process includes performing the annealing process in at least one of a nitrogen ambient and a noble gas ambient. Original
A method, comprising: providing a substrate including a dielectric layer disposed thereon; cleaning a surface of the dielectric layer to remove organic residues; forming a hydrophobic layer on the cleaned surface of the dielectric layer; after forming the hydrophobic layer, cleaning a surface of the hydrophobic layer in a solution of anhydrous toluene and ethanol; transferring a CVD-grown graphene film onto the cleaned surface of the hydrophobic layer, wherein the CVD-grown graphene film has a first electron mobility and a first hole mobility; and after transferring the CVD-grown graphene film, performing an annealing process, wherein the annealed CVD-grown graphene film has a second electron mobility greater than the first electron mobility and a second hole mobility greater than the first hole mobility. Previously presented
The method of claim 11, further comprising: after performing the annealing process, forming source and drain electrodes in contact with the CVD-grown graphene film; depositing a top-gate dielectric layer over the CVD-grown graphene film; and forming a top-gate electrode over the top-gate dielectric. Original
The method of claim 11, wherein the hydrophobic layer includes a hydrophobic material including at least one of octadecyltrichlorosilane (ODTS), octyltrichlorosilane (OTS), polytetrafluoroethylene (PTFE), polyethylene (PE), polypropylene (PP), polystyrene (PS), polyimide (P I), and wax. Original
The method of claim 11, wherein the CVD-grown graphene film includes one of monolayer graphene, bilayer graphene, and multi-layer graphene. Original
The method of claim 11, wherein performing the annealing process includes ramping up from about 25 ° C to an annealing temperature of about 200 °C at a ramp rate of about 60 ° C per minute. Original
Canceled
Canceled
A method, comprising: providing a substrate including an insulating layer; depositing an octadecyltrichlorosilane (ODTS) multilayer film [[and]]or an octyltrichlorosilane (OTS) multilayer film over the insulating layer; transferring a bilayer or multi-layer graphene film onto the deposited ODTS multilayer film or the deposited OTS multilayer film, wherein the transferred bilayer or multi-layer graphene film has a first carrier mobility; after transferring the bilayer or multi-layer graphene film, performing an annealing process, wherein the annealed bilayer or multi-layer graphene film has a second carrier mobility greater than the first carrier mobility; coating a surface of the annealed bilayer or multi-layer graphene film with at least one of CdSe/ZnS quantum dots and PbS quantum dots; and forming source and drain electrodes in contact with the annealed bilayer or multi-layer graphene film. Currently amended
The method of claim 21, further comprising: performing the annealing process at an annealing temperature of about 200 ° C for a duration of about 120 minutes. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
back-gated graphene field-effect transistor
top-gated graphene field-effect transistor
Materials described outside the worked examples.
octadecyltrichlorosilane (ODTS) multilayer film
octyltrichlorosilane (OTS) multilayer film
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0005]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
carrier mobility improvement after annealing | — | graphene layer |
Duration | 10–240 minutes |
Related documents with shared materials, methods, properties, or citations.
graphene layer
silicon dioxide
SiO₂
hydrophobic layer
polytetrafluoroethylene (PTFE)
polyethylene (PE)
polypropylene (PP)
polystyrene (PS)
polyimide (PI)
wax
bilayer or multi-layer graphene film
CdSe/ZnS quantum dots
PbS quantum dots
PbS
source/drain contact metals
FIG. 10 is a cross-sectional view of a back-gated graphene photodetector according to one or more aspects of the present disclosure; [0011]
FIG. 11 illustrates conductivity versus gate voltage for various graphene devices, in accordance with one or more aspects of the present disclosure; and [0012]
| — |
Thickness | 90–100 nm | — |
Thickness | 280–300 nm | — |
Pressure | 0.001 Torr | — |
Temperature | 150–250 °C | — |
graphene layer
silicon dioxide
SiO₂
hydrophobic layer
polytetrafluoroethylene (PTFE)
polyethylene (PE)
polypropylene (PP)
polystyrene (PS)
polyimide (PI)
wax
bilayer or multi-layer graphene film
CdSe/ZnS quantum dots
PbS quantum dots
PbS
source/drain contact metals
FIG. 10 is a cross-sectional view of a back-gated graphene photodetector according to one or more aspects of the present disclosure; [0011]
FIG. 11 illustrates conductivity versus gate voltage for various graphene devices, in accordance with one or more aspects of the present disclosure; and [0012]
| — |
Thickness | 90–100 nm | — |
Thickness | 280–300 nm | — |
Pressure | 0.001 Torr | — |
Temperature | 150–250 °C | — |
graphene layer
silicon dioxide
SiO₂
hydrophobic layer
polytetrafluoroethylene (PTFE)
polyethylene (PE)
polypropylene (PP)
polystyrene (PS)
polyimide (PI)
wax
bilayer or multi-layer graphene film
CdSe/ZnS quantum dots
PbS quantum dots
PbS
source/drain contact metals
FIG. 10 is a cross-sectional view of a back-gated graphene photodetector according to one or more aspects of the present disclosure; [0011]
FIG. 11 illustrates conductivity versus gate voltage for various graphene devices, in accordance with one or more aspects of the present disclosure; and [0012]
| — |
Thickness | 90–100 nm | — |
Thickness | 280–300 nm | — |
Pressure | 0.001 Torr | — |
Temperature | 150–250 °C | — |
graphene layer
silicon dioxide
SiO₂
hydrophobic layer
polytetrafluoroethylene (PTFE)
polyethylene (PE)
polypropylene (PP)
polystyrene (PS)
polyimide (PI)
wax
bilayer or multi-layer graphene film
CdSe/ZnS quantum dots
PbS quantum dots
PbS
source/drain contact metals
FIG. 10 is a cross-sectional view of a back-gated graphene photodetector according to one or more aspects of the present disclosure; [0011]
FIG. 11 illustrates conductivity versus gate voltage for various graphene devices, in accordance with one or more aspects of the present disclosure; and [0012]
| — |
Thickness | 90–100 nm | — |
Thickness | 280–300 nm | — |
Pressure | 0.001 Torr | — |
Temperature | 150–250 °C | — |