Patent
US 8,946,771GALLIUM NITRIDE SEMICONDUCTOR DEVICES AND METHOD MAKING THEREOF
Chih-Wen Hsiung
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,946,771Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) transistor device, comprising: a gallium nitride (GaN) layer located on a substrate; an electron supply layer located on top of the GaN layer, wherein the electron supply layer and the GaN layer share an interface that forms a hetero-junction therebetween; a planar etch stop layer located above the electron supply layer, wherein the planar etch stop layer is configured to stop an etching process from etching the electron supply layer; a source contact and a drain contact abuttin g the electron su pp ly layer and the p lanar etch sto p layer, where a bottom surface of the source contact, a bottom surface of the drain contact and a bottom surface of the p lanar etch sto p layer are co p lanar and contact a to p surface of the electron su pp ly layer; a gate structure located on top of the planar etch stop layer, so that the planar etch stop layer extends laterally as a continuous layer below the gate structure so as to separate the electron supply layer from the gate structure; and wherein the gate structure comprises a group I II -V semiconductor material located on top of and in direct contact with the planar etch stop layer, and a gate metal layer located on top of and in direct contact with the group I II -V semiconductor material.
The GaN transistor device of claim 1, wherein the planar etch stop layer comprises aluminum nitride (AIN). Serial No. 13/292,487 Page 3
The GaN transistor device of claim 1, wherein the planar etch stop layer comprises indium nitride (InN), aluminum oxide (A l2O 3), or gallium oxide (GaO).
The GaN transistor device of claim 1, wherein a bottom surface of the planar etch stop layer abuts a top surface of the electron supply layer in a gate region of the GaN transistor device. previously presented
The GaN transistor device of claim 1, wherein the planar etch stop layer has a band gap that is larger than band gaps of the group I II-V semiconductor material and the electron supply layer.
The GaN transistor device of claim 1, wherein the group I II -V semiconductor material comprises a p-type doped gallium nitride (GaN).
The GaN transistor device of claim 1, wherein the group I II -V semiconductor material comprises a p-type doped aluminum gallium nitride (AIGaN) or an indium gallium nitride (I n GaN).
1 0. The GaN transistor device of claim 1, wherein the electron supply layer comprises aluminum gallium nitride (AIGaN). 11-20.
The GaN transistor device of claim 1, fu r4her ee-mpris~g; wherein [[a]] the source contact and the drain contact abutting the electron Supply layer o n abottom s urfaco and abut[[ting]] sidewalls of the p lanar etch stop layer on a n adjacent S ide srae n ab tti n g the -etc h st o layer o n an adj acent s ide sur f ace, wherein the Gurco contact-and thc dr contact rc locatod on opposite sides of the gate structure.
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A transistor device, comprising: a substrate; a gallium nitride (GaN) layer disposed over the substrate; an electron supply layer disposed onto the GaN layer, wherein the electron supply layer has a larger bandgap than the GaN layer, so as to form a hetero-junction therebetween; an aluminum nitride (AIN) etch stop layer disposed onto and in direct contact with the electron supply layer, wherein the AIN etch stop layer is configured to stop an etching process from etching the electron supply layer; and a source contact and a drain contact abuttin g the electron su pp ly layer and the AIN etch sto p layer, wherein a bottom surface of the source contact, a bottom surface of the drain contact and a bottom surface of the AIN etch sto p layer are co p lanar and contact a to p surface of the electron su pp ly layer; a gate structure disposed at a position abutting the AIN etch stop layer, wherein the q ate structure com p rises a g rou p III -V semiconductor material located on to p of and in direct contact with the AIN etch sto p layer, and a q ate metal layer located on to p of and in direct contact with the g rou p III -V semiconductor material, and wherein the AIN etch stop layer has a larger bandgap than the electron supply layer and the gate structure. currently amended
The transistor device of claim 21, wherein the etch stop layer has a thickness in a range of between approximately 1 nm and approximately 20 nm. previously presented
The transistor device of claim 21, wherein the electron supply layer has a first etching selectivity for etching the gallium nitride layer, wherein the etch stop layer has a second etching selectivity for etching the gallium nitride layer that is greater than three times larger than the first etching selectivity.
The GaN transistor device of claim 21, fu r4her ee-mpr; &ig;~ wherein [[a]] the source contact and the drain contact abutting the electron Supply layer o n abottom surfaco and abut[[ting]] sidewalls of the ecl-trically -ins atingA.N etch stop layer on an adjacent Side face d a drain ontact abu tti n g th e clo tro n su pply lay e r on a bottom s u rfa co an d th e wherinthc ourco c tact-and-thc dr nctact-arc locatod on opposite sides of the gate structure.
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The transistor device of claim 24, wherein the group III -V semiconductor material comprises gallium nitride (GaN), aluminum gallium nitride (AIGaN), or indium gallium nitride (I n GaN). 26-27.
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A gallium nitride (GaN) transistor device, comprising: a substrate; a gallium nitride (GaN) layer disposed over the substrate; a layer of aluminum gallium nitride (AIGaN) disposed onto and in direct contact with the GaN layer; a layer of aluminum nitride (AIN) disposed onto and in direct contact with the layer of AIGaN, wherein the layer of AIN is configured to stop an etching process from etching the layer of AIGaN; a source contact and a drain contact abuttin g the layer if AIGaN and the layer of AIN, wherein a bottom surface of the source contact, a bottom surface of the drain contact and a bottom surface of the layer of AIN are co p lanar and contact a to p surface of the layer of AIGaN; a layer of doped gallium nitride (GaN) disposed onto and in direct contact with the layer of AIN; and a layer of gate metal disposed onto and in direct contact with the layer of doped GaN. Serial No. 13/292,487 Page 6 currently amended
The GaN transistor device of claim 29, further comprising: wherein [[a]] the source contact and the drain contact abutting the layer of !QaN O n-bottom-siifaee-a abut[[ting]] sidewalls of the layer of AIN on an adjacent side eu4aGet-an4d la ye r of AI Nl on an adjacent s ide sur face, Serial No. 13/292,487 Page 7 whereinthe oureontact and the drain are loated on opposite sides of the layer of gate metal.
canceled
Layer stacks claimed or described, ordered top of device to substrate.
enhancement mode GaN transistor device (generic etch stop layer)
Materials described outside the worked examples.
gallium nitride
GaN
aluminum gallium nitride
AlGaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 4 eV | AlGaN |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,946,771Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) transistor device, comprising: a gallium nitride (GaN) layer located on a substrate; an electron supply layer located on top of the GaN layer, wherein the electron supply layer and the GaN layer share an interface that forms a hetero-junction therebetween; a planar etch stop layer located above the electron supply layer, wherein the planar etch stop layer is configured to stop an etching process from etching the electron supply layer; a source contact and a drain contact abuttin g the electron su pp ly layer and the p lanar etch sto p layer, where a bottom surface of the source contact, a bottom surface of the drain contact and a bottom surface of the p lanar etch sto p layer are co p lanar and contact a to p surface of the electron su pp ly layer; a gate structure located on top of the planar etch stop layer, so that the planar etch stop layer extends laterally as a continuous layer below the gate structure so as to separate the electron supply layer from the gate structure; and wherein the gate structure comprises a group I II -V semiconductor material located on top of and in direct contact with the planar etch stop layer, and a gate metal layer located on top of and in direct contact with the group I II -V semiconductor material.
The GaN transistor device of claim 1, wherein the planar etch stop layer comprises aluminum nitride (AIN). Serial No. 13/292,487 Page 3
The GaN transistor device of claim 1, wherein the planar etch stop layer comprises indium nitride (InN), aluminum oxide (A l2O 3), or gallium oxide (GaO).
The GaN transistor device of claim 1, wherein a bottom surface of the planar etch stop layer abuts a top surface of the electron supply layer in a gate region of the GaN transistor device. previously presented
The GaN transistor device of claim 1, wherein the planar etch stop layer has a band gap that is larger than band gaps of the group I II-V semiconductor material and the electron supply layer.
The GaN transistor device of claim 1, wherein the group I II -V semiconductor material comprises a p-type doped gallium nitride (GaN).
The GaN transistor device of claim 1, wherein the group I II -V semiconductor material comprises a p-type doped aluminum gallium nitride (AIGaN) or an indium gallium nitride (I n GaN).
1 0. The GaN transistor device of claim 1, wherein the electron supply layer comprises aluminum gallium nitride (AIGaN). 11-20.
The GaN transistor device of claim 1, fu r4her ee-mpris~g; wherein [[a]] the source contact and the drain contact abutting the electron Supply layer o n abottom s urfaco and abut[[ting]] sidewalls of the p lanar etch stop layer on a n adjacent S ide srae n ab tti n g the -etc h st o layer o n an adj acent s ide sur f ace, wherein the Gurco contact-and thc dr contact rc locatod on opposite sides of the gate structure.
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A transistor device, comprising: a substrate; a gallium nitride (GaN) layer disposed over the substrate; an electron supply layer disposed onto the GaN layer, wherein the electron supply layer has a larger bandgap than the GaN layer, so as to form a hetero-junction therebetween; an aluminum nitride (AIN) etch stop layer disposed onto and in direct contact with the electron supply layer, wherein the AIN etch stop layer is configured to stop an etching process from etching the electron supply layer; and a source contact and a drain contact abuttin g the electron su pp ly layer and the AIN etch sto p layer, wherein a bottom surface of the source contact, a bottom surface of the drain contact and a bottom surface of the AIN etch sto p layer are co p lanar and contact a to p surface of the electron su pp ly layer; a gate structure disposed at a position abutting the AIN etch stop layer, wherein the q ate structure com p rises a g rou p III -V semiconductor material located on to p of and in direct contact with the AIN etch sto p layer, and a q ate metal layer located on to p of and in direct contact with the g rou p III -V semiconductor material, and wherein the AIN etch stop layer has a larger bandgap than the electron supply layer and the gate structure. currently amended
The transistor device of claim 21, wherein the etch stop layer has a thickness in a range of between approximately 1 nm and approximately 20 nm. previously presented
The transistor device of claim 21, wherein the electron supply layer has a first etching selectivity for etching the gallium nitride layer, wherein the etch stop layer has a second etching selectivity for etching the gallium nitride layer that is greater than three times larger than the first etching selectivity.
The GaN transistor device of claim 21, fu r4her ee-mpr; &ig;~ wherein [[a]] the source contact and the drain contact abutting the electron Supply layer o n abottom surfaco and abut[[ting]] sidewalls of the ecl-trically -ins atingA.N etch stop layer on an adjacent Side face d a drain ontact abu tti n g th e clo tro n su pply lay e r on a bottom s u rfa co an d th e wherinthc ourco c tact-and-thc dr nctact-arc locatod on opposite sides of the gate structure.
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The transistor device of claim 24, wherein the group III -V semiconductor material comprises gallium nitride (GaN), aluminum gallium nitride (AIGaN), or indium gallium nitride (I n GaN). 26-27.
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A gallium nitride (GaN) transistor device, comprising: a substrate; a gallium nitride (GaN) layer disposed over the substrate; a layer of aluminum gallium nitride (AIGaN) disposed onto and in direct contact with the GaN layer; a layer of aluminum nitride (AIN) disposed onto and in direct contact with the layer of AIGaN, wherein the layer of AIN is configured to stop an etching process from etching the layer of AIGaN; a source contact and a drain contact abuttin g the layer if AIGaN and the layer of AIN, wherein a bottom surface of the source contact, a bottom surface of the drain contact and a bottom surface of the layer of AIN are co p lanar and contact a to p surface of the layer of AIGaN; a layer of doped gallium nitride (GaN) disposed onto and in direct contact with the layer of AIN; and a layer of gate metal disposed onto and in direct contact with the layer of doped GaN. Serial No. 13/292,487 Page 6 currently amended
The GaN transistor device of claim 29, further comprising: wherein [[a]] the source contact and the drain contact abutting the layer of !QaN O n-bottom-siifaee-a abut[[ting]] sidewalls of the layer of AIN on an adjacent side eu4aGet-an4d la ye r of AI Nl on an adjacent s ide sur face, Serial No. 13/292,487 Page 7 whereinthe oureontact and the drain are loated on opposite sides of the layer of gate metal.
canceled
Layer stacks claimed or described, ordered top of device to substrate.
enhancement mode GaN transistor device (generic etch stop layer)
Materials described outside the worked examples.
gallium nitride
GaN
aluminum gallium nitride
AlGaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 4 eV | AlGaN |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,946,771Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) transistor device, comprising: a gallium nitride (GaN) layer located on a substrate; an electron supply layer located on top of the GaN layer, wherein the electron supply layer and the GaN layer share an interface that forms a hetero-junction therebetween; a planar etch stop layer located above the electron supply layer, wherein the planar etch stop layer is configured to stop an etching process from etching the electron supply layer; a source contact and a drain contact abuttin g the electron su pp ly layer and the p lanar etch sto p layer, where a bottom surface of the source contact, a bottom surface of the drain contact and a bottom surface of the p lanar etch sto p layer are co p lanar and contact a to p surface of the electron su pp ly layer; a gate structure located on top of the planar etch stop layer, so that the planar etch stop layer extends laterally as a continuous layer below the gate structure so as to separate the electron supply layer from the gate structure; and wherein the gate structure comprises a group I II -V semiconductor material located on top of and in direct contact with the planar etch stop layer, and a gate metal layer located on top of and in direct contact with the group I II -V semiconductor material.
The GaN transistor device of claim 1, wherein the planar etch stop layer comprises aluminum nitride (AIN). Serial No. 13/292,487 Page 3
The GaN transistor device of claim 1, wherein the planar etch stop layer comprises indium nitride (InN), aluminum oxide (A l2O 3), or gallium oxide (GaO).
The GaN transistor device of claim 1, wherein a bottom surface of the planar etch stop layer abuts a top surface of the electron supply layer in a gate region of the GaN transistor device. previously presented
The GaN transistor device of claim 1, wherein the planar etch stop layer has a band gap that is larger than band gaps of the group I II-V semiconductor material and the electron supply layer.
The GaN transistor device of claim 1, wherein the group I II -V semiconductor material comprises a p-type doped gallium nitride (GaN).
The GaN transistor device of claim 1, wherein the group I II -V semiconductor material comprises a p-type doped aluminum gallium nitride (AIGaN) or an indium gallium nitride (I n GaN).
1 0. The GaN transistor device of claim 1, wherein the electron supply layer comprises aluminum gallium nitride (AIGaN). 11-20.
The GaN transistor device of claim 1, fu r4her ee-mpris~g; wherein [[a]] the source contact and the drain contact abutting the electron Supply layer o n abottom s urfaco and abut[[ting]] sidewalls of the p lanar etch stop layer on a n adjacent S ide srae n ab tti n g the -etc h st o layer o n an adj acent s ide sur f ace, wherein the Gurco contact-and thc dr contact rc locatod on opposite sides of the gate structure.
canceled
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A transistor device, comprising: a substrate; a gallium nitride (GaN) layer disposed over the substrate; an electron supply layer disposed onto the GaN layer, wherein the electron supply layer has a larger bandgap than the GaN layer, so as to form a hetero-junction therebetween; an aluminum nitride (AIN) etch stop layer disposed onto and in direct contact with the electron supply layer, wherein the AIN etch stop layer is configured to stop an etching process from etching the electron supply layer; and a source contact and a drain contact abuttin g the electron su pp ly layer and the AIN etch sto p layer, wherein a bottom surface of the source contact, a bottom surface of the drain contact and a bottom surface of the AIN etch sto p layer are co p lanar and contact a to p surface of the electron su pp ly layer; a gate structure disposed at a position abutting the AIN etch stop layer, wherein the q ate structure com p rises a g rou p III -V semiconductor material located on to p of and in direct contact with the AIN etch sto p layer, and a q ate metal layer located on to p of and in direct contact with the g rou p III -V semiconductor material, and wherein the AIN etch stop layer has a larger bandgap than the electron supply layer and the gate structure. currently amended
The transistor device of claim 21, wherein the etch stop layer has a thickness in a range of between approximately 1 nm and approximately 20 nm. previously presented
The transistor device of claim 21, wherein the electron supply layer has a first etching selectivity for etching the gallium nitride layer, wherein the etch stop layer has a second etching selectivity for etching the gallium nitride layer that is greater than three times larger than the first etching selectivity.
The GaN transistor device of claim 21, fu r4her ee-mpr; &ig;~ wherein [[a]] the source contact and the drain contact abutting the electron Supply layer o n abottom surfaco and abut[[ting]] sidewalls of the ecl-trically -ins atingA.N etch stop layer on an adjacent Side face d a drain ontact abu tti n g th e clo tro n su pply lay e r on a bottom s u rfa co an d th e wherinthc ourco c tact-and-thc dr nctact-arc locatod on opposite sides of the gate structure.
canceled
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The transistor device of claim 24, wherein the group III -V semiconductor material comprises gallium nitride (GaN), aluminum gallium nitride (AIGaN), or indium gallium nitride (I n GaN). 26-27.
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A gallium nitride (GaN) transistor device, comprising: a substrate; a gallium nitride (GaN) layer disposed over the substrate; a layer of aluminum gallium nitride (AIGaN) disposed onto and in direct contact with the GaN layer; a layer of aluminum nitride (AIN) disposed onto and in direct contact with the layer of AIGaN, wherein the layer of AIN is configured to stop an etching process from etching the layer of AIGaN; a source contact and a drain contact abuttin g the layer if AIGaN and the layer of AIN, wherein a bottom surface of the source contact, a bottom surface of the drain contact and a bottom surface of the layer of AIN are co p lanar and contact a to p surface of the layer of AIGaN; a layer of doped gallium nitride (GaN) disposed onto and in direct contact with the layer of AIN; and a layer of gate metal disposed onto and in direct contact with the layer of doped GaN. Serial No. 13/292,487 Page 6 currently amended
The GaN transistor device of claim 29, further comprising: wherein [[a]] the source contact and the drain contact abutting the layer of !QaN O n-bottom-siifaee-a abut[[ting]] sidewalls of the layer of AIN on an adjacent side eu4aGet-an4d la ye r of AI Nl on an adjacent s ide sur face, Serial No. 13/292,487 Page 7 whereinthe oureontact and the drain are loated on opposite sides of the layer of gate metal.
canceled
Layer stacks claimed or described, ordered top of device to substrate.
enhancement mode GaN transistor device (generic etch stop layer)
Materials described outside the worked examples.
gallium nitride
GaN
aluminum gallium nitride
AlGaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 4 eV | AlGaN |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,946,771Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) transistor device, comprising: a gallium nitride (GaN) layer located on a substrate; an electron supply layer located on top of the GaN layer, wherein the electron supply layer and the GaN layer share an interface that forms a hetero-junction therebetween; a planar etch stop layer located above the electron supply layer, wherein the planar etch stop layer is configured to stop an etching process from etching the electron supply layer; a source contact and a drain contact abuttin g the electron su pp ly layer and the p lanar etch sto p layer, where a bottom surface of the source contact, a bottom surface of the drain contact and a bottom surface of the p lanar etch sto p layer are co p lanar and contact a to p surface of the electron su pp ly layer; a gate structure located on top of the planar etch stop layer, so that the planar etch stop layer extends laterally as a continuous layer below the gate structure so as to separate the electron supply layer from the gate structure; and wherein the gate structure comprises a group I II -V semiconductor material located on top of and in direct contact with the planar etch stop layer, and a gate metal layer located on top of and in direct contact with the group I II -V semiconductor material.
The GaN transistor device of claim 1, wherein the planar etch stop layer comprises aluminum nitride (AIN). Serial No. 13/292,487 Page 3
The GaN transistor device of claim 1, wherein the planar etch stop layer comprises indium nitride (InN), aluminum oxide (A l2O 3), or gallium oxide (GaO).
The GaN transistor device of claim 1, wherein a bottom surface of the planar etch stop layer abuts a top surface of the electron supply layer in a gate region of the GaN transistor device. previously presented
The GaN transistor device of claim 1, wherein the planar etch stop layer has a band gap that is larger than band gaps of the group I II-V semiconductor material and the electron supply layer.
The GaN transistor device of claim 1, wherein the group I II -V semiconductor material comprises a p-type doped gallium nitride (GaN).
The GaN transistor device of claim 1, wherein the group I II -V semiconductor material comprises a p-type doped aluminum gallium nitride (AIGaN) or an indium gallium nitride (I n GaN).
1 0. The GaN transistor device of claim 1, wherein the electron supply layer comprises aluminum gallium nitride (AIGaN). 11-20.
The GaN transistor device of claim 1, fu r4her ee-mpris~g; wherein [[a]] the source contact and the drain contact abutting the electron Supply layer o n abottom s urfaco and abut[[ting]] sidewalls of the p lanar etch stop layer on a n adjacent S ide srae n ab tti n g the -etc h st o layer o n an adj acent s ide sur f ace, wherein the Gurco contact-and thc dr contact rc locatod on opposite sides of the gate structure.
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
A transistor device, comprising: a substrate; a gallium nitride (GaN) layer disposed over the substrate; an electron supply layer disposed onto the GaN layer, wherein the electron supply layer has a larger bandgap than the GaN layer, so as to form a hetero-junction therebetween; an aluminum nitride (AIN) etch stop layer disposed onto and in direct contact with the electron supply layer, wherein the AIN etch stop layer is configured to stop an etching process from etching the electron supply layer; and a source contact and a drain contact abuttin g the electron su pp ly layer and the AIN etch sto p layer, wherein a bottom surface of the source contact, a bottom surface of the drain contact and a bottom surface of the AIN etch sto p layer are co p lanar and contact a to p surface of the electron su pp ly layer; a gate structure disposed at a position abutting the AIN etch stop layer, wherein the q ate structure com p rises a g rou p III -V semiconductor material located on to p of and in direct contact with the AIN etch sto p layer, and a q ate metal layer located on to p of and in direct contact with the g rou p III -V semiconductor material, and wherein the AIN etch stop layer has a larger bandgap than the electron supply layer and the gate structure. currently amended
The transistor device of claim 21, wherein the etch stop layer has a thickness in a range of between approximately 1 nm and approximately 20 nm. previously presented
The transistor device of claim 21, wherein the electron supply layer has a first etching selectivity for etching the gallium nitride layer, wherein the etch stop layer has a second etching selectivity for etching the gallium nitride layer that is greater than three times larger than the first etching selectivity.
The GaN transistor device of claim 21, fu r4her ee-mpr; &ig;~ wherein [[a]] the source contact and the drain contact abutting the electron Supply layer o n abottom surfaco and abut[[ting]] sidewalls of the ecl-trically -ins atingA.N etch stop layer on an adjacent Side face d a drain ontact abu tti n g th e clo tro n su pply lay e r on a bottom s u rfa co an d th e wherinthc ourco c tact-and-thc dr nctact-arc locatod on opposite sides of the gate structure.
canceled
canceled
The transistor device of claim 24, wherein the group III -V semiconductor material comprises gallium nitride (GaN), aluminum gallium nitride (AIGaN), or indium gallium nitride (I n GaN). 26-27.
canceled
canceled
A gallium nitride (GaN) transistor device, comprising: a substrate; a gallium nitride (GaN) layer disposed over the substrate; a layer of aluminum gallium nitride (AIGaN) disposed onto and in direct contact with the GaN layer; a layer of aluminum nitride (AIN) disposed onto and in direct contact with the layer of AIGaN, wherein the layer of AIN is configured to stop an etching process from etching the layer of AIGaN; a source contact and a drain contact abuttin g the layer if AIGaN and the layer of AIN, wherein a bottom surface of the source contact, a bottom surface of the drain contact and a bottom surface of the layer of AIN are co p lanar and contact a to p surface of the layer of AIGaN; a layer of doped gallium nitride (GaN) disposed onto and in direct contact with the layer of AIN; and a layer of gate metal disposed onto and in direct contact with the layer of doped GaN. Serial No. 13/292,487 Page 6 currently amended
The GaN transistor device of claim 29, further comprising: wherein [[a]] the source contact and the drain contact abutting the layer of !QaN O n-bottom-siifaee-a abut[[ting]] sidewalls of the layer of AIN on an adjacent side eu4aGet-an4d la ye r of AI Nl on an adjacent s ide sur face, Serial No. 13/292,487 Page 7 whereinthe oureontact and the drain are loated on opposite sides of the layer of gate metal.
canceled
Layer stacks claimed or described, ordered top of device to substrate.
enhancement mode GaN transistor device (generic etch stop layer)
Materials described outside the worked examples.
gallium nitride
GaN
aluminum gallium nitride
AlGaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 4 eV | AlGaN |
Related documents with shared materials, methods, properties, or citations.
enhancement mode GaN transistor device (AIN etch stop layer)
GaN transistor device with AlGaN electron supply, AlN etch stop, doped GaN gate
group III-V semiconductor material
gate metal
aluminum nitride
AlN
indium nitride
InN
aluminum oxide
Al₂O₃
gallium oxide
GaO
indium gallium nitride
InGaN
sapphire substrate
| 3.4 eV |
GaN |
— | 50–300 W | — |
Thickness | 1–20 nm | — |
enhancement mode GaN transistor device (AIN etch stop layer)
GaN transistor device with AlGaN electron supply, AlN etch stop, doped GaN gate
group III-V semiconductor material
gate metal
aluminum nitride
AlN
indium nitride
InN
aluminum oxide
Al₂O₃
gallium oxide
GaO
indium gallium nitride
InGaN
sapphire substrate
| 3.4 eV |
GaN |
— | 50–300 W | — |
Thickness | 1–20 nm | — |
enhancement mode GaN transistor device (AIN etch stop layer)
GaN transistor device with AlGaN electron supply, AlN etch stop, doped GaN gate
group III-V semiconductor material
gate metal
aluminum nitride
AlN
indium nitride
InN
aluminum oxide
Al₂O₃
gallium oxide
GaO
indium gallium nitride
InGaN
sapphire substrate
| 3.4 eV |
GaN |
— | 50–300 W | — |
Thickness | 1–20 nm | — |
enhancement mode GaN transistor device (AIN etch stop layer)
GaN transistor device with AlGaN electron supply, AlN etch stop, doped GaN gate
group III-V semiconductor material
gate metal
aluminum nitride
AlN
indium nitride
InN
aluminum oxide
Al₂O₃
gallium oxide
GaO
indium gallium nitride
InGaN
sapphire substrate
| 3.4 eV |
GaN |
— | 50–300 W | — |
Thickness | 1–20 nm | — |