The method of Claim 1, further comprising: cooling the reaction chamber; and removing the device with its deposited layers from the reaction chamber, wherein the steps of cooling and removing are conducted before the step of depositing a source contact and a drain contact.

The method of Claim 1, wherein the reaction chamber is a metal-organic vapor phase epitaxy reaction chamber or a molecular beam epitaxy reaction chamber.

The method of Claim 1, further comprising forming a gate contact in electrical contact with the second active layer.

The method of Claim 1, wherein depositing a passivation layer is performed at a temperature of from about 700 ° C to about 1300 °C.

The method of Claim 1, wherein the passivation layer comprises SiN.

The method of Claim 1, wherein the first active layer comprises a group III nitride semiconductor material.

The method of Claim 1, wherein the first active layer comprises GaN.

The method of Claim 1, wherein the second active layer comprises a group III nitride semiconductor material.

The method of Claim 1, wherein the second active layer comprises AlGaN or AlGaI nN.

The method of Claim 1, wherein the passivation layer is deposited to a thickness of from about 1 nm to about 30 nm.

The method of Claim 1, further comprising depositing a spacer layer between the first active layer and the second active layer, wherein the spacer layer increases mobility in the two-dimensional electron gas layer.

The method of Claim 1, further comprising depositing a third layer between the second active layer and the passivation layer, wherein the third layer is deposited for doping purposes or for increasing carrier density in the channel.

The method of Claim 1, further comprising depositing a buffer layer between the substrate and the first active layer, wherein the buffer layer provides a crystal structure transition atop the substrate.

The method of Claim 1, wherein the substrate comprises a material selected from the group consisting of silicon, sapphire, SiC, GaN, and A lN.

The method of Claim 1, wherein the device is selected from the group consisting of a high electron mobility transistor, a metal oxide semiconductor heterostructure -28- field effect transistor, a metal semiconductor field effect transistor, a metal-insulator- semiconductor field effect transistor, and a metal-insulator-semiconductor heterostructure field effect transistor.

The method of Claim 24, wherein the source contact and the drain contact are deposited directly on the passivation layer.

The method of Claim 24, further comprising: cooling the reaction chamber; and removing the device with its deposited layers from the reaction chamber, wherein the steps of cooling and removing are conducted before the step of depositing a source contact and a drain contact.

The method of Claim 24, wherein the reaction chamber is a metal-organic vapor phase epitaxy reaction chamber or a molecular beam epitaxy reaction chamber.

The method of Claim 24, further comprising forming a gate contact in electrical contact with the second active layer.

The method of Claim 24, wherein depositing a passivation layer is performed at a temperature of from about 700 ° C to about 1300 °C.

The method of Claim 24, wherein the passivation layer comprises SiN.

The method of Claim 24, wherein the first active layer comprises a group III nitride semiconductor material.

The method of Claim 24, wherein the first active layer comprises GaN.

The method of Claim 24, wherein the second active layer comprises a group III nitride semiconductor material.

The method of Claim 24, wherein the second active layer comprises AlGaN or AlGaI nN.

The method of Claim 24, wherein the passivation layer is deposited to a thickness of from about 1 nm to about 30 nm.

The method of Claim 24, further comprising depositing a spacer layer between the first active layer and the second active layer, wherein the spacer layer increases mobility in the two-dimensional electron gas layer.

The method of Claim 24, further comprising depositing a third layer between the second active layer and the passivation layer, wherein the third layer is deposited for doping purposes or for increasing carrier density in the channel.

The method of Claim 24, further comprising depositing a buffer layer between the substrate and the first active layer, wherein the buffer layer provides a crystal structure transition atop the substrate.

The method of Claim 24, wherein the substrate comprises a material selected from the group consisting of silicon, sapphire, SiC, G aN, and A lN.

The method of Claim 24, wherein the device is selected from the group consisting of a high electron mobility transistor, a metal oxide semiconductor heterostructure field effect transistor, a metal semiconductor field effect transistor, a metal-insulator- semiconductor field effect transistor, and a metal-insulator-semiconductor heterostructure field effect transistor.

The method of Claim 24, wherein the first layer comprises G aN grown by metal-organic vapor phase epitaxy, wherein the second layer comprises AlGaN grown by metal-organic vapor phase epitaxy, wherein the substrate is a [0001] sapphire substrate.

The method of Claim 24, f u rther comprising: annealing the substrate in H2; and thereafter nitriding the substrate, wherein the steps of annealing and nitriding are conducted prior to depositing the layers.

The method of Claim 24, wherein depositing a passivation layer comprises growing a SiN layer at a temperature of from about 950 0 C to about 1200 0 C using N H₃ and SiH 4 as starting materials.

The method of Claim 24, f u rther comprising cooling down the substrate then unloading the substrate from the reactor, wherein the steps of cooling down and unloading are conducted after depositing the passivation layer.

The method of Claim 1, further comprising: cooling the reaction chamber; and removing the device with its deposited layers from the reaction chamber, wherein the steps of cooling and removing are conducted before the step of depositing a source contact and a drain contact.

The method of Claim 1, wherein the reaction chamber is a metal-organic vapor phase epitaxy reaction chamber or a molecular beam epitaxy reaction chamber.

The method of Claim 1, further comprising forming a gate contact in electrical contact with the second active layer.

The method of Claim 1, wherein depositing a passivation layer is performed at a temperature of from about 700 ° C to about 1300 °C.

The method of Claim 1, wherein the passivation layer comprises SiN.

The method of Claim 1, wherein the first active layer comprises a group III nitride semiconductor material.

The method of Claim 1, wherein the first active layer comprises GaN.

The method of Claim 1, wherein the second active layer comprises a group III nitride semiconductor material.

The method of Claim 1, wherein the second active layer comprises AlGaN or AlGaI nN.

The method of Claim 1, wherein the passivation layer is deposited to a thickness of from about 1 nm to about 30 nm.

The method of Claim 1, further comprising depositing a spacer layer between the first active layer and the second active layer, wherein the spacer layer increases mobility in the two-dimensional electron gas layer.

The method of Claim 1, further comprising depositing a third layer between the second active layer and the passivation layer, wherein the third layer is deposited for doping purposes or for increasing carrier density in the channel.

The method of Claim 1, further comprising depositing a buffer layer between the substrate and the first active layer, wherein the buffer layer provides a crystal structure transition atop the substrate.

The method of Claim 1, wherein the substrate comprises a material selected from the group consisting of silicon, sapphire, SiC, GaN, and A lN.

The method of Claim 1, wherein the device is selected from the group consisting of a high electron mobility transistor, a metal oxide semiconductor heterostructure -28- field effect transistor, a metal semiconductor field effect transistor, a metal-insulator- semiconductor field effect transistor, and a metal-insulator-semiconductor heterostructure field effect transistor.

The method of Claim 24, wherein the source contact and the drain contact are deposited directly on the passivation layer.

The method of Claim 24, further comprising: cooling the reaction chamber; and removing the device with its deposited layers from the reaction chamber, wherein the steps of cooling and removing are conducted before the step of depositing a source contact and a drain contact.

The method of Claim 24, wherein the reaction chamber is a metal-organic vapor phase epitaxy reaction chamber or a molecular beam epitaxy reaction chamber.

The method of Claim 24, further comprising forming a gate contact in electrical contact with the second active layer.

The method of Claim 24, wherein depositing a passivation layer is performed at a temperature of from about 700 ° C to about 1300 °C.

The method of Claim 24, wherein the passivation layer comprises SiN.

The method of Claim 24, wherein the first active layer comprises a group III nitride semiconductor material.

The method of Claim 24, wherein the first active layer comprises GaN.

The method of Claim 24, wherein the second active layer comprises a group III nitride semiconductor material.

The method of Claim 24, wherein the second active layer comprises AlGaN or AlGaI nN.

The method of Claim 24, wherein the passivation layer is deposited to a thickness of from about 1 nm to about 30 nm.

The method of Claim 24, further comprising depositing a spacer layer between the first active layer and the second active layer, wherein the spacer layer increases mobility in the two-dimensional electron gas layer.

The method of Claim 24, further comprising depositing a third layer between the second active layer and the passivation layer, wherein the third layer is deposited for doping purposes or for increasing carrier density in the channel.

The method of Claim 24, further comprising depositing a buffer layer between the substrate and the first active layer, wherein the buffer layer provides a crystal structure transition atop the substrate.

The method of Claim 24, wherein the substrate comprises a material selected from the group consisting of silicon, sapphire, SiC, G aN, and A lN.

The method of Claim 24, wherein the device is selected from the group consisting of a high electron mobility transistor, a metal oxide semiconductor heterostructure field effect transistor, a metal semiconductor field effect transistor, a metal-insulator- semiconductor field effect transistor, and a metal-insulator-semiconductor heterostructure field effect transistor.

The method of Claim 24, wherein the first layer comprises G aN grown by metal-organic vapor phase epitaxy, wherein the second layer comprises AlGaN grown by metal-organic vapor phase epitaxy, wherein the substrate is a [0001] sapphire substrate.

The method of Claim 24, f u rther comprising: annealing the substrate in H2; and thereafter nitriding the substrate, wherein the steps of annealing and nitriding are conducted prior to depositing the layers.

The method of Claim 24, wherein depositing a passivation layer comprises growing a SiN layer at a temperature of from about 950 0 C to about 1200 0 C using N H₃ and SiH 4 as starting materials.

The method of Claim 24, f u rther comprising cooling down the substrate then unloading the substrate from the reactor, wherein the steps of cooling down and unloading are conducted after depositing the passivation layer.

The method of Claim 1, further comprising: cooling the reaction chamber; and removing the device with its deposited layers from the reaction chamber, wherein the steps of cooling and removing are conducted before the step of depositing a source contact and a drain contact.

The method of Claim 1, wherein the reaction chamber is a metal-organic vapor phase epitaxy reaction chamber or a molecular beam epitaxy reaction chamber.

The method of Claim 1, further comprising forming a gate contact in electrical contact with the second active layer.

The method of Claim 1, wherein depositing a passivation layer is performed at a temperature of from about 700 ° C to about 1300 °C.

The method of Claim 1, wherein the passivation layer comprises SiN.

The method of Claim 1, wherein the first active layer comprises a group III nitride semiconductor material.

The method of Claim 1, wherein the first active layer comprises GaN.

The method of Claim 1, wherein the second active layer comprises a group III nitride semiconductor material.

The method of Claim 1, wherein the second active layer comprises AlGaN or AlGaI nN.

The method of Claim 1, wherein the passivation layer is deposited to a thickness of from about 1 nm to about 30 nm.

The method of Claim 1, further comprising depositing a spacer layer between the first active layer and the second active layer, wherein the spacer layer increases mobility in the two-dimensional electron gas layer.

The method of Claim 1, further comprising depositing a third layer between the second active layer and the passivation layer, wherein the third layer is deposited for doping purposes or for increasing carrier density in the channel.

The method of Claim 1, further comprising depositing a buffer layer between the substrate and the first active layer, wherein the buffer layer provides a crystal structure transition atop the substrate.

The method of Claim 1, wherein the substrate comprises a material selected from the group consisting of silicon, sapphire, SiC, GaN, and A lN.

The method of Claim 1, wherein the device is selected from the group consisting of a high electron mobility transistor, a metal oxide semiconductor heterostructure -28- field effect transistor, a metal semiconductor field effect transistor, a metal-insulator- semiconductor field effect transistor, and a metal-insulator-semiconductor heterostructure field effect transistor.

The method of Claim 24, wherein the source contact and the drain contact are deposited directly on the passivation layer.

The method of Claim 24, further comprising: cooling the reaction chamber; and removing the device with its deposited layers from the reaction chamber, wherein the steps of cooling and removing are conducted before the step of depositing a source contact and a drain contact.

The method of Claim 24, wherein the reaction chamber is a metal-organic vapor phase epitaxy reaction chamber or a molecular beam epitaxy reaction chamber.

The method of Claim 24, further comprising forming a gate contact in electrical contact with the second active layer.

The method of Claim 24, wherein depositing a passivation layer is performed at a temperature of from about 700 ° C to about 1300 °C.

The method of Claim 24, wherein the passivation layer comprises SiN.

The method of Claim 24, wherein the first active layer comprises a group III nitride semiconductor material.

The method of Claim 24, wherein the first active layer comprises GaN.

The method of Claim 24, wherein the second active layer comprises a group III nitride semiconductor material.

The method of Claim 24, wherein the second active layer comprises AlGaN or AlGaI nN.

The method of Claim 24, wherein the passivation layer is deposited to a thickness of from about 1 nm to about 30 nm.

The method of Claim 24, further comprising depositing a spacer layer between the first active layer and the second active layer, wherein the spacer layer increases mobility in the two-dimensional electron gas layer.

The method of Claim 24, further comprising depositing a third layer between the second active layer and the passivation layer, wherein the third layer is deposited for doping purposes or for increasing carrier density in the channel.

The method of Claim 24, further comprising depositing a buffer layer between the substrate and the first active layer, wherein the buffer layer provides a crystal structure transition atop the substrate.

The method of Claim 24, wherein the substrate comprises a material selected from the group consisting of silicon, sapphire, SiC, G aN, and A lN.

The method of Claim 24, wherein the device is selected from the group consisting of a high electron mobility transistor, a metal oxide semiconductor heterostructure field effect transistor, a metal semiconductor field effect transistor, a metal-insulator- semiconductor field effect transistor, and a metal-insulator-semiconductor heterostructure field effect transistor.

The method of Claim 24, wherein the first layer comprises G aN grown by metal-organic vapor phase epitaxy, wherein the second layer comprises AlGaN grown by metal-organic vapor phase epitaxy, wherein the substrate is a [0001] sapphire substrate.

The method of Claim 24, f u rther comprising: annealing the substrate in H2; and thereafter nitriding the substrate, wherein the steps of annealing and nitriding are conducted prior to depositing the layers.

The method of Claim 24, wherein depositing a passivation layer comprises growing a SiN layer at a temperature of from about 950 0 C to about 1200 0 C using N H₃ and SiH 4 as starting materials.

The method of Claim 24, f u rther comprising cooling down the substrate then unloading the substrate from the reactor, wherein the steps of cooling down and unloading are conducted after depositing the passivation layer.

The method of Claim 1, further comprising: cooling the reaction chamber; and removing the device with its deposited layers from the reaction chamber, wherein the steps of cooling and removing are conducted before the step of depositing a source contact and a drain contact.

The method of Claim 1, wherein the reaction chamber is a metal-organic vapor phase epitaxy reaction chamber or a molecular beam epitaxy reaction chamber.

The method of Claim 1, further comprising forming a gate contact in electrical contact with the second active layer.

The method of Claim 1, wherein depositing a passivation layer is performed at a temperature of from about 700 ° C to about 1300 °C.

The method of Claim 1, wherein the passivation layer comprises SiN.

The method of Claim 1, wherein the first active layer comprises a group III nitride semiconductor material.

The method of Claim 1, wherein the first active layer comprises GaN.

The method of Claim 1, wherein the second active layer comprises a group III nitride semiconductor material.

The method of Claim 1, wherein the second active layer comprises AlGaN or AlGaI nN.

The method of Claim 1, wherein the passivation layer is deposited to a thickness of from about 1 nm to about 30 nm.

The method of Claim 1, further comprising depositing a spacer layer between the first active layer and the second active layer, wherein the spacer layer increases mobility in the two-dimensional electron gas layer.

The method of Claim 1, further comprising depositing a third layer between the second active layer and the passivation layer, wherein the third layer is deposited for doping purposes or for increasing carrier density in the channel.

The method of Claim 1, further comprising depositing a buffer layer between the substrate and the first active layer, wherein the buffer layer provides a crystal structure transition atop the substrate.

The method of Claim 1, wherein the substrate comprises a material selected from the group consisting of silicon, sapphire, SiC, GaN, and A lN.

The method of Claim 1, wherein the device is selected from the group consisting of a high electron mobility transistor, a metal oxide semiconductor heterostructure -28- field effect transistor, a metal semiconductor field effect transistor, a metal-insulator- semiconductor field effect transistor, and a metal-insulator-semiconductor heterostructure field effect transistor.

The method of Claim 24, wherein the source contact and the drain contact are deposited directly on the passivation layer.

The method of Claim 24, further comprising: cooling the reaction chamber; and removing the device with its deposited layers from the reaction chamber, wherein the steps of cooling and removing are conducted before the step of depositing a source contact and a drain contact.

The method of Claim 24, wherein the reaction chamber is a metal-organic vapor phase epitaxy reaction chamber or a molecular beam epitaxy reaction chamber.

The method of Claim 24, further comprising forming a gate contact in electrical contact with the second active layer.

The method of Claim 24, wherein depositing a passivation layer is performed at a temperature of from about 700 ° C to about 1300 °C.

The method of Claim 24, wherein the passivation layer comprises SiN.

The method of Claim 24, wherein the first active layer comprises a group III nitride semiconductor material.

The method of Claim 24, wherein the first active layer comprises GaN.

The method of Claim 24, wherein the second active layer comprises a group III nitride semiconductor material.

The method of Claim 24, wherein the second active layer comprises AlGaN or AlGaI nN.

The method of Claim 24, wherein the passivation layer is deposited to a thickness of from about 1 nm to about 30 nm.

The method of Claim 24, further comprising depositing a spacer layer between the first active layer and the second active layer, wherein the spacer layer increases mobility in the two-dimensional electron gas layer.

The method of Claim 24, further comprising depositing a third layer between the second active layer and the passivation layer, wherein the third layer is deposited for doping purposes or for increasing carrier density in the channel.

The method of Claim 24, further comprising depositing a buffer layer between the substrate and the first active layer, wherein the buffer layer provides a crystal structure transition atop the substrate.

The method of Claim 24, wherein the substrate comprises a material selected from the group consisting of silicon, sapphire, SiC, G aN, and A lN.

The method of Claim 24, wherein the device is selected from the group consisting of a high electron mobility transistor, a metal oxide semiconductor heterostructure field effect transistor, a metal semiconductor field effect transistor, a metal-insulator- semiconductor field effect transistor, and a metal-insulator-semiconductor heterostructure field effect transistor.

The method of Claim 24, wherein the first layer comprises G aN grown by metal-organic vapor phase epitaxy, wherein the second layer comprises AlGaN grown by metal-organic vapor phase epitaxy, wherein the substrate is a [0001] sapphire substrate.

The method of Claim 24, f u rther comprising: annealing the substrate in H2; and thereafter nitriding the substrate, wherein the steps of annealing and nitriding are conducted prior to depositing the layers.

The method of Claim 24, wherein depositing a passivation layer comprises growing a SiN layer at a temperature of from about 950 0 C to about 1200 0 C using N H₃ and SiH 4 as starting materials.

The method of Claim 24, f u rther comprising cooling down the substrate then unloading the substrate from the reactor, wherein the steps of cooling down and unloading are conducted after depositing the passivation layer.