Patent
US 12,662,752 B2VACANCY-RICH SILICON FOR USE WITH A GALLIUM NITRIDE EPITAXIAL LAYER
Pu-Fang Chen, Ching Yu Chen
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)·Jun. 23, 2026·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 12,662,752 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a block diagram of a manufacturing system to prepare a semiconductor substrate for an epitaxial layer deposition process, in accordance with some …
FIG. 2 is a flow diagram of a method for fabricating a silicon substrate suitable for a gallium nitride epitaxial layer deposition process, in accordance with …
FIG. 3 is a pictorial view of a silicon ingot, in accordance 45 with some embodiments of the present disclosure.
FIG. 4 is a pictorial magnified view of atomic arrange- ments in a silicon lattice, in accordance with some embodi- ments of the present disclosure.
FIG. 5A is a pictorial view of wafers cut from various 50 portions of the silicon ingot shown in
FIG. 6 is a photo luminescent wafer map, in accordance with some embodiments of the present disclosure.
FIG. 7 is a photograph of a wet-oxidized wafer, in accordance with some embodiments of the present disclo- sure. 60
FIGS. 8A and 8B are micrographs of defects under an optical microscope, in accordance with some embodiments of the present disclosure.
FIG. 9 is a plot of the relationship between V/G and the density of native defects within a silicon crystal ingot, in 65 accordance with some embodiments of …
FIGS. 10A and 10B are wafer maps showing areas of vacancies and self-interstitials, in accordance with some embodiments of the present disclosure.
FIGS. 11A and 11B are cross-wafer plots of concentration profiles for vacancies and self-interstitials, in accordance with some embodiments of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: forming a crystal ingot from a crystal melt by pulling a solid crystal from the crystal melt at a pulling velocity V, the crystal ingot having a central region and an outer radius; while forming the crystal ingot, adjusting a ratio of the pulling velocity V to an axial temperature gradient G(V/G), wherein adjusting the ratio V/G adjusts char-acteristics of self-interstitial defects that form at the outer radius and vacancy defects that form in the central region; selecting a vacancy-rich region of the crystal ingot, wherein the vacancy-rich region comprises an oxida-tion induced stacking fault ring; cutting vacancy-rich semiconductor wafers from the vacancy-rich region of the crystal ingot; and removing the oxidation induced stacking fault ring in the vacancy-rich semiconductor wafers.
The method of claim 1, wherein forming the crystal ingot comprises forming a silicon crystal ingot, and wherein cutting the vacancy-rich semiconductor wafers comprises cutting vacancy-rich silicon wafers.
The method of claim 1, wherein the characteristics of the self-interstitial and vacancy defects comprise one or more of a number of the self-interstitial and vacancy defects, a density of the self-interstitial and vacancy defects, and a distribution of the self-interstitial and vacancy defects.
The method of claim 1, wherein pulling the solid crystal comprises pulling a solid crystal that is suitable for manu-facturing semiconductor devices comprising one or more of silicon, germanium, compound semiconductors, and alloy semiconductors.
The method of claim 1, wherein the ratio V/G is within a range of about 0.00155 cm2/min ° K to about 0.0020 cm2/min ° K.
A method, comprising: identifying vacancy-rich semiconductor wafers from among a group of semiconductor wafers, wherein a peripheral region of each of the vacancy-rich semicon-ductor wafers comprises an oxidation induced stacking fault ring; removing the oxidation induced stacking fault ring by applying an annealing process to the vacancy-rich semiconductor wafers; performing a nitridation operation that exposes the vacancy-rich semiconductor wafers to a nitrogen gas; and epitaxially growing gallium nitride on the annealed vacancy-rich semiconductor wafers.
The method of claim 6, wherein applying the annealing process comprises performing a thermal operation that exposes the vacancy-rich semiconductor wafers to tempera-tures greater than about 1200° C.
The method of claim 6, wherein a gas pressure of the nitridation operation is between about 0.9 atm and about 1.1 atm.
The method of claim 6, further comprising, after the annealing process, evaluating a thermal conductivity of the vacancy-rich semiconductor wafers.
The method of claim 6, further comprising, after the annealing process, evaluating a vacancy density of the vacancy-rich wafers.
The method of claim 6, wherein identifying the vacancy-rich semiconductor wafers comprises evaluating a vacancy density of the group of semiconductor wafers by creating a wafer map showing a profile of oxidation induced stacking faults.
The method of claim 6, wherein epitaxially growing the gallium nitride on the annealed vacancy-rich semicon-ductor wafers comprises epitaxially growing the gallium nitride using a metal-organic chemical vapor deposition process.
A method, comprising: forming a crystal ingot from a crystal melt by pulling a solid crystal from the crystal melt at a pulling velocity V, wherein the crystal ingot comprises a central region and an outer radius; while forming the crystal ingot, adjusting a ratio of the pulling velocity V to an axial temperature gradient G, wherein adjusting a ratio of the pulling velocity V to the axial temperature gradient G (ratio V/G) controls self-interstitial defects that form at the outer radius and vacancy defects that form in the central region; determining a region of the crystal ingot that is vacancy-rich; cutting vacancy-rich wafers from the vacancy-rich region of the crystal ingot; evaluating the vacancy-rich wafers against a set of selec-tion criteria; and removing interstitials in the vacancy-rich wafers.
The method of claim 17, wherein evaluating the vacancy-rich wafers comprises analyzing an image of one or more oxidation induced stacking fault rings around edges of the vacancy-rich wafers.
The method of claim 17, wherein evaluating the vacancy-rich wafers comprises one or more of evaluating a photoluminescent wafer map, inspecting an oxidized wafer, and inspecting defects on a Secco-etched wafer.
The method of claim 17, further comprising removing oxidation induced stacking fault rings in the vacancy-rich wafers. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si epitaxial substrate
Materials described outside the worked examples.
silicon
Si
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
V/G ratio for vacancy-rich crystal growth | 0.00155–0.002 cm2/min·K | Si |
High-temperature annealing temperature for OISF ring removal | ≥ 1200 °C |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 18
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,662,752 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a block diagram of a manufacturing system to prepare a semiconductor substrate for an epitaxial layer deposition process, in accordance with some …
FIG. 2 is a flow diagram of a method for fabricating a silicon substrate suitable for a gallium nitride epitaxial layer deposition process, in accordance with …
FIG. 3 is a pictorial view of a silicon ingot, in accordance 45 with some embodiments of the present disclosure.
FIG. 4 is a pictorial magnified view of atomic arrange- ments in a silicon lattice, in accordance with some embodi- ments of the present disclosure.
FIG. 5A is a pictorial view of wafers cut from various 50 portions of the silicon ingot shown in
FIG. 6 is a photo luminescent wafer map, in accordance with some embodiments of the present disclosure.
FIG. 7 is a photograph of a wet-oxidized wafer, in accordance with some embodiments of the present disclo- sure. 60
FIGS. 8A and 8B are micrographs of defects under an optical microscope, in accordance with some embodiments of the present disclosure.
FIG. 9 is a plot of the relationship between V/G and the density of native defects within a silicon crystal ingot, in 65 accordance with some embodiments of …
FIGS. 10A and 10B are wafer maps showing areas of vacancies and self-interstitials, in accordance with some embodiments of the present disclosure.
FIGS. 11A and 11B are cross-wafer plots of concentration profiles for vacancies and self-interstitials, in accordance with some embodiments of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: forming a crystal ingot from a crystal melt by pulling a solid crystal from the crystal melt at a pulling velocity V, the crystal ingot having a central region and an outer radius; while forming the crystal ingot, adjusting a ratio of the pulling velocity V to an axial temperature gradient G(V/G), wherein adjusting the ratio V/G adjusts char-acteristics of self-interstitial defects that form at the outer radius and vacancy defects that form in the central region; selecting a vacancy-rich region of the crystal ingot, wherein the vacancy-rich region comprises an oxida-tion induced stacking fault ring; cutting vacancy-rich semiconductor wafers from the vacancy-rich region of the crystal ingot; and removing the oxidation induced stacking fault ring in the vacancy-rich semiconductor wafers.
The method of claim 1, wherein forming the crystal ingot comprises forming a silicon crystal ingot, and wherein cutting the vacancy-rich semiconductor wafers comprises cutting vacancy-rich silicon wafers.
The method of claim 1, wherein the characteristics of the self-interstitial and vacancy defects comprise one or more of a number of the self-interstitial and vacancy defects, a density of the self-interstitial and vacancy defects, and a distribution of the self-interstitial and vacancy defects.
The method of claim 1, wherein pulling the solid crystal comprises pulling a solid crystal that is suitable for manu-facturing semiconductor devices comprising one or more of silicon, germanium, compound semiconductors, and alloy semiconductors.
The method of claim 1, wherein the ratio V/G is within a range of about 0.00155 cm2/min ° K to about 0.0020 cm2/min ° K.
A method, comprising: identifying vacancy-rich semiconductor wafers from among a group of semiconductor wafers, wherein a peripheral region of each of the vacancy-rich semicon-ductor wafers comprises an oxidation induced stacking fault ring; removing the oxidation induced stacking fault ring by applying an annealing process to the vacancy-rich semiconductor wafers; performing a nitridation operation that exposes the vacancy-rich semiconductor wafers to a nitrogen gas; and epitaxially growing gallium nitride on the annealed vacancy-rich semiconductor wafers.
The method of claim 6, wherein applying the annealing process comprises performing a thermal operation that exposes the vacancy-rich semiconductor wafers to tempera-tures greater than about 1200° C.
The method of claim 6, wherein a gas pressure of the nitridation operation is between about 0.9 atm and about 1.1 atm.
The method of claim 6, further comprising, after the annealing process, evaluating a thermal conductivity of the vacancy-rich semiconductor wafers.
The method of claim 6, further comprising, after the annealing process, evaluating a vacancy density of the vacancy-rich wafers.
The method of claim 6, wherein identifying the vacancy-rich semiconductor wafers comprises evaluating a vacancy density of the group of semiconductor wafers by creating a wafer map showing a profile of oxidation induced stacking faults.
The method of claim 6, wherein epitaxially growing the gallium nitride on the annealed vacancy-rich semicon-ductor wafers comprises epitaxially growing the gallium nitride using a metal-organic chemical vapor deposition process.
A method, comprising: forming a crystal ingot from a crystal melt by pulling a solid crystal from the crystal melt at a pulling velocity V, wherein the crystal ingot comprises a central region and an outer radius; while forming the crystal ingot, adjusting a ratio of the pulling velocity V to an axial temperature gradient G, wherein adjusting a ratio of the pulling velocity V to the axial temperature gradient G (ratio V/G) controls self-interstitial defects that form at the outer radius and vacancy defects that form in the central region; determining a region of the crystal ingot that is vacancy-rich; cutting vacancy-rich wafers from the vacancy-rich region of the crystal ingot; evaluating the vacancy-rich wafers against a set of selec-tion criteria; and removing interstitials in the vacancy-rich wafers.
The method of claim 17, wherein evaluating the vacancy-rich wafers comprises analyzing an image of one or more oxidation induced stacking fault rings around edges of the vacancy-rich wafers.
The method of claim 17, wherein evaluating the vacancy-rich wafers comprises one or more of evaluating a photoluminescent wafer map, inspecting an oxidized wafer, and inspecting defects on a Secco-etched wafer.
The method of claim 17, further comprising removing oxidation induced stacking fault rings in the vacancy-rich wafers. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si epitaxial substrate
Materials described outside the worked examples.
silicon
Si
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
V/G ratio for vacancy-rich crystal growth | 0.00155–0.002 cm2/min·K | Si |
High-temperature annealing temperature for OISF ring removal | ≥ 1200 °C |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 18
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,662,752 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a block diagram of a manufacturing system to prepare a semiconductor substrate for an epitaxial layer deposition process, in accordance with some …
FIG. 2 is a flow diagram of a method for fabricating a silicon substrate suitable for a gallium nitride epitaxial layer deposition process, in accordance with …
FIG. 3 is a pictorial view of a silicon ingot, in accordance 45 with some embodiments of the present disclosure.
FIG. 4 is a pictorial magnified view of atomic arrange- ments in a silicon lattice, in accordance with some embodi- ments of the present disclosure.
FIG. 5A is a pictorial view of wafers cut from various 50 portions of the silicon ingot shown in
FIG. 6 is a photo luminescent wafer map, in accordance with some embodiments of the present disclosure.
FIG. 7 is a photograph of a wet-oxidized wafer, in accordance with some embodiments of the present disclo- sure. 60
FIGS. 8A and 8B are micrographs of defects under an optical microscope, in accordance with some embodiments of the present disclosure.
FIG. 9 is a plot of the relationship between V/G and the density of native defects within a silicon crystal ingot, in 65 accordance with some embodiments of …
FIGS. 10A and 10B are wafer maps showing areas of vacancies and self-interstitials, in accordance with some embodiments of the present disclosure.
FIGS. 11A and 11B are cross-wafer plots of concentration profiles for vacancies and self-interstitials, in accordance with some embodiments of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: forming a crystal ingot from a crystal melt by pulling a solid crystal from the crystal melt at a pulling velocity V, the crystal ingot having a central region and an outer radius; while forming the crystal ingot, adjusting a ratio of the pulling velocity V to an axial temperature gradient G(V/G), wherein adjusting the ratio V/G adjusts char-acteristics of self-interstitial defects that form at the outer radius and vacancy defects that form in the central region; selecting a vacancy-rich region of the crystal ingot, wherein the vacancy-rich region comprises an oxida-tion induced stacking fault ring; cutting vacancy-rich semiconductor wafers from the vacancy-rich region of the crystal ingot; and removing the oxidation induced stacking fault ring in the vacancy-rich semiconductor wafers.
The method of claim 1, wherein forming the crystal ingot comprises forming a silicon crystal ingot, and wherein cutting the vacancy-rich semiconductor wafers comprises cutting vacancy-rich silicon wafers.
The method of claim 1, wherein the characteristics of the self-interstitial and vacancy defects comprise one or more of a number of the self-interstitial and vacancy defects, a density of the self-interstitial and vacancy defects, and a distribution of the self-interstitial and vacancy defects.
The method of claim 1, wherein pulling the solid crystal comprises pulling a solid crystal that is suitable for manu-facturing semiconductor devices comprising one or more of silicon, germanium, compound semiconductors, and alloy semiconductors.
The method of claim 1, wherein the ratio V/G is within a range of about 0.00155 cm2/min ° K to about 0.0020 cm2/min ° K.
A method, comprising: identifying vacancy-rich semiconductor wafers from among a group of semiconductor wafers, wherein a peripheral region of each of the vacancy-rich semicon-ductor wafers comprises an oxidation induced stacking fault ring; removing the oxidation induced stacking fault ring by applying an annealing process to the vacancy-rich semiconductor wafers; performing a nitridation operation that exposes the vacancy-rich semiconductor wafers to a nitrogen gas; and epitaxially growing gallium nitride on the annealed vacancy-rich semiconductor wafers.
The method of claim 6, wherein applying the annealing process comprises performing a thermal operation that exposes the vacancy-rich semiconductor wafers to tempera-tures greater than about 1200° C.
The method of claim 6, wherein a gas pressure of the nitridation operation is between about 0.9 atm and about 1.1 atm.
The method of claim 6, further comprising, after the annealing process, evaluating a thermal conductivity of the vacancy-rich semiconductor wafers.
The method of claim 6, further comprising, after the annealing process, evaluating a vacancy density of the vacancy-rich wafers.
The method of claim 6, wherein identifying the vacancy-rich semiconductor wafers comprises evaluating a vacancy density of the group of semiconductor wafers by creating a wafer map showing a profile of oxidation induced stacking faults.
The method of claim 6, wherein epitaxially growing the gallium nitride on the annealed vacancy-rich semicon-ductor wafers comprises epitaxially growing the gallium nitride using a metal-organic chemical vapor deposition process.
A method, comprising: forming a crystal ingot from a crystal melt by pulling a solid crystal from the crystal melt at a pulling velocity V, wherein the crystal ingot comprises a central region and an outer radius; while forming the crystal ingot, adjusting a ratio of the pulling velocity V to an axial temperature gradient G, wherein adjusting a ratio of the pulling velocity V to the axial temperature gradient G (ratio V/G) controls self-interstitial defects that form at the outer radius and vacancy defects that form in the central region; determining a region of the crystal ingot that is vacancy-rich; cutting vacancy-rich wafers from the vacancy-rich region of the crystal ingot; evaluating the vacancy-rich wafers against a set of selec-tion criteria; and removing interstitials in the vacancy-rich wafers.
The method of claim 17, wherein evaluating the vacancy-rich wafers comprises analyzing an image of one or more oxidation induced stacking fault rings around edges of the vacancy-rich wafers.
The method of claim 17, wherein evaluating the vacancy-rich wafers comprises one or more of evaluating a photoluminescent wafer map, inspecting an oxidized wafer, and inspecting defects on a Secco-etched wafer.
The method of claim 17, further comprising removing oxidation induced stacking fault rings in the vacancy-rich wafers. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si epitaxial substrate
Materials described outside the worked examples.
silicon
Si
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
V/G ratio for vacancy-rich crystal growth | 0.00155–0.002 cm2/min·K | Si |
High-temperature annealing temperature for OISF ring removal | ≥ 1200 °C |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 18
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,662,752 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a block diagram of a manufacturing system to prepare a semiconductor substrate for an epitaxial layer deposition process, in accordance with some …
FIG. 2 is a flow diagram of a method for fabricating a silicon substrate suitable for a gallium nitride epitaxial layer deposition process, in accordance with …
FIG. 3 is a pictorial view of a silicon ingot, in accordance 45 with some embodiments of the present disclosure.
FIG. 4 is a pictorial magnified view of atomic arrange- ments in a silicon lattice, in accordance with some embodi- ments of the present disclosure.
FIG. 5A is a pictorial view of wafers cut from various 50 portions of the silicon ingot shown in
FIG. 6 is a photo luminescent wafer map, in accordance with some embodiments of the present disclosure.
FIG. 7 is a photograph of a wet-oxidized wafer, in accordance with some embodiments of the present disclo- sure. 60
FIGS. 8A and 8B are micrographs of defects under an optical microscope, in accordance with some embodiments of the present disclosure.
FIG. 9 is a plot of the relationship between V/G and the density of native defects within a silicon crystal ingot, in 65 accordance with some embodiments of …
FIGS. 10A and 10B are wafer maps showing areas of vacancies and self-interstitials, in accordance with some embodiments of the present disclosure.
FIGS. 11A and 11B are cross-wafer plots of concentration profiles for vacancies and self-interstitials, in accordance with some embodiments of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: forming a crystal ingot from a crystal melt by pulling a solid crystal from the crystal melt at a pulling velocity V, the crystal ingot having a central region and an outer radius; while forming the crystal ingot, adjusting a ratio of the pulling velocity V to an axial temperature gradient G(V/G), wherein adjusting the ratio V/G adjusts char-acteristics of self-interstitial defects that form at the outer radius and vacancy defects that form in the central region; selecting a vacancy-rich region of the crystal ingot, wherein the vacancy-rich region comprises an oxida-tion induced stacking fault ring; cutting vacancy-rich semiconductor wafers from the vacancy-rich region of the crystal ingot; and removing the oxidation induced stacking fault ring in the vacancy-rich semiconductor wafers.
The method of claim 1, wherein forming the crystal ingot comprises forming a silicon crystal ingot, and wherein cutting the vacancy-rich semiconductor wafers comprises cutting vacancy-rich silicon wafers.
The method of claim 1, wherein the characteristics of the self-interstitial and vacancy defects comprise one or more of a number of the self-interstitial and vacancy defects, a density of the self-interstitial and vacancy defects, and a distribution of the self-interstitial and vacancy defects.
The method of claim 1, wherein pulling the solid crystal comprises pulling a solid crystal that is suitable for manu-facturing semiconductor devices comprising one or more of silicon, germanium, compound semiconductors, and alloy semiconductors.
The method of claim 1, wherein the ratio V/G is within a range of about 0.00155 cm2/min ° K to about 0.0020 cm2/min ° K.
A method, comprising: identifying vacancy-rich semiconductor wafers from among a group of semiconductor wafers, wherein a peripheral region of each of the vacancy-rich semicon-ductor wafers comprises an oxidation induced stacking fault ring; removing the oxidation induced stacking fault ring by applying an annealing process to the vacancy-rich semiconductor wafers; performing a nitridation operation that exposes the vacancy-rich semiconductor wafers to a nitrogen gas; and epitaxially growing gallium nitride on the annealed vacancy-rich semiconductor wafers.
The method of claim 6, wherein applying the annealing process comprises performing a thermal operation that exposes the vacancy-rich semiconductor wafers to tempera-tures greater than about 1200° C.
The method of claim 6, wherein a gas pressure of the nitridation operation is between about 0.9 atm and about 1.1 atm.
The method of claim 6, further comprising, after the annealing process, evaluating a thermal conductivity of the vacancy-rich semiconductor wafers.
The method of claim 6, further comprising, after the annealing process, evaluating a vacancy density of the vacancy-rich wafers.
The method of claim 6, wherein identifying the vacancy-rich semiconductor wafers comprises evaluating a vacancy density of the group of semiconductor wafers by creating a wafer map showing a profile of oxidation induced stacking faults.
The method of claim 6, wherein epitaxially growing the gallium nitride on the annealed vacancy-rich semicon-ductor wafers comprises epitaxially growing the gallium nitride using a metal-organic chemical vapor deposition process.
A method, comprising: forming a crystal ingot from a crystal melt by pulling a solid crystal from the crystal melt at a pulling velocity V, wherein the crystal ingot comprises a central region and an outer radius; while forming the crystal ingot, adjusting a ratio of the pulling velocity V to an axial temperature gradient G, wherein adjusting a ratio of the pulling velocity V to the axial temperature gradient G (ratio V/G) controls self-interstitial defects that form at the outer radius and vacancy defects that form in the central region; determining a region of the crystal ingot that is vacancy-rich; cutting vacancy-rich wafers from the vacancy-rich region of the crystal ingot; evaluating the vacancy-rich wafers against a set of selec-tion criteria; and removing interstitials in the vacancy-rich wafers.
The method of claim 17, wherein evaluating the vacancy-rich wafers comprises analyzing an image of one or more oxidation induced stacking fault rings around edges of the vacancy-rich wafers.
The method of claim 17, wherein evaluating the vacancy-rich wafers comprises one or more of evaluating a photoluminescent wafer map, inspecting an oxidized wafer, and inspecting defects on a Secco-etched wafer.
The method of claim 17, further comprising removing oxidation induced stacking fault rings in the vacancy-rich wafers. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si epitaxial substrate
Materials described outside the worked examples.
silicon
Si
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
V/G ratio for vacancy-rich crystal growth | 0.00155–0.002 cm2/min·K | Si |
High-temperature annealing temperature for OISF ring removal | ≥ 1200 °C |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 18
Related documents with shared materials, methods, properties, or citations.
germanium
Ge
nitrogen gas
N₂
silicon carbide
SiC
gallium arsenide
GaAs
High-temperature phase duration of annealing | 60–200 seconds | Si |
Gas pressure during nitridation operation | 0.9–1.1 atm | SiN₂ |
Pressure | 12–15 pa | — |
Thickness | 149.5–150.5 mm | — |
Thickness | 980–1020 µm | — |
Temperature | 1200–1280 °C | — |
Thickness | ≤ 30 µm | — |
Pressure | ≤ 150 pa | — |
Cited non-patent literature · 5
germanium
Ge
nitrogen gas
N₂
silicon carbide
SiC
gallium arsenide
GaAs
High-temperature phase duration of annealing | 60–200 seconds | Si |
Gas pressure during nitridation operation | 0.9–1.1 atm | SiN₂ |
Pressure | 12–15 pa | — |
Thickness | 149.5–150.5 mm | — |
Thickness | 980–1020 µm | — |
Temperature | 1200–1280 °C | — |
Thickness | ≤ 30 µm | — |
Pressure | ≤ 150 pa | — |
Cited non-patent literature · 5
germanium
Ge
nitrogen gas
N₂
silicon carbide
SiC
gallium arsenide
GaAs
High-temperature phase duration of annealing | 60–200 seconds | Si |
Gas pressure during nitridation operation | 0.9–1.1 atm | SiN₂ |
Pressure | 12–15 pa | — |
Thickness | 149.5–150.5 mm | — |
Thickness | 980–1020 µm | — |
Temperature | 1200–1280 °C | — |
Thickness | ≤ 30 µm | — |
Pressure | ≤ 150 pa | — |
Cited non-patent literature · 5
germanium
Ge
nitrogen gas
N₂
silicon carbide
SiC
gallium arsenide
GaAs
High-temperature phase duration of annealing | 60–200 seconds | Si |
Gas pressure during nitridation operation | 0.9–1.1 atm | SiN₂ |
Pressure | 12–15 pa | — |
Thickness | 149.5–150.5 mm | — |
Thickness | 980–1020 µm | — |
Temperature | 1200–1280 °C | — |
Thickness | ≤ 30 µm | — |
Pressure | ≤ 150 pa | — |
Cited non-patent literature · 5