Patent
US 10,141,409Thin film transistor and producing method thereof, and array substrate
Dacheng ZHANG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
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US 10,141,409Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A producing method of a thin film transistor, comprising steps of: forming a gate electrode composed of graphene; forming a gate insulating layer composed of oxidized graphene; forming an active region composed of doped oxidized graphene or doped graphene; forming a source electrode and a drain electrode composed of graphene, wherein, the graphene composing the source electrode, the drain electrode and the gate electrode is for m ed by reducing oxidized graphene, and the doped oxidized graphene composing the active region is formed by a first treating pf oxidized graphene; or the doped graphene composing the active region is formed by a second treating g f oxidized graphene. Currently amended
The p r oducing method of the thin film transistor according to claim 1, wherein, the step of forming a gate electrode composed of graphene includes: form ing a first oxidized graphene material layer; reducing the first oxidized graphene material layer to obtain a first graphene material layer, patterning the first graphene material layer to form the gate electrode; or patterning the first oxidized graphene material layer, and reducing the patterned first oxidized graphene material layer, to form the gate electrode. Original
The producing method of the thin film transistor according to claim 1, wherein, the step of forming a gate insulating layer composed of oxidized graphene includes: forming a second oxidized graphene material layer, and taking the second oxidized graphene material layer as the gate insulating layer. Original
The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped oxidized graphene includes: forming a third oxidized graphene material layer; doping the third oxidized graphene material layer, to obtain a doped oxidized graphene material layer, patterning the doped oxidized graphene material layer to form the active region; or patterning the third oxidized graphene material layer, and doping the patterned third oxidized graphene material layer, to form the active region. Original
5. (Origin al) The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped graphene includes: forming a third oxidized grap h ene material layer; reducing the third oxidi ze d graphene material layer, and then doping the same, to obtain the doped graphene material layer, patte rn ing the doped graphene material layer, to form the active region; or patte rn ing the third oxidized graphene material layer, reducing the patterned third oxidized graphene material layer, and then doping the same, to form the active region. Original
(Original) The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped oxidized graphene includes: forming a third oxidized graphene material layer; forming a photoresist layer on the third oxidized graphene material layer, the photoresist layer including polymethyl methacrylate, heating to 50* C to 100 * C so that polymethyl methacryl at e penetrates into the third oxidized graphene material layer, and the third oxidized graphene material layer become a doped oxidized graphene material layer; patterning the doped oxidized graphene material layer by a photolithography process, to form the active region. Original
(Original) The producing method of the thin film transistor according to claim 1, wherein, the step of fo r ming an active region composed of doped graphene includes: forming a third oxidized graphene material layer; reducing the third oxidized graphene material layer, to obtain a second graphene material layer, and then forming a photoresist layer on the second graphene material layer, the photoresist layer including polymethyl methacrylate, heating to 50* C to 100 * C so that polymethyl met h acrylate penetrates into the second graphene material layer, and the second graphene material layer become a doped graphene material layer; patterning the doped graphene material layer by a photolithogra p hy process, to form the active region. Original
The producing method of the thin film transistor according to claim 1, whe re in, the step of fo rm ing a source electrode and a drain electrode composed of graphene includes: forming a fourth oxidized graphene material layer; reducing the fourth oxidized g r aphene material layer to obtain a third graphene material layer; patterning the third graphene material layer to f the source electrode and the drain electrode; or, patte rn ing the fourth oxidized graphene material layer, and reducing the patterned fourth oxidized graphene material layer to fo rm the source electrode and the drain electrode. Original
The producing method of the thin film transistor according to claim 1, wherein, the step of forming a gate insulating l ayer composed of oxidized graphene and the step of forming an active region composed of doped oxidized graphene include: forming a fifth oxidized graphene material layer; performing a treatment including doping and patterning to an upper layer portion of the f fifh oxidized graphene material layer, to obtain the active region composed of doped oxidized graphene; a portion of the fifth oxidized graphene material layer without being performed the treatment composes the gate insulating layer. Original
The producing method of the thin film transistor according to claim 1, whe re in, the step of fo rm ing a gate insulating layer composed of oxidized graphene and the step of forming an active region composed of doped graphene include: forming a fifth oxidized graphene material layer; performing a treatment including reducing, doping and patte rn ing to an upper layer portion of the fifth oxidized graphene material layer, to obtain the active region composed of doped graphene; a portion of the fifth oxidized graphene material layer without being performed the treatment composes the gate insulating layer. Original
11. The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped graphene and the step of for m ing a source electrode and a drain electrode composed of graphene include: forming a sixth oxidized graphene material layer; reducing the sixth oxidized graphene material layer to obtain a fourth graphene material layer; performing a treatment including patte rn ing and doping to the fourth graphene material layer, to obtain the source electrode, the drain electrode and the active region, wherein, the patterning is performed so that the fourth graphene material layer for m s a pattern including the sour ce electrode, the drain electrode and the active region, and doping is perfo ed so as to dope a portion corresponding to the active region. Original
(Previously Presented) A thin film transistor, comprising: a source electrode, a drain electrode, a gate electrode, an active region and a gate insulating layer, wherein, the source electrode, the drain electrode and the gate electrode are composed of graphene, the active region is composed of doped oxidized graphene, the gate insulating layer is composed of oxidized graphene, and wherein, the graphene composing the source electrode, the drain electrode and the gate electrode is fo r med by reducing oxidized graphene, and the doped oxidized graphene composing the active region is fo ed by treating oxidized graphene. Previously presented
The thin film transistor according to claim 12, wherein, doped oxidized graphene composing the active region is for m ed by doping oxidized graphene. Original
(O riginal) The thin film tra n sistor according to claim 12, wherein, doped graphene composing the active region is formed by reducing oxidized graphene, and then doping the same. Original
(O riginal) The thin film transistor according to claim 12, wherein, the source electrode and the drain electrode have a thickness in a range of 1 nm to 100 n m, and/or, the gate electrode has a thickness in a range of I nm to 100 nm, and/or, the active region has a thickness in a range of 1 nm to 100 nm, and/or, the gate insulating layer has a thickness in a range of 30 nm to 300 nm. Original
(Previously Presented) An a r ray substrate, comprising: the thin film transistor according to claim 12. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
thin film transistor (method)
thin film transistor (device)
Materials described outside the worked examples.
graphene (reduced from oxidized graphene)
oxidized graphene
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
source/drain electrode thickness | 1–100 nm | graphene (reduced from oxidized graphene) |
gate electrode thickness | 1–100 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,141,409Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A producing method of a thin film transistor, comprising steps of: forming a gate electrode composed of graphene; forming a gate insulating layer composed of oxidized graphene; forming an active region composed of doped oxidized graphene or doped graphene; forming a source electrode and a drain electrode composed of graphene, wherein, the graphene composing the source electrode, the drain electrode and the gate electrode is for m ed by reducing oxidized graphene, and the doped oxidized graphene composing the active region is formed by a first treating pf oxidized graphene; or the doped graphene composing the active region is formed by a second treating g f oxidized graphene. Currently amended
The p r oducing method of the thin film transistor according to claim 1, wherein, the step of forming a gate electrode composed of graphene includes: form ing a first oxidized graphene material layer; reducing the first oxidized graphene material layer to obtain a first graphene material layer, patterning the first graphene material layer to form the gate electrode; or patterning the first oxidized graphene material layer, and reducing the patterned first oxidized graphene material layer, to form the gate electrode. Original
The producing method of the thin film transistor according to claim 1, wherein, the step of forming a gate insulating layer composed of oxidized graphene includes: forming a second oxidized graphene material layer, and taking the second oxidized graphene material layer as the gate insulating layer. Original
The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped oxidized graphene includes: forming a third oxidized graphene material layer; doping the third oxidized graphene material layer, to obtain a doped oxidized graphene material layer, patterning the doped oxidized graphene material layer to form the active region; or patterning the third oxidized graphene material layer, and doping the patterned third oxidized graphene material layer, to form the active region. Original
5. (Origin al) The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped graphene includes: forming a third oxidized grap h ene material layer; reducing the third oxidi ze d graphene material layer, and then doping the same, to obtain the doped graphene material layer, patte rn ing the doped graphene material layer, to form the active region; or patte rn ing the third oxidized graphene material layer, reducing the patterned third oxidized graphene material layer, and then doping the same, to form the active region. Original
(Original) The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped oxidized graphene includes: forming a third oxidized graphene material layer; forming a photoresist layer on the third oxidized graphene material layer, the photoresist layer including polymethyl methacrylate, heating to 50* C to 100 * C so that polymethyl methacryl at e penetrates into the third oxidized graphene material layer, and the third oxidized graphene material layer become a doped oxidized graphene material layer; patterning the doped oxidized graphene material layer by a photolithography process, to form the active region. Original
(Original) The producing method of the thin film transistor according to claim 1, wherein, the step of fo r ming an active region composed of doped graphene includes: forming a third oxidized graphene material layer; reducing the third oxidized graphene material layer, to obtain a second graphene material layer, and then forming a photoresist layer on the second graphene material layer, the photoresist layer including polymethyl methacrylate, heating to 50* C to 100 * C so that polymethyl met h acrylate penetrates into the second graphene material layer, and the second graphene material layer become a doped graphene material layer; patterning the doped graphene material layer by a photolithogra p hy process, to form the active region. Original
The producing method of the thin film transistor according to claim 1, whe re in, the step of fo rm ing a source electrode and a drain electrode composed of graphene includes: forming a fourth oxidized graphene material layer; reducing the fourth oxidized g r aphene material layer to obtain a third graphene material layer; patterning the third graphene material layer to f the source electrode and the drain electrode; or, patte rn ing the fourth oxidized graphene material layer, and reducing the patterned fourth oxidized graphene material layer to fo rm the source electrode and the drain electrode. Original
The producing method of the thin film transistor according to claim 1, wherein, the step of forming a gate insulating l ayer composed of oxidized graphene and the step of forming an active region composed of doped oxidized graphene include: forming a fifth oxidized graphene material layer; performing a treatment including doping and patterning to an upper layer portion of the f fifh oxidized graphene material layer, to obtain the active region composed of doped oxidized graphene; a portion of the fifth oxidized graphene material layer without being performed the treatment composes the gate insulating layer. Original
The producing method of the thin film transistor according to claim 1, whe re in, the step of fo rm ing a gate insulating layer composed of oxidized graphene and the step of forming an active region composed of doped graphene include: forming a fifth oxidized graphene material layer; performing a treatment including reducing, doping and patte rn ing to an upper layer portion of the fifth oxidized graphene material layer, to obtain the active region composed of doped graphene; a portion of the fifth oxidized graphene material layer without being performed the treatment composes the gate insulating layer. Original
11. The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped graphene and the step of for m ing a source electrode and a drain electrode composed of graphene include: forming a sixth oxidized graphene material layer; reducing the sixth oxidized graphene material layer to obtain a fourth graphene material layer; performing a treatment including patte rn ing and doping to the fourth graphene material layer, to obtain the source electrode, the drain electrode and the active region, wherein, the patterning is performed so that the fourth graphene material layer for m s a pattern including the sour ce electrode, the drain electrode and the active region, and doping is perfo ed so as to dope a portion corresponding to the active region. Original
(Previously Presented) A thin film transistor, comprising: a source electrode, a drain electrode, a gate electrode, an active region and a gate insulating layer, wherein, the source electrode, the drain electrode and the gate electrode are composed of graphene, the active region is composed of doped oxidized graphene, the gate insulating layer is composed of oxidized graphene, and wherein, the graphene composing the source electrode, the drain electrode and the gate electrode is fo r med by reducing oxidized graphene, and the doped oxidized graphene composing the active region is fo ed by treating oxidized graphene. Previously presented
The thin film transistor according to claim 12, wherein, doped oxidized graphene composing the active region is for m ed by doping oxidized graphene. Original
(O riginal) The thin film tra n sistor according to claim 12, wherein, doped graphene composing the active region is formed by reducing oxidized graphene, and then doping the same. Original
(O riginal) The thin film transistor according to claim 12, wherein, the source electrode and the drain electrode have a thickness in a range of 1 nm to 100 n m, and/or, the gate electrode has a thickness in a range of I nm to 100 nm, and/or, the active region has a thickness in a range of 1 nm to 100 nm, and/or, the gate insulating layer has a thickness in a range of 30 nm to 300 nm. Original
(Previously Presented) An a r ray substrate, comprising: the thin film transistor according to claim 12. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
thin film transistor (method)
thin film transistor (device)
Materials described outside the worked examples.
graphene (reduced from oxidized graphene)
oxidized graphene
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
source/drain electrode thickness | 1–100 nm | graphene (reduced from oxidized graphene) |
gate electrode thickness | 1–100 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,141,409Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A producing method of a thin film transistor, comprising steps of: forming a gate electrode composed of graphene; forming a gate insulating layer composed of oxidized graphene; forming an active region composed of doped oxidized graphene or doped graphene; forming a source electrode and a drain electrode composed of graphene, wherein, the graphene composing the source electrode, the drain electrode and the gate electrode is for m ed by reducing oxidized graphene, and the doped oxidized graphene composing the active region is formed by a first treating pf oxidized graphene; or the doped graphene composing the active region is formed by a second treating g f oxidized graphene. Currently amended
The p r oducing method of the thin film transistor according to claim 1, wherein, the step of forming a gate electrode composed of graphene includes: form ing a first oxidized graphene material layer; reducing the first oxidized graphene material layer to obtain a first graphene material layer, patterning the first graphene material layer to form the gate electrode; or patterning the first oxidized graphene material layer, and reducing the patterned first oxidized graphene material layer, to form the gate electrode. Original
The producing method of the thin film transistor according to claim 1, wherein, the step of forming a gate insulating layer composed of oxidized graphene includes: forming a second oxidized graphene material layer, and taking the second oxidized graphene material layer as the gate insulating layer. Original
The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped oxidized graphene includes: forming a third oxidized graphene material layer; doping the third oxidized graphene material layer, to obtain a doped oxidized graphene material layer, patterning the doped oxidized graphene material layer to form the active region; or patterning the third oxidized graphene material layer, and doping the patterned third oxidized graphene material layer, to form the active region. Original
5. (Origin al) The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped graphene includes: forming a third oxidized grap h ene material layer; reducing the third oxidi ze d graphene material layer, and then doping the same, to obtain the doped graphene material layer, patte rn ing the doped graphene material layer, to form the active region; or patte rn ing the third oxidized graphene material layer, reducing the patterned third oxidized graphene material layer, and then doping the same, to form the active region. Original
(Original) The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped oxidized graphene includes: forming a third oxidized graphene material layer; forming a photoresist layer on the third oxidized graphene material layer, the photoresist layer including polymethyl methacrylate, heating to 50* C to 100 * C so that polymethyl methacryl at e penetrates into the third oxidized graphene material layer, and the third oxidized graphene material layer become a doped oxidized graphene material layer; patterning the doped oxidized graphene material layer by a photolithography process, to form the active region. Original
(Original) The producing method of the thin film transistor according to claim 1, wherein, the step of fo r ming an active region composed of doped graphene includes: forming a third oxidized graphene material layer; reducing the third oxidized graphene material layer, to obtain a second graphene material layer, and then forming a photoresist layer on the second graphene material layer, the photoresist layer including polymethyl methacrylate, heating to 50* C to 100 * C so that polymethyl met h acrylate penetrates into the second graphene material layer, and the second graphene material layer become a doped graphene material layer; patterning the doped graphene material layer by a photolithogra p hy process, to form the active region. Original
The producing method of the thin film transistor according to claim 1, whe re in, the step of fo rm ing a source electrode and a drain electrode composed of graphene includes: forming a fourth oxidized graphene material layer; reducing the fourth oxidized g r aphene material layer to obtain a third graphene material layer; patterning the third graphene material layer to f the source electrode and the drain electrode; or, patte rn ing the fourth oxidized graphene material layer, and reducing the patterned fourth oxidized graphene material layer to fo rm the source electrode and the drain electrode. Original
The producing method of the thin film transistor according to claim 1, wherein, the step of forming a gate insulating l ayer composed of oxidized graphene and the step of forming an active region composed of doped oxidized graphene include: forming a fifth oxidized graphene material layer; performing a treatment including doping and patterning to an upper layer portion of the f fifh oxidized graphene material layer, to obtain the active region composed of doped oxidized graphene; a portion of the fifth oxidized graphene material layer without being performed the treatment composes the gate insulating layer. Original
The producing method of the thin film transistor according to claim 1, whe re in, the step of fo rm ing a gate insulating layer composed of oxidized graphene and the step of forming an active region composed of doped graphene include: forming a fifth oxidized graphene material layer; performing a treatment including reducing, doping and patte rn ing to an upper layer portion of the fifth oxidized graphene material layer, to obtain the active region composed of doped graphene; a portion of the fifth oxidized graphene material layer without being performed the treatment composes the gate insulating layer. Original
11. The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped graphene and the step of for m ing a source electrode and a drain electrode composed of graphene include: forming a sixth oxidized graphene material layer; reducing the sixth oxidized graphene material layer to obtain a fourth graphene material layer; performing a treatment including patte rn ing and doping to the fourth graphene material layer, to obtain the source electrode, the drain electrode and the active region, wherein, the patterning is performed so that the fourth graphene material layer for m s a pattern including the sour ce electrode, the drain electrode and the active region, and doping is perfo ed so as to dope a portion corresponding to the active region. Original
(Previously Presented) A thin film transistor, comprising: a source electrode, a drain electrode, a gate electrode, an active region and a gate insulating layer, wherein, the source electrode, the drain electrode and the gate electrode are composed of graphene, the active region is composed of doped oxidized graphene, the gate insulating layer is composed of oxidized graphene, and wherein, the graphene composing the source electrode, the drain electrode and the gate electrode is fo r med by reducing oxidized graphene, and the doped oxidized graphene composing the active region is fo ed by treating oxidized graphene. Previously presented
The thin film transistor according to claim 12, wherein, doped oxidized graphene composing the active region is for m ed by doping oxidized graphene. Original
(O riginal) The thin film tra n sistor according to claim 12, wherein, doped graphene composing the active region is formed by reducing oxidized graphene, and then doping the same. Original
(O riginal) The thin film transistor according to claim 12, wherein, the source electrode and the drain electrode have a thickness in a range of 1 nm to 100 n m, and/or, the gate electrode has a thickness in a range of I nm to 100 nm, and/or, the active region has a thickness in a range of 1 nm to 100 nm, and/or, the gate insulating layer has a thickness in a range of 30 nm to 300 nm. Original
(Previously Presented) An a r ray substrate, comprising: the thin film transistor according to claim 12. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
thin film transistor (method)
thin film transistor (device)
Materials described outside the worked examples.
graphene (reduced from oxidized graphene)
oxidized graphene
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
source/drain electrode thickness | 1–100 nm | graphene (reduced from oxidized graphene) |
gate electrode thickness | 1–100 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,141,409Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A producing method of a thin film transistor, comprising steps of: forming a gate electrode composed of graphene; forming a gate insulating layer composed of oxidized graphene; forming an active region composed of doped oxidized graphene or doped graphene; forming a source electrode and a drain electrode composed of graphene, wherein, the graphene composing the source electrode, the drain electrode and the gate electrode is for m ed by reducing oxidized graphene, and the doped oxidized graphene composing the active region is formed by a first treating pf oxidized graphene; or the doped graphene composing the active region is formed by a second treating g f oxidized graphene. Currently amended
The p r oducing method of the thin film transistor according to claim 1, wherein, the step of forming a gate electrode composed of graphene includes: form ing a first oxidized graphene material layer; reducing the first oxidized graphene material layer to obtain a first graphene material layer, patterning the first graphene material layer to form the gate electrode; or patterning the first oxidized graphene material layer, and reducing the patterned first oxidized graphene material layer, to form the gate electrode. Original
The producing method of the thin film transistor according to claim 1, wherein, the step of forming a gate insulating layer composed of oxidized graphene includes: forming a second oxidized graphene material layer, and taking the second oxidized graphene material layer as the gate insulating layer. Original
The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped oxidized graphene includes: forming a third oxidized graphene material layer; doping the third oxidized graphene material layer, to obtain a doped oxidized graphene material layer, patterning the doped oxidized graphene material layer to form the active region; or patterning the third oxidized graphene material layer, and doping the patterned third oxidized graphene material layer, to form the active region. Original
5. (Origin al) The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped graphene includes: forming a third oxidized grap h ene material layer; reducing the third oxidi ze d graphene material layer, and then doping the same, to obtain the doped graphene material layer, patte rn ing the doped graphene material layer, to form the active region; or patte rn ing the third oxidized graphene material layer, reducing the patterned third oxidized graphene material layer, and then doping the same, to form the active region. Original
(Original) The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped oxidized graphene includes: forming a third oxidized graphene material layer; forming a photoresist layer on the third oxidized graphene material layer, the photoresist layer including polymethyl methacrylate, heating to 50* C to 100 * C so that polymethyl methacryl at e penetrates into the third oxidized graphene material layer, and the third oxidized graphene material layer become a doped oxidized graphene material layer; patterning the doped oxidized graphene material layer by a photolithography process, to form the active region. Original
(Original) The producing method of the thin film transistor according to claim 1, wherein, the step of fo r ming an active region composed of doped graphene includes: forming a third oxidized graphene material layer; reducing the third oxidized graphene material layer, to obtain a second graphene material layer, and then forming a photoresist layer on the second graphene material layer, the photoresist layer including polymethyl methacrylate, heating to 50* C to 100 * C so that polymethyl met h acrylate penetrates into the second graphene material layer, and the second graphene material layer become a doped graphene material layer; patterning the doped graphene material layer by a photolithogra p hy process, to form the active region. Original
The producing method of the thin film transistor according to claim 1, whe re in, the step of fo rm ing a source electrode and a drain electrode composed of graphene includes: forming a fourth oxidized graphene material layer; reducing the fourth oxidized g r aphene material layer to obtain a third graphene material layer; patterning the third graphene material layer to f the source electrode and the drain electrode; or, patte rn ing the fourth oxidized graphene material layer, and reducing the patterned fourth oxidized graphene material layer to fo rm the source electrode and the drain electrode. Original
The producing method of the thin film transistor according to claim 1, wherein, the step of forming a gate insulating l ayer composed of oxidized graphene and the step of forming an active region composed of doped oxidized graphene include: forming a fifth oxidized graphene material layer; performing a treatment including doping and patterning to an upper layer portion of the f fifh oxidized graphene material layer, to obtain the active region composed of doped oxidized graphene; a portion of the fifth oxidized graphene material layer without being performed the treatment composes the gate insulating layer. Original
The producing method of the thin film transistor according to claim 1, whe re in, the step of fo rm ing a gate insulating layer composed of oxidized graphene and the step of forming an active region composed of doped graphene include: forming a fifth oxidized graphene material layer; performing a treatment including reducing, doping and patte rn ing to an upper layer portion of the fifth oxidized graphene material layer, to obtain the active region composed of doped graphene; a portion of the fifth oxidized graphene material layer without being performed the treatment composes the gate insulating layer. Original
11. The producing method of the thin film transistor according to claim 1, wherein, the step of forming an active region composed of doped graphene and the step of for m ing a source electrode and a drain electrode composed of graphene include: forming a sixth oxidized graphene material layer; reducing the sixth oxidized graphene material layer to obtain a fourth graphene material layer; performing a treatment including patte rn ing and doping to the fourth graphene material layer, to obtain the source electrode, the drain electrode and the active region, wherein, the patterning is performed so that the fourth graphene material layer for m s a pattern including the sour ce electrode, the drain electrode and the active region, and doping is perfo ed so as to dope a portion corresponding to the active region. Original
(Previously Presented) A thin film transistor, comprising: a source electrode, a drain electrode, a gate electrode, an active region and a gate insulating layer, wherein, the source electrode, the drain electrode and the gate electrode are composed of graphene, the active region is composed of doped oxidized graphene, the gate insulating layer is composed of oxidized graphene, and wherein, the graphene composing the source electrode, the drain electrode and the gate electrode is fo r med by reducing oxidized graphene, and the doped oxidized graphene composing the active region is fo ed by treating oxidized graphene. Previously presented
The thin film transistor according to claim 12, wherein, doped oxidized graphene composing the active region is for m ed by doping oxidized graphene. Original
(O riginal) The thin film tra n sistor according to claim 12, wherein, doped graphene composing the active region is formed by reducing oxidized graphene, and then doping the same. Original
(O riginal) The thin film transistor according to claim 12, wherein, the source electrode and the drain electrode have a thickness in a range of 1 nm to 100 n m, and/or, the gate electrode has a thickness in a range of I nm to 100 nm, and/or, the active region has a thickness in a range of 1 nm to 100 nm, and/or, the gate insulating layer has a thickness in a range of 30 nm to 300 nm. Original
(Previously Presented) An a r ray substrate, comprising: the thin film transistor according to claim 12. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
thin film transistor (method)
thin film transistor (device)
Materials described outside the worked examples.
graphene (reduced from oxidized graphene)
oxidized graphene
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
source/drain electrode thickness | 1–100 nm | graphene (reduced from oxidized graphene) |
gate electrode thickness | 1–100 nm |
Related documents with shared materials, methods, properties, or citations.
doped graphene
polymethyl methacrylate (PMMA)
active region thickness | 1–100 nm | doped oxidized graphene |
gate insulating layer thickness | 30–300 nm | oxidized graphene |
doped graphene
polymethyl methacrylate (PMMA)
active region thickness | 1–100 nm | doped oxidized graphene |
gate insulating layer thickness | 30–300 nm | oxidized graphene |
doped graphene
polymethyl methacrylate (PMMA)
active region thickness | 1–100 nm | doped oxidized graphene |
gate insulating layer thickness | 30–300 nm | oxidized graphene |
doped graphene
polymethyl methacrylate (PMMA)
active region thickness | 1–100 nm | doped oxidized graphene |
gate insulating layer thickness | 30–300 nm | oxidized graphene |