Patent
US 9,418,938SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Masayuki KITAMURA
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,418,938Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1. and 2 are exec uted, t hereby f ormin g the via hole 18. S ubsequently, the step of
FIG. 2 is a schematic cross-sectiona l view for explainin g par t of the semiconductor device manu f acturing m ethod according to the first embodiment
FIG. 3 is a s c hemat i c c r oss-sectional view for 5 explainin g part of the sem i conduc t or device manufac turi ng method accor ding to t he fir st embod …
FIG. 4 is a schemat ic cr os s-sect i onal view for explain ing part of the semicond uct or device manufacturing method according to the first embo d iment; 10 …
FIG. 5 is a schematic cross-sectional vie w showing the structure of a se miconductor device accordin g to a 10 first modification of the first emb o dimen u. In …
FIG. 6 is a schematic cross-sec ti onal v iew showin g the struct ure of a se m iconductor device ac c ording -t o a second modification of the first em …
FIG. 7 is executed. In the s tep of F IG. 7, an impurity (phosphorus) is introduc ed i n to the grap hene intercon n ect 14 from the lateral surface of the via …
FIG. 8 i s a sc hematic cross-sectional v iew showing a se micon duct o r device according to the second embodim ent. I n the second embod i ment, the elements …
FIGS. 9 and 1 0 are cross-s e ctional views schema t ically sho wing the sem i con duc tor d evice m anufactur i ng method of the third embodiment. Firstly, …
FIG. 10 is a schematic cross-sectional vie w for 30 explaining part of the semiconduct or device manufac t urin g method according to the third embodiment; and …
FIG. 11, the dia meter of each dum my v ia c ondu cti ng port ion 30 is f ormed smaller than 25 the inter conn ect wid th of the graphene interconnect 14, an d …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a graphene interconnect; an insulation film formed on the graphene interconnect; and a via conducting portion formed in a via hole provided in the graphene interconnect and the insulation film, wherein the graphene interconnect has a region containing an impurity at least around the via hole.
The semiconductor device of claim 1, wherein a bottom of the via hole is positioned deeper than a bottom of the graphene interconnect.
The semiconductor device of claim 1, wherein a bottom of the via hole is positioned shallower than a bottom of the graphene interconnect.
The semiconductor device of claim 1, wherein a bottom of the via hole is substantially level with a bottom of the graphene interconnect.
The semiconductor device of claim 1, further comprising an underlying film formed beneath the graphene interconnect, wherein the via hole is extended into the underlying film.
The semiconductor device of claim 1, wherein at least a bottom of the via conducting portion has a diameter smaller than a width of the graphene interconnect.
canceled
The semiconductor device of claim [[7]] 1, wherein a concentration of the impurity decreases as a distance from the via hole increases.
The semiconductor device of claim [[7]] 1, wherein the region containing the impurity contains at least one element selected from phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb), bismuth (Bi), fluorine (F), chlorine (C l), bromine (Br), iodine (1), astatine (At), hydrogen (H) and boron (B).
The semiconductor device of claim [[7]] 1, wherein the graphene interconnect and the insulation film have a dummy via hole in which a dummy via conducting portion is provided.
The semiconductor device of claim 10, wherein the graphene interconnect has a region containing an impurity around the dummy via hole, and a concentration of the impurity decreases as a distance from the dummy via hole increases.
A method of manufacturing a semiconductor device, comprising: forming a graphene interconnect; forming an insulation film on the graphene interconnect; forming a via hole in the graphene interconnect and the insulation film; and forming a via conducting portion in the via hole. withdrawn
The method of claim 12, wherein a bottom of the via hole is positioned deeper than a bottom of the graphene interconnect. withdrawn
The method of claim 12, wherein a bottom of the via hole is positioned shallower than a bottom of the graphene interconnect. withdrawn
The method of claim 12, wherein a bottom of the via hole is substantially level with a bottom of the graphene interconnect. withdrawn
The method of claim 12, further comprising introducing an impurity into the graphene interconnect from a lateral surface of the via hole. withdrawn
A method of manufacturing a semiconductor device, comprising: forming a graphene interconnect; forming a hole in the graphene interconnect; introducing an impurity into the graphene interconnect from a lateral surface of the hole; and forming a conducting portion in the hole. withdrawn
The method of claim 19, wherein forming the hole in the graphene interconnect includes forming a plurality of holes in the graphene interconnect along an interconnect length direction of the graphene interconnect. -6- withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with graphene interconnect and via conducting portion
Materials described outside the worked examples.
graphene interconnect
insulation film
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1. and 2 are exec uted, t hereby f ormin g the via hole 18. S ubsequently, the step of
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,418,938Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1. and 2 are exec uted, t hereby f ormin g the via hole 18. S ubsequently, the step of
FIG. 2 is a schematic cross-sectiona l view for explainin g par t of the semiconductor device manu f acturing m ethod according to the first embodiment
FIG. 3 is a s c hemat i c c r oss-sectional view for 5 explainin g part of the sem i conduc t or device manufac turi ng method accor ding to t he fir st embod …
FIG. 4 is a schemat ic cr os s-sect i onal view for explain ing part of the semicond uct or device manufacturing method according to the first embo d iment; 10 …
FIG. 5 is a schematic cross-sectional vie w showing the structure of a se miconductor device accordin g to a 10 first modification of the first emb o dimen u. In …
FIG. 6 is a schematic cross-sec ti onal v iew showin g the struct ure of a se m iconductor device ac c ording -t o a second modification of the first em …
FIG. 7 is executed. In the s tep of F IG. 7, an impurity (phosphorus) is introduc ed i n to the grap hene intercon n ect 14 from the lateral surface of the via …
FIG. 8 i s a sc hematic cross-sectional v iew showing a se micon duct o r device according to the second embodim ent. I n the second embod i ment, the elements …
FIGS. 9 and 1 0 are cross-s e ctional views schema t ically sho wing the sem i con duc tor d evice m anufactur i ng method of the third embodiment. Firstly, …
FIG. 10 is a schematic cross-sectional vie w for 30 explaining part of the semiconduct or device manufac t urin g method according to the third embodiment; and …
FIG. 11, the dia meter of each dum my v ia c ondu cti ng port ion 30 is f ormed smaller than 25 the inter conn ect wid th of the graphene interconnect 14, an d …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a graphene interconnect; an insulation film formed on the graphene interconnect; and a via conducting portion formed in a via hole provided in the graphene interconnect and the insulation film, wherein the graphene interconnect has a region containing an impurity at least around the via hole.
The semiconductor device of claim 1, wherein a bottom of the via hole is positioned deeper than a bottom of the graphene interconnect.
The semiconductor device of claim 1, wherein a bottom of the via hole is positioned shallower than a bottom of the graphene interconnect.
The semiconductor device of claim 1, wherein a bottom of the via hole is substantially level with a bottom of the graphene interconnect.
The semiconductor device of claim 1, further comprising an underlying film formed beneath the graphene interconnect, wherein the via hole is extended into the underlying film.
The semiconductor device of claim 1, wherein at least a bottom of the via conducting portion has a diameter smaller than a width of the graphene interconnect.
canceled
The semiconductor device of claim [[7]] 1, wherein a concentration of the impurity decreases as a distance from the via hole increases.
The semiconductor device of claim [[7]] 1, wherein the region containing the impurity contains at least one element selected from phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb), bismuth (Bi), fluorine (F), chlorine (C l), bromine (Br), iodine (1), astatine (At), hydrogen (H) and boron (B).
The semiconductor device of claim [[7]] 1, wherein the graphene interconnect and the insulation film have a dummy via hole in which a dummy via conducting portion is provided.
The semiconductor device of claim 10, wherein the graphene interconnect has a region containing an impurity around the dummy via hole, and a concentration of the impurity decreases as a distance from the dummy via hole increases.
A method of manufacturing a semiconductor device, comprising: forming a graphene interconnect; forming an insulation film on the graphene interconnect; forming a via hole in the graphene interconnect and the insulation film; and forming a via conducting portion in the via hole. withdrawn
The method of claim 12, wherein a bottom of the via hole is positioned deeper than a bottom of the graphene interconnect. withdrawn
The method of claim 12, wherein a bottom of the via hole is positioned shallower than a bottom of the graphene interconnect. withdrawn
The method of claim 12, wherein a bottom of the via hole is substantially level with a bottom of the graphene interconnect. withdrawn
The method of claim 12, further comprising introducing an impurity into the graphene interconnect from a lateral surface of the via hole. withdrawn
A method of manufacturing a semiconductor device, comprising: forming a graphene interconnect; forming a hole in the graphene interconnect; introducing an impurity into the graphene interconnect from a lateral surface of the hole; and forming a conducting portion in the hole. withdrawn
The method of claim 19, wherein forming the hole in the graphene interconnect includes forming a plurality of holes in the graphene interconnect along an interconnect length direction of the graphene interconnect. -6- withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with graphene interconnect and via conducting portion
Materials described outside the worked examples.
graphene interconnect
insulation film
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1. and 2 are exec uted, t hereby f ormin g the via hole 18. S ubsequently, the step of
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,418,938Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1. and 2 are exec uted, t hereby f ormin g the via hole 18. S ubsequently, the step of
FIG. 2 is a schematic cross-sectiona l view for explainin g par t of the semiconductor device manu f acturing m ethod according to the first embodiment
FIG. 3 is a s c hemat i c c r oss-sectional view for 5 explainin g part of the sem i conduc t or device manufac turi ng method accor ding to t he fir st embod …
FIG. 4 is a schemat ic cr os s-sect i onal view for explain ing part of the semicond uct or device manufacturing method according to the first embo d iment; 10 …
FIG. 5 is a schematic cross-sectional vie w showing the structure of a se miconductor device accordin g to a 10 first modification of the first emb o dimen u. In …
FIG. 6 is a schematic cross-sec ti onal v iew showin g the struct ure of a se m iconductor device ac c ording -t o a second modification of the first em …
FIG. 7 is executed. In the s tep of F IG. 7, an impurity (phosphorus) is introduc ed i n to the grap hene intercon n ect 14 from the lateral surface of the via …
FIG. 8 i s a sc hematic cross-sectional v iew showing a se micon duct o r device according to the second embodim ent. I n the second embod i ment, the elements …
FIGS. 9 and 1 0 are cross-s e ctional views schema t ically sho wing the sem i con duc tor d evice m anufactur i ng method of the third embodiment. Firstly, …
FIG. 10 is a schematic cross-sectional vie w for 30 explaining part of the semiconduct or device manufac t urin g method according to the third embodiment; and …
FIG. 11, the dia meter of each dum my v ia c ondu cti ng port ion 30 is f ormed smaller than 25 the inter conn ect wid th of the graphene interconnect 14, an d …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a graphene interconnect; an insulation film formed on the graphene interconnect; and a via conducting portion formed in a via hole provided in the graphene interconnect and the insulation film, wherein the graphene interconnect has a region containing an impurity at least around the via hole.
The semiconductor device of claim 1, wherein a bottom of the via hole is positioned deeper than a bottom of the graphene interconnect.
The semiconductor device of claim 1, wherein a bottom of the via hole is positioned shallower than a bottom of the graphene interconnect.
The semiconductor device of claim 1, wherein a bottom of the via hole is substantially level with a bottom of the graphene interconnect.
The semiconductor device of claim 1, further comprising an underlying film formed beneath the graphene interconnect, wherein the via hole is extended into the underlying film.
The semiconductor device of claim 1, wherein at least a bottom of the via conducting portion has a diameter smaller than a width of the graphene interconnect.
canceled
The semiconductor device of claim [[7]] 1, wherein a concentration of the impurity decreases as a distance from the via hole increases.
The semiconductor device of claim [[7]] 1, wherein the region containing the impurity contains at least one element selected from phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb), bismuth (Bi), fluorine (F), chlorine (C l), bromine (Br), iodine (1), astatine (At), hydrogen (H) and boron (B).
The semiconductor device of claim [[7]] 1, wherein the graphene interconnect and the insulation film have a dummy via hole in which a dummy via conducting portion is provided.
The semiconductor device of claim 10, wherein the graphene interconnect has a region containing an impurity around the dummy via hole, and a concentration of the impurity decreases as a distance from the dummy via hole increases.
A method of manufacturing a semiconductor device, comprising: forming a graphene interconnect; forming an insulation film on the graphene interconnect; forming a via hole in the graphene interconnect and the insulation film; and forming a via conducting portion in the via hole. withdrawn
The method of claim 12, wherein a bottom of the via hole is positioned deeper than a bottom of the graphene interconnect. withdrawn
The method of claim 12, wherein a bottom of the via hole is positioned shallower than a bottom of the graphene interconnect. withdrawn
The method of claim 12, wherein a bottom of the via hole is substantially level with a bottom of the graphene interconnect. withdrawn
The method of claim 12, further comprising introducing an impurity into the graphene interconnect from a lateral surface of the via hole. withdrawn
A method of manufacturing a semiconductor device, comprising: forming a graphene interconnect; forming a hole in the graphene interconnect; introducing an impurity into the graphene interconnect from a lateral surface of the hole; and forming a conducting portion in the hole. withdrawn
The method of claim 19, wherein forming the hole in the graphene interconnect includes forming a plurality of holes in the graphene interconnect along an interconnect length direction of the graphene interconnect. -6- withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with graphene interconnect and via conducting portion
Materials described outside the worked examples.
graphene interconnect
insulation film
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1. and 2 are exec uted, t hereby f ormin g the via hole 18. S ubsequently, the step of
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,418,938Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1. and 2 are exec uted, t hereby f ormin g the via hole 18. S ubsequently, the step of
FIG. 2 is a schematic cross-sectiona l view for explainin g par t of the semiconductor device manu f acturing m ethod according to the first embodiment
FIG. 3 is a s c hemat i c c r oss-sectional view for 5 explainin g part of the sem i conduc t or device manufac turi ng method accor ding to t he fir st embod …
FIG. 4 is a schemat ic cr os s-sect i onal view for explain ing part of the semicond uct or device manufacturing method according to the first embo d iment; 10 …
FIG. 5 is a schematic cross-sectional vie w showing the structure of a se miconductor device accordin g to a 10 first modification of the first emb o dimen u. In …
FIG. 6 is a schematic cross-sec ti onal v iew showin g the struct ure of a se m iconductor device ac c ording -t o a second modification of the first em …
FIG. 7 is executed. In the s tep of F IG. 7, an impurity (phosphorus) is introduc ed i n to the grap hene intercon n ect 14 from the lateral surface of the via …
FIG. 8 i s a sc hematic cross-sectional v iew showing a se micon duct o r device according to the second embodim ent. I n the second embod i ment, the elements …
FIGS. 9 and 1 0 are cross-s e ctional views schema t ically sho wing the sem i con duc tor d evice m anufactur i ng method of the third embodiment. Firstly, …
FIG. 10 is a schematic cross-sectional vie w for 30 explaining part of the semiconduct or device manufac t urin g method according to the third embodiment; and …
FIG. 11, the dia meter of each dum my v ia c ondu cti ng port ion 30 is f ormed smaller than 25 the inter conn ect wid th of the graphene interconnect 14, an d …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a graphene interconnect; an insulation film formed on the graphene interconnect; and a via conducting portion formed in a via hole provided in the graphene interconnect and the insulation film, wherein the graphene interconnect has a region containing an impurity at least around the via hole.
The semiconductor device of claim 1, wherein a bottom of the via hole is positioned deeper than a bottom of the graphene interconnect.
The semiconductor device of claim 1, wherein a bottom of the via hole is positioned shallower than a bottom of the graphene interconnect.
The semiconductor device of claim 1, wherein a bottom of the via hole is substantially level with a bottom of the graphene interconnect.
The semiconductor device of claim 1, further comprising an underlying film formed beneath the graphene interconnect, wherein the via hole is extended into the underlying film.
The semiconductor device of claim 1, wherein at least a bottom of the via conducting portion has a diameter smaller than a width of the graphene interconnect.
canceled
The semiconductor device of claim [[7]] 1, wherein a concentration of the impurity decreases as a distance from the via hole increases.
The semiconductor device of claim [[7]] 1, wherein the region containing the impurity contains at least one element selected from phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb), bismuth (Bi), fluorine (F), chlorine (C l), bromine (Br), iodine (1), astatine (At), hydrogen (H) and boron (B).
The semiconductor device of claim [[7]] 1, wherein the graphene interconnect and the insulation film have a dummy via hole in which a dummy via conducting portion is provided.
The semiconductor device of claim 10, wherein the graphene interconnect has a region containing an impurity around the dummy via hole, and a concentration of the impurity decreases as a distance from the dummy via hole increases.
A method of manufacturing a semiconductor device, comprising: forming a graphene interconnect; forming an insulation film on the graphene interconnect; forming a via hole in the graphene interconnect and the insulation film; and forming a via conducting portion in the via hole. withdrawn
The method of claim 12, wherein a bottom of the via hole is positioned deeper than a bottom of the graphene interconnect. withdrawn
The method of claim 12, wherein a bottom of the via hole is positioned shallower than a bottom of the graphene interconnect. withdrawn
The method of claim 12, wherein a bottom of the via hole is substantially level with a bottom of the graphene interconnect. withdrawn
The method of claim 12, further comprising introducing an impurity into the graphene interconnect from a lateral surface of the via hole. withdrawn
A method of manufacturing a semiconductor device, comprising: forming a graphene interconnect; forming a hole in the graphene interconnect; introducing an impurity into the graphene interconnect from a lateral surface of the hole; and forming a conducting portion in the hole. withdrawn
The method of claim 19, wherein forming the hole in the graphene interconnect includes forming a plurality of holes in the graphene interconnect along an interconnect length direction of the graphene interconnect. -6- withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with graphene interconnect and via conducting portion
Materials described outside the worked examples.
graphene interconnect
insulation film
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1. and 2 are exec uted, t hereby f ormin g the via hole 18. S ubsequently, the step of
Related documents with shared materials, methods, properties, or citations.
underlying film
impurity dopant
multilayer graphene
SOG (spin-on glass)
barrier metal (Ti/TaN stacked film)
Ni (nickel) catalytic layer
Ni
outer conducting portion of via
inner conducting portion of via
FIG. 3 is a s c hemat i c c r oss-sectional view for 5 explainin g part of the sem i conduc t or device manufac turi ng method accor ding to t he fir st embod …
FIGS. 9 and 1 0 are cross-s e ctional views schema t ically sho wing the sem i con duc tor d evice m anufactur i ng method of the third embodiment. Firstly, …
underlying film
impurity dopant
multilayer graphene
SOG (spin-on glass)
barrier metal (Ti/TaN stacked film)
Ni (nickel) catalytic layer
Ni
outer conducting portion of via
inner conducting portion of via
FIG. 3 is a s c hemat i c c r oss-sectional view for 5 explainin g part of the sem i conduc t or device manufac turi ng method accor ding to t he fir st embod …
FIGS. 9 and 1 0 are cross-s e ctional views schema t ically sho wing the sem i con duc tor d evice m anufactur i ng method of the third embodiment. Firstly, …
underlying film
impurity dopant
multilayer graphene
SOG (spin-on glass)
barrier metal (Ti/TaN stacked film)
Ni (nickel) catalytic layer
Ni
outer conducting portion of via
inner conducting portion of via
FIG. 3 is a s c hemat i c c r oss-sectional view for 5 explainin g part of the sem i conduc t or device manufac turi ng method accor ding to t he fir st embod …
FIGS. 9 and 1 0 are cross-s e ctional views schema t ically sho wing the sem i con duc tor d evice m anufactur i ng method of the third embodiment. Firstly, …
underlying film
impurity dopant
multilayer graphene
SOG (spin-on glass)
barrier metal (Ti/TaN stacked film)
Ni (nickel) catalytic layer
Ni
outer conducting portion of via
inner conducting portion of via
FIG. 3 is a s c hemat i c c r oss-sectional view for 5 explainin g part of the sem i conduc t or device manufac turi ng method accor ding to t he fir st embod …
FIGS. 9 and 1 0 are cross-s e ctional views schema t ically sho wing the sem i con duc tor d evice m anufactur i ng method of the third embodiment. Firstly, …